- g -

• GarnetExtLink() : GarnetExtLink
• GarnetIntLink() : GarnetIntLink
• GarnetNetwork() : GarnetNetwork
• GarnetSyntheticTraffic() : GarnetSyntheticTraffic
• GarnetSyntheticTrafficSenderState() : GarnetSyntheticTraffic::GarnetSyntheticTrafficSenderState
• GdbCommand() : BaseRemoteGDB::GdbCommand
• gdbRegs() : AlphaISA::RemoteGDB , ArmISA::RemoteGDB , BaseRemoteGDB , MipsISA::RemoteGDB , PowerISA::RemoteGDB , RiscvISA::RemoteGDB , SparcISA::RemoteGDB , X86ISA::RemoteGDB
• gdtSize() : X86ISA::X86Process
• gdtStart() : X86ISA::X86Process
• gem5_getPort() : FastModel::AmbaFromTlmBridge64 , FastModel::AmbaToTlmBridge64 , FastModel::ScxEvsCortexA76< Types > , sc_core::sc_module , sc_gem5::Gem5ToTlmBridge< BITWIDTH > , sc_gem5::TlmToGem5Bridge< BITWIDTH >
• Gem5Extension() : Gem5SystemC::Gem5Extension
• Gem5ToTlmBridge() : sc_gem5::Gem5ToTlmBridge< BITWIDTH >
• gen() : sc_gem5::UniqueNameGen
• generalExceptionsToAArch64() : ArmISA::ArmStaticInst
• GeneralProtection() : X86ISA::GeneralProtection
• generateDisassembly() : ArmISA::ArmStaticInst , ArmISA::BranchEret64 , ArmISA::BranchEretA64 , ArmISA::BranchImm64 , ArmISA::BranchImm , ArmISA::BranchImmCond64 , ArmISA::BranchImmImmReg64 , ArmISA::BranchImmReg64 , ArmISA::BranchReg64 , ArmISA::BranchReg , ArmISA::BranchRegReg64 , ArmISA::BranchRegReg , ArmISA::BranchRet64 , ArmISA::BranchRetA64 , ArmISA::DataImmOp , ArmISA::DataRegOp , ArmISA::DataRegRegOp , ArmISA::DataX1Reg2ImmOp , ArmISA::DataX1RegImmOp , ArmISA::DataX1RegOp , ArmISA::DataX2RegImmOp , ArmISA::DataX2RegOp , ArmISA::DataX3RegOp , ArmISA::DataXCondCompImmOp , ArmISA::DataXCondCompRegOp , ArmISA::DataXCondSelOp , ArmISA::DataXERegOp , ArmISA::DataXImmOnlyOp , ArmISA::DataXImmOp , ArmISA::DataXSRegOp , ArmISA::FpCondCompRegOp , ArmISA::FpCondSelOp , ArmISA::FpRegImmOp , ArmISA::FpRegRegImmOp , ArmISA::FpRegRegOp , ArmISA::FpRegRegRegCondOp , ArmISA::FpRegRegRegImmOp , ArmISA::FpRegRegRegOp , ArmISA::FpRegRegRegRegOp , ArmISA::MemoryDImm64 , ArmISA::MemoryDImmEx64 , ArmISA::MemoryEx64 , ArmISA::MemoryImm64 , ArmISA::MemoryLiteral64 , ArmISA::MemoryOffset< Base > , ArmISA::MemoryPostIndex64 , ArmISA::MemoryPostIndex< Base > , ArmISA::MemoryPreIndex64 , ArmISA::MemoryPreIndex< Base > , ArmISA::MemoryRaw64 , ArmISA::MemoryReg64 , ArmISA::MicroIntImmOp , ArmISA::MicroIntImmXOp , ArmISA::MicroIntMov , ArmISA::MicroIntOp , ArmISA::MicroIntRegXOp , ArmISA::MicroMemOp , ArmISA::MicroMemPairOp , ArmISA::MicroSetPCCPSR , ArmISA::PredImmOp , ArmISA::PredIntOp , ArmISA::PredMacroOp , ArmISA::RfeOp , ArmISA::SrsOp , ArmISA::SveAdrOp , ArmISA::SveBinConstrPredOp , ArmISA::SveBinDestrPredOp , ArmISA::SveBinIdxUnpredOp , ArmISA::SveBinImmIdxUnpredOp , ArmISA::SveBinImmPredOp , ArmISA::SveBinImmUnpredConstrOp , ArmISA::SveBinImmUnpredDestrOp , ArmISA::SveBinUnpredOp , ArmISA::SveBinWideImmUnpredOp , ArmISA::SveCmpImmOp , ArmISA::SveCmpOp , ArmISA::SveComplexIdxOp , ArmISA::SveComplexOp , ArmISA::SveCompTermOp , ArmISA::SveContigMemSI , ArmISA::SveContigMemSS , ArmISA::SveDotProdIdxOp , ArmISA::SveDotProdOp , ArmISA::SveElemCountOp , ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType > , ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType > , ArmISA::SveIndexIIOp , ArmISA::SveIndexIROp , ArmISA::SveIndexRIOp , ArmISA::SveIndexRROp , ArmISA::SveIntCmpImmOp , ArmISA::SveIntCmpOp , ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType > , ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType > , ArmISA::SveMemPredFillSpill , ArmISA::SveMemVecFillSpill , ArmISA::SveOrdReducOp , ArmISA::SvePartBrkOp , ArmISA::SvePartBrkPropOp , ArmISA::SvePredBinPermOp , ArmISA::SvePredCountOp , ArmISA::SvePredCountPredOp , ArmISA::SvePredLogicalOp , ArmISA::SvePredTestOp , ArmISA::SvePredUnaryWImplicitDstOp , ArmISA::SvePredUnaryWImplicitSrcOp , ArmISA::SvePredUnaryWImplicitSrcPredOp , ArmISA::SvePtrueOp , ArmISA::SveReducOp , ArmISA::SveSelectOp , ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType > , ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType > , ArmISA::SveTblOp , ArmISA::SveTerImmUnpredOp , ArmISA::SveTerPredOp , ArmISA::SveUnaryPredOp , ArmISA::SveUnaryPredPredOp , ArmISA::SveUnarySca2VecUnpredOp , ArmISA::SveUnaryUnpredOp , ArmISA::SveUnaryWideImmPredOp , ArmISA::SveUnaryWideImmUnpredOp , ArmISA::SveUnpackOp , ArmISA::SveWhileOp , ArmISA::SveWImplicitSrcDstOp , ArmISA::SysDC64 , DecoderFaultInst , FailUnimplemented , GPUStaticInst , HsailISA::AtomicInst< MemDataType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::BrInstBase< TargetType > , HsailISA::BrnInstBase< TargetType > , HsailISA::Call , HsailISA::CbrInstBase< TargetType > , HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands > , HsailISA::HsailGPUStaticInst , HsailISA::LdaInst< DestDataType, AddrOperandType > , HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType > , HsailISA::SpecialInst1SrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcBase< DestOperandType > , HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType > , HsailISA::Stub , HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType > , HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType > , ImmOp64 , ImmOp , KernelLaunchStaticInst , McrMrcImplDefined , McrMrcMiscInst , McrrOp , MiscRegImmOp64 , MiscRegImplDefined64 , MiscRegRegImmOp64 , MiscRegRegImmOp , MrrcOp , MrsOp , MsrImmOp , MsrRegOp , PowerISA::BranchNonPCRel , PowerISA::BranchNonPCRelCond , PowerISA::BranchPCRel , PowerISA::BranchPCRelCond , PowerISA::BranchRegCond , PowerISA::CondLogicOp , PowerISA::CondMoveOp , PowerISA::FloatOp , PowerISA::IntImmOp , PowerISA::IntOp , PowerISA::IntRotateOp , PowerISA::IntShiftOp , PowerISA::MemDispOp , PowerISA::MemOp , PowerISA::MiscOp , PowerISA::PowerStaticInst , RegImmImmOp , RegImmOp , RegImmRegOp , RegImmRegShiftOp , RegMiscRegImmOp64 , RegMiscRegImmOp , RegOp , RegRegImmImmOp64 , RegRegImmImmOp , RegRegImmOp , RegRegOp , RegRegRegImmOp64 , RegRegRegImmOp , RegRegRegOp , RegRegRegRegOp , RiscvISA::AtomicMemOp , RiscvISA::AtomicMemOpMicro , RiscvISA::CompRegOp , RiscvISA::CSROp , RiscvISA::Load , RiscvISA::LoadReserved , RiscvISA::LoadReservedMicro , RiscvISA::MemFenceMicro , RiscvISA::RegOp , RiscvISA::Store , RiscvISA::StoreCond , RiscvISA::StoreCondMicro , RiscvISA::SystemOp , RiscvISA::Unknown , SparcISA::BlockMemImmMicro , SparcISA::BlockMemMicro , SparcISA::Branch , SparcISA::BranchDisp , SparcISA::BranchImm13 , SparcISA::FailUnimplemented , SparcISA::FpUnimpl , SparcISA::IntOp , SparcISA::IntOpImm , SparcISA::Mem , SparcISA::MemImm , SparcISA::Nop , SparcISA::Priv , SparcISA::RdPriv , SparcISA::SetHi , SparcISA::SparcMacroInst , SparcISA::SparcStaticInst , SparcISA::Trap , SparcISA::Unknown , SparcISA::WarnUnimplemented , SparcISA::WrPriv , SparcISA::WrPrivImm , StaticInst , UnknownOp64 , UnknownOp , WarnUnimplemented , X86ISA::FpOp , X86ISA::LdStOp , X86ISA::LdStSplitOp , X86ISA::MacroopBase , X86ISA::MediaOpImm , X86ISA::MediaOpReg , X86ISA::RegOp , X86ISA::RegOpImm , X86ISA::X86MicroopBase , X86ISA::X86StaticInst
• generateHsaKernelInfo() : HsaCode , HsailCode
• generateInterrupt() : Pl011 , Pl111 , UFSHostDevice
• generateIpi() : Iob
• generateLongDescFault() : ArmISA::TableWalker
• generatePkt() : GarnetSyntheticTraffic
• generateReadEvent() : Pl111
• generateSGI() : Gicv3CPUInterface
• generateTCEvent() : DefaultCommit< Impl >
• generateTrapEvent() : DefaultCommit< Impl >
• GenericAlignmentFault() : GenericAlignmentFault
• GenericArmPciHost() : GenericArmPciHost
• GenericArmSystem() : GenericArmSystem
• GenericPageTableFault() : GenericPageTableFault
• GenericPciHost() : GenericPciHost
• GenericTimer() : GenericTimer
• GenericTimerISA() : GenericTimerISA
• GenericTimerMem() : GenericTimerMem
• genFlags() : X86ISA::RegOpBase
• genIndirectInfo() : IndirectPredictor , SimpleIndirectPredictor
• genMemFragmentRequest() : AtomicSimpleCPU , CheckerCPU
• genRegister() : Trace::TarmacTracerRecord
• genStartAddr() : DramGen
• genSwiMask() : GicV2
• get() : ArmInterruptPinGen , ArmPPIGen , ArmSPIGen , BasePrefetcher::PrefetchInfo , Block , Coeff8 , Coeff8x8 , Compressed , CRegOperand , DmaReadFifo , DRegOperand , GuestABI::Argument< ABI, Arg, Enabled > , GuestABI::Argument< ABI, VarArgs< Types... > > , GuestABI::Argument< DefaultSyscallABI, Arg, typename std::enable_if< std::is_integral< Arg >::value >::type > , GuestABI::Argument< DefaultSyscallABI, Arg, typename std::enable_if< std::is_pointer< Arg >::value >::type > , GuestABI::Argument< PseudoInstABI, uint64_t > , GuestABI::Argument< TestABI_1D, Arg, typename std::enable_if< std::is_floating_point< Arg >::value >::type > , GuestABI::Argument< TestABI_1D, int > , GuestABI::Argument< TestABI_2D, Arg, typename std::enable_if< std::is_floating_point< Arg >::value >::type > , GuestABI::Argument< TestABI_2D, int > , GuestABI::Argument< TestABI_TcInit, int > , GuestABI::Argument< X86PseudoInstABI, uint64_t > , GuestABI::VarArgs< Types > , ImmOperand< T > , Label , ListOperand , m5::Coroutine< Arg, Ret >::CallerType , m5::Coroutine< Arg, Ret > , Matrix64x12 , Net::Ip6Ptr , Net::IpPtr , Net::TcpPtr , Net::UdpPtr , Packet , RefCountingPtr< T > , RegOrImmOperand< RegOperand, T > , sc_core::sc_direct_access< Element > , sc_core::sc_member_access< Element, Access > , sc_dt::sc_fxnum_bitref , sc_dt::sc_fxnum_fast_bitref , sc_dt::sc_fxnum_fast_subref , sc_dt::sc_fxnum_subref , SRegOperand , tlm::tlm_blocking_get_if< T > , tlm::tlm_fifo< T > , tlm::tlm_global_quantum , tlm::tlm_put_get_imp< PUT_DATA, GET_DATA > , tlm_utils::peq_with_cb_and_phase< OWNER, TYPES >::delta_list
• get_accessor() : tlm_utils::instance_specific_extension_container
• get_address() : tlm::tlm_generic_payload
• get_aggregate_fault_probability() : Router
• get_attribute() : sc_core::sc_object , sc_gem5::Object
• get_base_export() : tlm::tlm_base_initiator_socket< BUSWIDTH, FW_IF, BW_IF, N, POL > , tlm::tlm_base_initiator_socket_b< BUSWIDTH, FW_IF, BW_IF > , tlm::tlm_base_target_socket< BUSWIDTH, FW_IF, BW_IF, N, POL > , tlm::tlm_base_target_socket_b< BUSWIDTH, FW_IF, BW_IF > , tlm_utils::multi_passthrough_initiator_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL >
• get_base_interface() : tlm::tlm_base_initiator_socket< BUSWIDTH, FW_IF, BW_IF, N, POL > , tlm::tlm_base_initiator_socket_b< BUSWIDTH, FW_IF, BW_IF > , tlm::tlm_base_target_socket< BUSWIDTH, FW_IF, BW_IF, N, POL > , tlm::tlm_base_target_socket_b< BUSWIDTH, FW_IF, BW_IF > , tlm_utils::multi_passthrough_initiator_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL >
• get_base_port() : tlm::tlm_base_initiator_socket< BUSWIDTH, FW_IF, BW_IF, N, POL > , tlm::tlm_base_initiator_socket_b< BUSWIDTH, FW_IF, BW_IF > , tlm::tlm_base_target_socket< BUSWIDTH, FW_IF, BW_IF, N, POL > , tlm::tlm_base_target_socket_b< BUSWIDTH, FW_IF, BW_IF >
• get_binders() : tlm_utils::multi_init_base_if< TYPES > , tlm_utils::multi_passthrough_initiator_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::multi_target_base_if< TYPES >
• get_bit() : sc_dt::sc_bitref_r< T > , sc_dt::sc_bv_base , sc_dt::sc_concref_r< X, Y > , sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_fxval , sc_dt::sc_fxval_fast , sc_dt::sc_lv_base , sc_dt::sc_subref_r< X > , sc_dt::scfx_rep
• get_bits() : VecPredRegContainer< NumBits, Packed >
• get_buf_read_activity() : InputUnit
• get_buf_write_activity() : InputUnit
• get_bus_width() : tlm::tlm_base_initiator_socket< BUSWIDTH, FW_IF, BW_IF, N, POL > , tlm::tlm_base_socket_if , tlm::tlm_base_target_socket< BUSWIDTH, FW_IF, BW_IF, N, POL >
• get_byte_enable_length() : tlm::tlm_generic_payload
• get_byte_enable_ptr() : tlm::tlm_generic_payload
• get_cached_report() : sc_core::sc_report_handler
• get_catch_actions() : sc_core::sc_report_handler
• get_child_events() : sc_core::sc_module , sc_core::sc_object , sc_core::sc_process_handle , sc_gem5::Object
• get_child_objects() : sc_core::sc_module , sc_core::sc_object , sc_core::sc_process_handle , sc_gem5::Object
• get_command() : tlm::tlm_generic_payload
• get_count() : sc_core::sc_report_handler
• get_credit_count() : OutputUnit , OutVcState
• get_crossbar_activity() : CrossbarSwitch
• get_curr_proc_info() : sc_core::sc_simcontext
• get_current_time() : tlm_utils::tlm_quantumkeeper
• get_cword() : sc_dt::sc_bitref_r< T > , sc_dt::sc_bv_base , sc_dt::sc_concref_r< X, Y > , sc_dt::sc_lv_base , sc_dt::sc_subref_r< X >
• get_data() : Linux::ThreadInfo
• get_data_length() : tlm::tlm_generic_payload
• get_data_ptr() : tlm::tlm_generic_payload
• get_data_ref() : sc_core::sc_signal< sc_dt::sc_bigint< W > > , sc_core::sc_signal< sc_dt::sc_biguint< W > > , sc_core::sc_signal< sc_dt::sc_int< W > > , sc_core::sc_signal< sc_dt::sc_uint< W > > , sc_core::sc_signal_in_if< sc_dt::sc_bigint< W > > , sc_core::sc_signal_in_if< sc_dt::sc_biguint< W > > , sc_core::sc_signal_in_if< sc_dt::sc_int< W > > , sc_core::sc_signal_in_if< sc_dt::sc_uint< W > >
• get_dequeue_time() : flit
• get_direct_mem_ptr() : sc_gem5::TlmToGem5Bridge< BITWIDTH > , SimpleLTTarget1 , tlm::tlm_fw_direct_mem_if< TRANS > , tlm_utils::callback_binder_fw< TYPES > , tlm_utils::passthrough_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::process , tlm_utils::passthrough_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::process , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process
• get_direction() : InputUnit , OutputUnit
• get_dmi_pointer() : adapt_ext2gp< BUSWIDTH > , adapt_gp2ext< BUSWIDTH >
• get_dmi_ptr() : tlm::tlm_dmi
• get_elements() : sc_core::sc_vector_assembly< T, MT > , sc_core::sc_vector_base
• get_end_address() : tlm::tlm_dmi
• get_enqueue_time() : flit , InputUnit , VirtualChannel
• get_event() : tlm_utils::peq_with_get< PAYLOAD >
• get_export_base() : tlm::tlm_base_initiator_socket< BUSWIDTH, FW_IF, BW_IF, N, POL > , tlm::tlm_base_socket_if , tlm::tlm_base_target_socket< BUSWIDTH, FW_IF, BW_IF, N, POL >
• get_extension() : tlm::tlm_generic_payload , tlm_utils::instance_specific_extensions_per_accessor
• get_fault_vector() : Router
• get_file_name() : sc_core::sc_report
• get_global_quantum() : tlm_utils::tlm_quantumkeeper
• get_gp_option() : tlm::tlm_generic_payload
• get_granted_access() : tlm::tlm_dmi
• get_handle() : tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::process_handle_list , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::process_handle_list
• get_hierarch_bind() : tlm_utils::multi_init_base< BUSWIDTH, TYPES, N, POL > , tlm_utils::multi_passthrough_initiator_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::multi_target_base< BUSWIDTH, TYPES, N, POL >
• get_id() : flit , NetworkLink , Router , sc_core::sc_report
• get_inlink_id() : InputUnit
• get_input_arbiter_activity() : SwitchAllocator
• get_inputUnit_ref() : Router
• get_interface() : sc_core::sc_export< IF > , sc_core::sc_export_base , sc_core::sc_port_b< IF >
• get_iterface() : sc_core::sc_export< IF > , sc_core::sc_export_base
• get_last_binder() : tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::multi_to_multi_bind_base< TYPES >
• get_line_number() : sc_core::sc_report
• get_local_time() : tlm_utils::tlm_quantumkeeper
• get_log_file_name() : sc_core::sc_report_handler
• get_max() : SimpleAddressMap
• get_message() : sc_core::sc_report
• get_min() : SimpleAddressMap
• get_msg() : sc_core::sc_report
• get_msg_ptr() : flit
• get_msg_type() : sc_core::sc_report
• get_multi_binds() : tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::multi_target_base_if< TYPES >
• get_name() : tlm::tlm_phase
• get_net_ptr() : Router
• get_new_action_id() : sc_core::sc_report_handler
• get_next_transaction() : tlm_utils::peq_with_get< PAYLOAD >
• get_num_inports() : Router
• get_num_outports() : Router
• get_num_vcs() : Router
• get_num_vnets() : Router
• get_number() : cp::Print
• get_other_side() : tlm_utils::callback_binder_fw< TYPES >
• get_outlink_id() : OutputUnit
• get_outport() : flit , InputUnit , VirtualChannel
• get_output_arbiter_activity() : SwitchAllocator
• get_outputUnit_ref() : Router
• get_outvc() : InputUnit , VirtualChannel
• get_packed_rep() : sc_dt::sc_signed , sc_dt::sc_unsigned
• get_parent_object() : sc_core::sc_event , sc_core::sc_object , sc_core::sc_process_handle , sc_gem5::Object
• get_pipe_stages() : Router
• get_policy() : sc_core::sc_vector_iter< Element, AccessPolicy >
• get_port_base() : tlm::tlm_base_initiator_socket< BUSWIDTH, FW_IF, BW_IF, N, POL > , tlm::tlm_base_socket_if , tlm::tlm_base_target_socket< BUSWIDTH, FW_IF, BW_IF, N, POL >
• get_process_name() : sc_core::sc_report
• get_process_object() : sc_core::sc_process_handle
• get_protocol_types() : ClockRateControlInitiatorSocket , ClockRateControlTargetSocket , SignalInterruptInitiatorSocket , SignalInterruptTargetSocket , tlm::tlm_base_socket_if , tlm::tlm_initiator_socket< BUSWIDTH, TYPES, N, POL > , tlm::tlm_target_socket< BUSWIDTH, TYPES, N, POL >
• get_ptr() : Block
• get_raw() : sc_dt::sc_signed , sc_dt::sc_unsigned , VecPredRegT< VecElem, NumElems, Packed, Const >
• get_read_latency() : tlm::tlm_dmi
• get_ref_count() : tlm::tlm_generic_payload
• get_rep() : sc_dt::sc_fxnum , sc_dt::sc_fxval
• get_report_type() : tlm_utils::convenience_socket_base , tlm_utils::multi_socket_base , tlm_utils::passthrough_socket_base , tlm_utils::simple_socket_base
• get_response_status() : tlm::tlm_generic_payload
• get_response_string() : tlm::tlm_generic_payload
• get_route() : flit
• get_router_id() : GarnetNetwork , NetworkInterface
• get_severity() : sc_core::sc_report
• get_signal() : sc_core::sc_signal< sc_dt::sc_bigint< W > > , sc_core::sc_signal< sc_dt::sc_biguint< W > > , sc_core::sc_signal< sc_dt::sc_int< W > >
• get_size() : flit , tlm_utils::time_ordered_list< PAYLOAD >
• get_slice() : sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::scfx_rep
• get_socket() : tlm_utils::convenience_socket_base , tlm_utils::multi_init_base< BUSWIDTH, TYPES, N, POL > , tlm_utils::multi_target_base< BUSWIDTH, TYPES, N, POL > , tlm_utils::passthrough_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::passthrough_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_initiator_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_initiator_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >
• get_socket_category() : tlm::tlm_base_initiator_socket< BUSWIDTH, FW_IF, BW_IF, N, POL > , tlm::tlm_base_socket_if , tlm::tlm_base_target_socket< BUSWIDTH, FW_IF, BW_IF, N, POL > , tlm_utils::multi_init_base< BUSWIDTH, TYPES, N, POL > , tlm_utils::multi_target_base< BUSWIDTH, TYPES, N, POL >
• get_sockets() : tlm_utils::multi_init_base_if< TYPES > , tlm_utils::multi_passthrough_initiator_socket< MODULE, BUSWIDTH, TYPES, N, POL >
• get_src_delay() : flit
• get_stage() : flit
• get_start_address() : tlm::tlm_dmi
• get_state() : VirtualChannel
• get_streaming_width() : tlm::tlm_generic_payload
• get_time() : flit , sc_core::sc_report
• get_type() : flit , sc_dt::sc_fxval , sc_dt::scfx_rep
• get_val() : sc_dt::sc_fxnum_fast , sc_dt::sc_fxval_fast
• get_value() : sc_core::sc_semaphore , sc_core::sc_semaphore_if
• get_vc() : flit
• get_vc_per_vnet() : Router
• get_vec() : SparcISA::Interrupts
• get_verbosity() : sc_core::sc_report
• get_verbosity_level() : sc_core::sc_report_handler
• get_vnet() : flit , NetworkInterface , SwitchAllocator
• get_vnet_type() : GarnetNetwork
• get_word() : sc_dt::sc_bitref_r< T > , sc_dt::sc_bv_base , sc_dt::sc_concref_r< X, Y > , sc_dt::sc_lv_base , sc_dt::sc_subref_r< X >
• get_write_latency() : tlm::tlm_dmi
• get_writer_policy() : sc_core::sc_signal_write_if< T > , sc_gem5::ScSignalBase , sc_gem5::ScSignalBaseT< T, WRITER_POLICY >
• getAccessBackingStore() : RubySystem
• getAccessDepth() : Request
• getAccessLatency() : Request
• getAccessMapEntry() : AccessMapPatternMatching
• getAccessMode() : RubyRequest
• getAccessPermission() : AbstractController
• getActiveInt() : GicV2
• getActivityCount() : ActivityRecorder
• getActivityRecorder() : Minor::Pipeline
• getAdaptiveRouting() : SimpleNetwork
• getAddr() : BasePrefetcher::PrefetchInfo , DRAMCtrl::DRAMPacket , Packet , TempCacheBlk , Trace::InstRecord
• getAddress() : AccessTraceForAddress , Check , SubBlock , VirtQueue
• getAddressAtIdx() : CacheMemory
• getAddressMask() : SimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS > , SimpleBusLT< NR_OF_INITIATORS, NR_OF_TARGETS >
• getAddressOffset() : SimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS > , SimpleBusLT< NR_OF_INITIATORS, NR_OF_TARGETS >
• getAddressOperand() : HsailISA::MemInst
• getAddressProfiler() : Profiler
• getAddrMonitor() : BaseDynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• getAddrRange() : AbstractMemory , LdsState , Packet
• getAddrRanges() : AbstractController , AddrMapper , AddrMapper::MapperSlavePort , BaseCache::CpuSidePort , BaseCache , BaseXBar , BasicPioDevice , Bridge::BridgeSlavePort , CoherentXBar::CoherentXBarSlavePort , CommMonitor , CommMonitor::MonitorSlavePort , DRAMCtrl::MemoryPort , DRAMSim2::MemoryPort , ExternalSlave::ExternalPort , FastModel::GIC , GenericPciHost , GenericTimerMem , GicV2 , Gicv2m , Gicv3 , Gicv3Its , GpuDispatcher , HDLcd , Iob , LdsState::CuSidePort , MasterPort , MemCheckerMonitor , MemCheckerMonitor::MonitorSlavePort , MemDelay::SlavePort , NoMaliGpu , NoncoherentXBar::NoncoherentXBarSlavePort , PciDevice , PioDevice , PioPort< Device > , Pl111 , QoS::MemSinkCtrl::MemoryPort , RangeAddrMapper , RubyPort::MemSlavePort , RubyPort::PioSlavePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH >::BridgeSlavePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH > , SerialLink::SerialLinkSlavePort , SimpleCache::CPUSidePort , SimpleCache , SimpleMemobj::CPUSidePort , SimpleMemobj , SimpleMemory::MemoryPort , SlavePort , SMMUATSSlavePort , SMMUControlPort , SMMUSlavePort , TLBCoalescer::CpuSidePort , TsunamiPChip , Uart8250 , UFSHostDevice , VGic , X86ISA::GpuTLB::CpuSidePort , X86ISA::I8042 , X86ISA::Interrupts , X86ISA::IntSlavePort< Device >
• getAddrTable() : SymbolTable
• getAffinity() : Gicv3Redistributor
• getAllDest() : NetDest
• getAllInstructions() : Profiler
• getAllObjectNames() : CxxConfigFileBase , CxxIniFile
• getAndFormatOneReg() : BaseKvmCPU
• getAndIncrementInstSeq() : FullO3CPU< Impl >
• getAndIncSeqNum() : ComputeUnit
• getAPIVersion() : Kvm
• getArch() : ObjectFile , System
• getArchFlags() : Request
• getArchParams() : DRAMPower
• getArg() : Arguments
• getArmSystem() : ArmSystem
• getASID() : BaseDynInst< Impl >
• getAsid() : Request
• getAtomicOp() : Packet
• getAtomicOpFunctor() : Request
• getAttr() : ArmISA::TLB , KvmDevice
• getAttrPtr() : KvmDevice
• getBackdoor() : sc_gem5::Gem5ToTlmBridge< BITWIDTH >
• getBackingStore() : PhysicalMemory
• getBankConflictPenalty() : LdsState
• getBankedRegs() : GicV2
• getBanks() : LdsState
• getBAR() : PciDevice
• getBaseAddr() : PrdTableEntry
• getBE() : Packet
• getBias() : Process
• getBiasLSUM() : MPP_StatisticalCorrector , MPP_StatisticalCorrector_64KB , MPP_StatisticalCorrector_8KB
• getBimodePred() : TAGE_SC_L_TAGE , TAGEBase
• getBins() : Histogram
• getBinSize() : Histogram
• getBlockAddr() : Packet
• getBlockedMemInstToExecute() : InstructionQueue< Impl >
• getBlockSize() : BaseCache
• getBlockSizeBits() : RubySystem
• getBlockSizeBytes() : RubySystem
• getBootLoader() : ArmSystem
• getBpSpaceId() : FastModel::CortexA76TC , Iris::ThreadContext
• getBrigBaseData() : BrigObject
• getBrkPoint() : MemState
• getBufferSize() : SimpleNetwork
• getBuffersPerCtrlVC() : GarnetNetwork
• getBuffersPerDataVC() : GarnetNetwork
• getBusState() : QoS::MemCtrl
• getBusStateNext() : QoS::MemCtrl
• getbyte() : BaseRemoteGDB
• getByte() : DataBlock , SubBlock
• getByteCount() : PrdTableEntry
• getByteEnable() : Request
• getByteTracker() : MemChecker
• getCacheAssoc() : CacheMemory
• getCacheSize() : CacheMemory
• getCall() : ArmSemihosting
• getCandidates() : DeltaCorrelatingPredictionTables::DCPTEntry
• getCause() : GlobalSimLoopExitEvent , LocalSimLoopExitEvent
• getCCList() : UnifiedFreeList
• getCCReg() : UnifiedFreeList
• getCheck() : CheckTable
• getCheckerCpuPtr() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• getCheckFlush() : RubyTester
• getChunkEvent() : DmaCallback
• getClock() : Shader
• getCode() : DictionaryCompressor< T >::Pattern , EmbeddedPython , GlobalSimLoopExitEvent , LocalSimLoopExitEvent
• getCodeSectionEntry() : BrigObject
• getCOE() : FDEntry
• getCommittingThread() : DefaultCommit< Impl > , Minor::Execute
• getCompleteHeader() : BmpWriter
• getComputeUnit() : LdsState
• getConfAddrRanges() : PhysicalMemory
• getConstPtr() : Packet
• getConsumer() : MessageBuffer , WireBuffer
• getContext() : BaseCPU , BaseKvmCPU , Wavefront
• getCooldownEnabled() : RubySystem
• getCore() : FastModel::CortexA76Cluster
• getCount() : BloomFilter::Base , BloomFilter::Block , BloomFilter::Multi , BloomFilter::MultiBitSel , BloomFilter::Perfect , InstructionQueue< Impl > , LSQ< Impl > , LSQUnit< Impl >
• getCounter() : ArmISA::PMU
• getCounterId() : ArmISA::PMU::CounterState
• getCounterTypeRegister() : ArmISA::PMU
• getCounterValue() : ArmISA::PMU
• getCpSeq() : Trace::InstRecord
• getCpSeqValid() : Trace::InstRecord
• getCpuAddrMonitor() : BaseCPU
• getCPUInterface() : Gicv3 , Gicv3Redistributor
• getCpuPort() : RubyDirectedTester
• getCpuPriority() : GicV2
• getCpuPtr() : BaseDynInst< Impl > , CheckerThreadContext< TC > , Iris::ThreadContext , Minor::ExecContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• getCPUSequencer() : AbstractController
• getCpuTarget() : GicV2
• getCreditQueue() : InputUnit
• getCtr() : TAGEBase
• getCtrlAddr() : DRAMCtrl
• getCurrentInstCount() : BaseCPU , CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• getCurrentQueue() : VirtIODeviceBase
• getCurSveVecLen() : ArmISA::ArmStaticInst
• getCurSveVecLenInBits() : ArmISA::ArmStaticInst , ArmISA::ISA
• getCurSveVecLenInBitsAtReset() : ArmISA::ISA
• getCurSveVecLenInQWords() : ArmISA::ArmStaticInst
• getCurTick() : EventQueue , sc_gem5::Scheduler
• getData() : BrigObject , DataBlock , Histogram , SimpleATInitiator1::MyTransaction< DT > , SimpleATInitiator2::MyTransaction< DT >
• getDataBlk() : AbstractCacheEntry
• getDataLatency() : CacheMemory
• getDataMod() : DataBlock
• getDataPort() : AtomicSimpleCPU , BaseCPU , BaseKvmCPU , CheckerCPU , FullO3CPU< Impl > , Iris::BaseCPU , LSQ< Impl > , Minor::Pipeline , MinorCPU , TimingSimpleCPU , TraceCPU
• getDataRate() : DRAMPower
• getDataStatus() : Trace::InstRecord
• getDcachePort() : Minor::Execute , Minor::LSQ
• getDebugRegisters() : X86KvmCPU
• getDecoderPtr() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• getDecompressionLatency() : BaseCacheCompressor , CompressionBlk
• getDeferredMemInstToExecute() : InstructionQueue< Impl >
• getDelayedTicks() : Message
• getDelayHist() : AbstractController
• getDelayVCHist() : AbstractController
• getDesc() : AlphaISA::AlphaLinuxProcess , ArmFreebsdProcess32 , ArmFreebsdProcess64 , ArmFreebsdProcessBits::SyscallTable , ArmLinuxProcess32 , ArmLinuxProcess64 , ArmLinuxProcessBits::SyscallTable , MipsLinuxProcess , PowerLinuxProcess , Process , RiscvLinuxProcess32 , RiscvLinuxProcess64 , SparcISA::Sparc32LinuxProcess , SparcISA::Sparc64LinuxProcess , SparcISA::SparcLinuxProcess , SparcISA::SparcSolarisProcess , X86ISA::X86Process
• getDesc32() : SparcISA::SparcLinuxProcess
• getDescription() : WireBuffer
• getDescriptor() : VirtQueue
• getDest() : Request
• getDestination() : Message
• getDevice() : PciHost
• getDeviceAddressRanges() : ComputeUnit::DataPort , ComputeUnit::SQCPort
• getDeviceStatus() : VirtIODeviceBase
• getDistributor() : Gicv3
• getDMAPort() : ArmISA::Stage2MMU
• getDMIData() : SimpleLTInitiator2_dmi , SimpleLTInitiator3_dmi
• getDMIPointer() : SimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS > , SimpleBusLT< NR_OF_INITIATORS, NR_OF_TARGETS >
• getDriver() : DeviceFDEntry
• getDTBPtr() : CheckerCPU , CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• getDynamicPower() : MathExprPowerModel , PowerModel , PowerModelState , SubSystem
• getDynInstr() : LdsState
• getEmulEnv() : X86ISA::MacroopBase
• getEndpointBandwidth() : SimpleNetwork
• getEndType() : PipeFDEntry
• getEntry() : BaseIndexingPolicy , MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB , StatisticalCorrector::SCThreadHistory
• getEOT() : PrdTableEntry
• getEquation() : ThermalCapacitor , ThermalDomain , ThermalEntity , ThermalReference , ThermalResistor
• getErrorMessage() : MemChecker
• getEvent() : ArmISA::PMU
• getEvs() : FastModel::CortexA76Cluster
• getExecuteTick() : ElasticTrace::TraceInfo
• getExpressions() : ObjectMatch
• getExt() : Net::Ip6Hdr
• getExtension() : Gem5SystemC::Gem5Extension
• getExternalPort() : ExternalMaster::Handler , ExternalSlave::Handler , StubSlavePortHandler
• getExtMachInst() : X86ISA::MacroopBase
• getExtraData() : Request
• getFatal() : Logger
• getFault() : BaseDynInst< Impl > , WholeTranslationState
• getFaultAddrReg64() : ArmISA::ArmFault
• getFaultStatusCode() : ArmISA::AbortFault< T >
• getFaultVAddr() : ArmISA::AbortFault< T > , ArmISA::ArmFault , GenericAlignmentFault , GenericPageTableFault
• getfd() : ListenSocket
• getFDEntry() : FDArray
• getfdStatic() : TCPIface
• getFetchingThread() : DefaultFetch< Impl >
• getFetchSeq() : Trace::InstRecord
• getFetchSeqValid() : Trace::InstRecord
• getFileName() : DeviceFDEntry , FileFDEntry
• getFileOffset() : FileFDEntry
• getFirstResponseToCompletionDelayHist() : GPUCoalescer , Sequencer
• getFlags() : CxxConfigFileBase , Event , HBFDEntry , Request , Trace::InstRecord , WholeTranslationState
• getFloatData() : Trace::InstRecord
• getFloatReg() : UnifiedFreeList
• getForwardRequestToFirstResponseHist() : GPUCoalescer , Sequencer
• getFPUState() : BaseKvmCPU
• getFreebsdDesc() : ArmFreebsdProcessBits
• getFreeTid() : FullO3CPU< Impl >
• getFromScEvent() : sc_gem5::Event
• getFromScObject() : sc_gem5::Object
• getFsr() : ArmISA::AbortFault< T > , ArmISA::ArmFault
• getFU() : FUPool::FUIdxQueue
• getFunction() : BrigObject , HsaObject
• getGenericTimer() : ArmISA::ISA , ArmSystem
• getGHR() : TAGEBase
• getGIC() : ArmSystem
• getGicReg() : KvmKernelGicV2
• getGICv3CPUInterface() : ArmISA::ISA
• getGlobalMasterId() : System
• getGMLdRespFIFO() : GlobalMemPipeline
• getGMStRespFIFO() : GlobalMemPipeline
• getGPUCoalescer() : AbstractController
• getGuestByteOrder() : System
• getGuestData() : BaseKvmCPU
• getGuestFeatures() : VirtIODeviceBase
• getHack() : Logger
• getHash() : FrameBuffer , MultiperspectivePerceptron::ACYCLIC , MultiperspectivePerceptron::BIAS , MultiperspectivePerceptron::BLURRYPATH , MultiperspectivePerceptron::GHIST , MultiperspectivePerceptron::GHISTMODPATH , MultiperspectivePerceptron::GHISTPATH , MultiperspectivePerceptron::HistorySpec , MultiperspectivePerceptron::IMLI , MultiperspectivePerceptron::LOCAL , MultiperspectivePerceptron::MODHIST , MultiperspectivePerceptron::MODPATH , MultiperspectivePerceptron::PATH , MultiperspectivePerceptron::RECENCY , MultiperspectivePerceptron::RECENCYPOS , MultiperspectivePerceptron::SGHISTPATH
• getHashFilter() : MultiperspectivePerceptron::MPPBranchInfo
• getHCREL2FMO() : Gicv3CPUInterface
• getHCREL2IMO() : Gicv3CPUInterface
• getHead() : EventQueue
• getHeadPacket() : Minor::LSQ::LSQRequest , Minor::LSQ::SingleDataRequest , Minor::LSQ::SpecialDataRequest , Minor::LSQ::SplitDataRequest
• getHistoryStackEntry() : MPP_StatisticalCorrector::MPP_SCThreadHistory
• getHitLatencyHist() : Sequencer
• getHitMachLatencyHist() : Sequencer
• getHitTypeLatencyHist() : Sequencer
• getHitTypeMachLatencyHist() : Sequencer
• getHostCycles() : BaseKvmCPU , X86KvmCPU
• getHotLines() : Profiler
• getHPC() : MultiperspectivePerceptron::MPPBranchInfo
• getHPPIR0() : Gicv3CPUInterface
• getHPPIR1() : Gicv3CPUInterface
• getHPPVILR() : Gicv3CPUInterface
• getHypControl() : SystemCounter
• getIcachePort() : Minor::Fetch1
• getId() : Port , RubyPort
• getImgExtension() : BmpWriter , ImgWriter , PngWriter
• getImmediate() : X86ISA::Decoder
• getIncomingLink() : Message
• getIncompleteTimes() : Sequencer
• getIncompleteWriteCluster() : MemChecker::ByteTracker
• getIndBias() : MPP_StatisticalCorrector , StatisticalCorrector
• getIndBiasBank() : MPP_StatisticalCorrector , StatisticalCorrector , TAGE_SC_L_64KB_StatisticalCorrector , TAGE_SC_L_8KB_StatisticalCorrector
• getIndBiasSK() : MPP_StatisticalCorrector , StatisticalCorrector
• getIndex() : DefaultBTB , MultiCompressor::MultiCompData , MultiperspectivePerceptron , MultiperspectivePerceptronTAGE , StackDistCalc
• getIndUpd() : MPP_StatisticalCorrector , StatisticalCorrector
• getIndUpds() : StatisticalCorrector
• getInfo() : Logger
• getInitialApicId() : X86ISA::Interrupts
• getInitialToForwardDelayHist() : GPUCoalescer , Sequencer
• getInLinks() : PerfectSwitch
• getInportDirection() : Router
• getInput() : Minor::Decode , Minor::Execute , Minor::Fetch2
• getInst() : BrigObject
• getInstance() : GpuDispatcher
• getInstListIt() : BaseDynInst< Impl >
• getInstPort() : AtomicSimpleCPU , BaseCPU , BaseKvmCPU , CheckerCPU , DefaultFetch< Impl > , FullO3CPU< Impl > , Iris::BaseCPU , Minor::Pipeline , MinorCPU , TimingSimpleCPU , TraceCPU
• getInstRecord() : Trace::ExeTracer , Trace::InstPBTrace , Trace::InstTracer , Trace::IntelTrace , Trace::NativeTrace , Trace::TarmacParser , Trace::TarmacTracer
• getInstructionProfiler() : Profiler
• getInsts() : DefaultCommit< Impl >
• getInstToExecute() : InstructionQueue< Impl >
• getIntAddrRange() : X86ISA::Interrupts
• getIntConfig() : GicV2
• getIntData() : Trace::InstRecord
• getIntEnabled() : GicV2
• getInterface() : sc_gem5::Port
• getInterpPath() : ElfObject
• getInterpreter() : ElfObject , ObjectFile , Process
• getInterrupt() : AlphaISA::Interrupts , ArmISA::Interrupts , BaseInterrupts , MipsISA::Interrupts , Pl050 , PowerISA::Interrupts , RiscvISA::Interrupts , SparcISA::Interrupts , X86ISA::Interrupts
• getInterruptController() : BaseCPU
• getInterrupts() : FullO3CPU< Impl >
• getInterval() : Intel8254Timer::Counter::CounterEvent
• getIntGroup() : GicV2 , Gicv3Distributor , Gicv3Redistributor
• getIntPriority() : GicV2
• getIntReg() : UnifiedFreeList
• getIntWidth() : ArmISA::ArmStaticInst
• getIsaPtr() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• getISR() : ArmISA::Interrupts
• getIssueToInitialDelayHist() : GPUCoalescer , Sequencer
• getIssuingThread() : Minor::Execute
• getITBPtr() : CheckerCPU , CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• getIterator() : CircularQueue< T >
• getKernel() : BrigObject , HsaObject
• getKernelControl() : SystemCounter
• getKernelEnd() : System
• getKernelEntry() : System
• getKernelStart() : System
• getKernelStats() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext , ThreadState
• getKvmRunState() : BaseKvmCPU
• getKvmVM() : System
• getLaneAddr() : CallArgMem
• getLaneOffset() : CallArgMem
• getLastAccess() : AbstractCacheEntry
• getLastEnqueueTime() : Message
• getLastMemBarrier() : Minor::LSQ
• getLatency() : BankedArray , SimpleMemory , Throttle
• getLatencyHist() : GPUCoalescer , Sequencer
• getLBABase() : IdeDisk
• getLds() : ComputeUnit
• getLdsPort() : ComputeUnit
• getLE() : Packet
• getLength() : X86ISA::SMBios::BiosInformation , X86ISA::SMBios::SMBiosStructure
• getLineAddress() : RubyRequest
• getLinkBandwidth() : Throttle
• getLinkUtilization() : NetworkLink
• getLinuxDesc() : ArmLinuxProcessBits
• getList() : EmbeddedPython
• getLMReqFIFO() : LocalMemPipeline
• getLMRespFIFO() : LocalMemPipeline
• getLoadHead() : LSQ< Impl > , LSQUnit< Impl >
• getLoadHeadSeqNum() : LSQ< Impl > , LSQUnit< Impl >
• getLocalHistory() : StatisticalCorrector::SCThreadHistory
• getLocalHistoryLength() : MultiperspectivePerceptron::LocalHistories
• getLocalIndex() : LocalBP
• getLockedAddrList() : AbstractMemory
• getLoop() : LoopPredictor
• getLoopUseCounter() : LoopPredictor
• getLRUindex() : Prefetcher
• getLSQ() : Minor::Execute
• getMachineID() : AbstractController
• getMacroStaticInst() : Trace::InstRecord
• getMandatoryQueue() : AbstractController
• getMap() : EmbeddedPyBind
• getMappings() : EmulationPageTable
• getMask() : WriteMask
• getMasterId() : BasePrefetcher::PrefetchInfo , System
• getMasterName() : System
• getMatchLocation() : DictionaryCompressor< T >::Pattern
• getMax() : Histogram
• getMaxEntries() : ROB< Impl >
• getMaxPermittedPrefetches() : QueuedPrefetcher
• getMaxStackSize() : MemState
• getMemDepViolator() : LSQ< Impl > , LSQUnit< Impl >
• getMemInst() : ComputeUnit::LDSPort::SenderState
• getMemOperandSize() : HsailISA::MemInst
• getMemoryMode() : System
• getMemoryQueue() : AbstractController
• getMemorySizeBits() : RubySystem
• getMemSpec() : DRAMPower
• getMemValid() : Trace::InstRecord
• getMessageSize() : Message
• getMicroOpCount() : TraceCPU::ElasticDataGen , TraceCPU::ElasticDataGen::InputStream
• getMiscIndices() : ArmISA::ISA
• getMiscRegId() : PhysRegFile
• getMISR() : VGic
• getMissLatencyHist() : GPUCoalescer , Sequencer
• getMissMachLatencyHist() : GPUCoalescer , Sequencer
• getMissTypeLatencyHist() : GPUCoalescer , Sequencer
• getMissTypeMachLatencyHist() : GPUCoalescer , Sequencer
• getMmapEnd() : MemState
• getMsgCount() : Switch , Throttle
• getMsgCounter() : Message
• getMSR() : X86KvmCPU
• getMsrIntersection() : X86KvmCPU
• getMSRs() : X86KvmCPU
• getName() : BaseDelta< BaseType, DeltaSizeBits > , BaseDictionaryCompressor , CPack , CxxConfigParams , FPCD , LdsState , ProbePoint , RepeatedQwordsCompressor , StaticInst , ZeroCompressor
• getNext() : Queue< Entry > , sc_gem5::NodeList< T >
• getNextByte() : X86ISA::Decoder
• getNextLevel() : SparcISA::SparcFault< T > , SparcISA::SparcFaultBase
• getNextPacket() : BaseGen , DramGen , DramRotGen , ExitGen , IdleGen , LinearGen , RandomGen , TraceGen
• getNextQueueEntry() : BaseCache
• getNextReady() : sc_gem5::Scheduler
• getNextReadyResp() : GlobalMemPipeline
• getNextThreadStackBase() : MemState
• getNiFlitSize() : GarnetNetwork
• getNode() : ThermalDomain
• getNodePtr() : Stats::Temp
• getNum() : MachineID
• getNumberOfVirtualNetworks() : Network
• getNumBlocks() : CacheMemory
• getNumCols() : GarnetNetwork
• getNumCUs() : GpuDispatcher
• getNumNodes() : Network
• getNumOperands() : GPUDynInst , GPUStaticInst , HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::BrInstBase< TargetType > , HsailISA::BrnInstBase< TargetType > , HsailISA::Call , HsailISA::CbrInstBase< TargetType > , HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands > , HsailISA::LdaInstBase< DestOperandType, AddrOperandType > , HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType > , HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType > , HsailISA::SpecialInst1SrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcNoDest , HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType > , HsailISA::StInstBase< MemDataType, SrcOperandType, AddrOperandType > , HsailISA::Stub , HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType > , HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType > , KernelLaunchStaticInst
• getNumPatterns() : BaseDelta< BaseType, DeltaSizeBits > , BaseDictionaryCompressor , CPack , FPCD , RepeatedQwordsCompressor , ZeroCompressor
• getNumPinnedWrites() : PhysRegId , RegId
• getNumPinnedWritesToComplete() : PhysRegId
• getNumRouters() : GarnetNetwork
• getNumRows() : GarnetNetwork
• getNumStages() : ActivityRecorder
• getNumTargets() : MSHR , WriteQueueEntry
• getNumValid() : SectorBlk
• getNumValidBlocks() : AbstractCacheEntry
• getObject() : CxxConfigManager
• getObjectChildren() : CxxConfigFileBase , CxxIniFile
• getOffset() : AddrRange , Packet
• getOneReg() : BaseKvmCPU
• getOneRegU32() : BaseKvmCPU
• getOneRegU64() : BaseKvmCPU
• getOperand() : BrigObject
• getOperandPtr() : BrigObject
• getOperandSize() : GPUDynInst , GPUStaticInst , HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::BrInstBase< TargetType > , HsailISA::BrnInstBase< TargetType > , HsailISA::Call , HsailISA::CbrInstBase< TargetType > , HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands > , HsailISA::LdaInstBase< DestOperandType, AddrOperandType > , HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType > , HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType > , HsailISA::SpecialInst1SrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcNoDest , HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType > , HsailISA::StInstBase< MemDataType, SrcOperandType, AddrOperandType > , HsailISA::Stub , HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType > , HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType > , KernelLaunchStaticInst
• getOpLatency() : FUPool
• getOpSys() : ObjectFile
• getOrAllocBp() : Iris::ThreadContext
• getOrdered() : MessageBuffer
• getOstream() : Trace::Logger , Trace::OstreamLogger
• getOutLinks() : PerfectSwitch
• getOutportDirection() : Router
• getOutQueue() : OutputUnit
• getOutstandReqHist() : GPUCoalescer , Sequencer
• getPA() : ChannelAddr
• getPacket() : BaseGen , BasePrefetcher , Gem5SystemC::Gem5Extension , MultiPrefetcher , QueuedPrefetcher
• getPacketData() : IGbE::TxDescCache
• getPacketSize() : IGbE::TxDescCache
• getPaddr() : BasePrefetcher::PrefetchInfo , Request , WholeTranslationState
• getPage() : DecodeCache::AddrMap< Value >
• getPageBytes() : System
• getPageShift() : System
• getPageTableOps() : SMMUv3
• getPanic() : Logger
• getParam() : CxxConfigFileBase , CxxIniFile
• getParamVector() : CxxConfigFileBase , CxxIniFile
• getParent() : LdsState
• getParentObject() : sc_gem5::Event
• getPathHist() : TAGEBase
• getPattern() : BaseDelta< BaseType, DeltaSizeBits > , CPack , DictionaryCompressor< T >::Factory< Head, Tail > , DictionaryCompressor< T >::Factory< Head > , DictionaryCompressor< T > , FPCD , RepeatedQwordsCompressor , ZeroCompressor
• getPatternEntry() : SignaturePathPrefetcher
• getPatternNumber() : DictionaryCompressor< T >::Pattern
• getPC() : BasePrefetcher::PrefetchInfo , MultiperspectivePerceptron::MPPBranchInfo , Request
• getPC2() : MultiperspectivePerceptron::MPPBranchInfo
• getPCState() : Trace::InstRecord
• getPeer() : EtherInt , Port
• getPendingFragment() : TimingSimpleCPU::SplitMainSenderState
• getPendingInt() : GicV2
• getPermission() : AbstractCacheEntry , PerfectCacheMemory< ENTRY >
• getPhysicalAddress() : RubyRequest
• getPhysMem() : RubySystem , System
• getPhysProxy() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext , ThreadState
• getPid() : BaseCPU
• getPipeReadSource() : PipeFDEntry
• getPointer() : MPP_StatisticalCorrector::MPP_SCThreadHistory
• getPort() : AbstractController , AddrMapper , ArmISA::TableWalker , BaseCache , BaseCPU , BaseTrafficGen , BaseXBar , Bridge , CommMonitor , ComputeUnit , CopyEngine::CopyEngineChannel , CopyEngine , DistEtherLink , DmaDevice , DRAMCtrl , DRAMSim2 , EtherBus , EtherLink , EtherSwitch , EtherTapBase , ExternalMaster , ExternalSlave , FastModel::CortexA76 , FastModel::CortexA76Cluster , FastModel::GIC , GarnetSyntheticTraffic , Gicv3Its , GpuDispatcher , IGbE , LdsState , MemCheckerMonitor , MemDelay , MemTest , MessageBuffer , Network , NSGigE , PioDevice , QoS::MemSinkCtrl , RubyDirectedTester , RubyPort , RubyTester , SerialLink , SimObject , SimpleCache , SimpleMemobj , SimpleMemory , Sinic::Device , SMMUv3 , SMMUv3SlaveInterface , System , TLBCoalescer , X86ISA::Cmos , X86ISA::GpuTLB , X86ISA::I8042 , X86ISA::I82094AA , X86ISA::I8254 , X86ISA::I8259 , X86ISA::Interrupts , X86ISA::Walker
• getPortDirectionName() : Router
• getPortId() : SimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS > , SimpleBusLT< NR_OF_INITIATORS, NR_OF_TARGETS >
• getPortPeers() : CxxConfigFileBase , CxxIniFile
• getPossibleEntries() : AssociativeSet< Entry > , BaseIndexingPolicy , SetAssociative , SkewedAssociative
• getPowerParams() : DRAMPower
• getPred() : Wavefront
• getPredictedAddresses() : PIFPrefetcher::CompactorEntry
• getPrediction() : LocalBP , TournamentBP
• getPrefetch() : RubyRequest
• getPrefetchEntry() : Prefetcher
• getPriority() : MessageBuffer
• getProbeManager() : ProbeListenerObject , SimObject
• getProcessPtr() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext , ThreadState
• getProfiler() : RubySystem
• getProgramCounter() : RubyRequest
• getPSMapping() : IrregularStreamBufferPrefetcher
• getPSTATEFromPSR() : ArmISA::ArmStaticInst
• getPtr() : Packet
• getQueueAddress() : VirtIODeviceBase
• getQueueSelect() : VirtIODeviceBase
• getQueueSize() : VirtIODeviceBase
• getQuiesceEvent() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext , ThreadState
• getRandomCheck() : CheckTable
• getRandomization() : RubySystem
• getRaw() : Packet
• getRawData() : ArmISA::TableWalker::DescriptorBase , ArmISA::TableWalker::L1Descriptor , ArmISA::TableWalker::L2Descriptor , ArmISA::TableWalker::LongDescriptor
• getReadableCpuPort() : RubyTester
• getReadQueueSize() : QoS::MemCtrl
• getRedistributor() : Gicv3 , Gicv3Its
• getRedistributorByAddr() : Gicv3
• getRedistributorByAffinity() : Gicv3
• getRefCounter() : ComputeUnit , LdsState
• getReg() : Scoreboard , SimpleFreeList
• getRegArrayBit() : X86ISA::Interrupts
• getRegElemIds() : PhysRegFile
• getRegIds() : PhysRegFile
• getRegisterIndex() : GPUDynInst , GPUStaticInst , HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::BrInstBase< TargetType > , HsailISA::BrnInstBase< TargetType > , HsailISA::Call , HsailISA::CbrInstBase< TargetType > , HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands > , HsailISA::LdaInstBase< DestOperandType, AddrOperandType > , HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType > , HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType > , HsailISA::SpecialInst1SrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcNoDest , HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType > , HsailISA::StInstBase< MemDataType, SrcOperandType, AddrOperandType > , HsailISA::Stub , HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType > , HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType > , KernelLaunchStaticInst
• getRegisters() : BaseKvmCPU
• getRegList() : ArmKvmCPU , BaseArmKvmCPU
• getRegs() : AlphaISA::RemoteGDB::AlphaGdbRegCache , ArmISA::RemoteGDB::AArch32GdbRegCache , ArmISA::RemoteGDB::AArch64GdbRegCache , BaseGdbRegCache , MipsISA::RemoteGDB::MipsGdbRegCache , PowerISA::RemoteGDB::PowerGdbRegCache , RiscvISA::RemoteGDB::RiscvGdbRegCache , SparcISA::RemoteGDB::SPARC64GdbRegCache , SparcISA::RemoteGDB::SPARCGdbRegCache , X86ISA::RemoteGDB::AMD64GdbRegCache , X86ISA::RemoteGDB::X86GdbRegCache
• getReplacementWeight() : CacheMemory
• getReqInstSeqNum() : Request
• getRequestStatus() : GPUCoalescer
• getResultTe() : ArmISA::TLB
• getRoutingAlgorithm() : GarnetNetwork
• getScheduledThread() : Minor::Decode , Minor::Fetch1 , Minor::Fetch2
• getSectionNames() : IniFile
• getSectionOffset() : BrigObject
• getSections() : ElfObject
• getSectorBlock() : SectorSubBlk
• getSectorOffset() : SectorSubBlk
• getSendFunctional() : BaseCPU , Iris::BaseCPU
• getServiceTick() : QoS::MemCtrl
• getSet() : ReplaceableEntry
• getSetIndex() : SimpleIndirectPredictor
• getSharing() : AccessTraceForAddress
• getSignatureEntry() : SignaturePathPrefetcher
• getSimFD() : HBFDEntry
• getSimObjectResolver() : CxxConfigManager
• getsize() : AlphaISA::TLB , ArmISA::TLB
• getSize() : BaseCacheCompressor::CompressionData , BasePrefetcher::PrefetchInfo , DirectoryMemory , DRAMCtrl::DRAMPacket , FDArray , flitBuffer , HsaCode , HsailCode , MessageBuffer
• getsize() : MipsISA::TLB
• getSize() : MultiperspectivePerceptron::LocalHistories , NetDest , Packet
• getsize() : PowerISA::TLB
• getSize() : Request
• getsize() : RiscvISA::TLB
• getSize() : RubyRequest , Set , StorageMap , StorageSpace , SubBlock , TimeBuffer< T > , Trace::InstRecord , VirtQueue
• getSizeBits() : BaseCacheCompressor::CompressionData , CompressionBlk , DictionaryCompressor< T >::Pattern
• getSizeInBits() : LoopPredictor , MPP_StatisticalCorrector_64KB , MPP_StatisticalCorrector_8KB , StatisticalCorrector , TAGEBase
• getSocket() : sc_gem5::Gem5ToTlmBridge< BITWIDTH > , sc_gem5::TlmToGem5Bridge< BITWIDTH >
• getSpecialRegisters() : BaseKvmCPU
• getSquaredTotal() : Histogram
• getSrcOperand() : ListOperand
• getstack() : AlphaISA::StackTrace , ArmISA::StackTrace , MipsISA::StackTrace , PowerISA::StackTrace , RiscvISA::StackTrace , SparcISA::StackTrace , X86ISA::StackTrace
• getStackBase() : MemState
• getStackMin() : MemState
• getStackSize() : MemState
• getStageActive() : ActivityRecorder
• getStallMapSize() : MessageBuffer
• getStandardDeviation() : Histogram
• getStartCycle() : RubySystem
• getStartPC() : Process
• getStatGroups() : Stats::Group
• getStaticContextSize() : GpuDispatcher , Wavefront
• getStaticInst() : Trace::InstRecord
• getStaticPower() : MathExprPowerModel , PowerModel , PowerModelState , SubSystem
• getStats() : Stats::Group
• getStatValue() : MathExprPowerModel
• getSTDIO() : ArmSemihosting
• getStoreHead() : LSQ< Impl > , LSQUnit< Impl >
• getStoreHeadSeqNum() : LSQ< Impl > , LSQUnit< Impl >
• getStrideEntry() : SignaturePathPrefetcher::PatternEntry
• getString() : BrigObject
• getStringLength() : X86ISA::SMBios::SMBiosStructure
• getSum() : StackDistCalc
• getSumsLeavesToRoot() : StackDistCalc
• getSymbolTable() : SymbolTable
• getSyndromeReg64() : ArmISA::ArmFault
• getSyscallArg() : AlphaProcess , ArmProcess32 , ArmProcess64 , MipsProcess , PowerLinuxProcess , PowerProcess , Process , RiscvProcess , Sparc32Process , Sparc64Process , X86ISA::I386Process , X86ISA::X86_64Process
• getSysRegMap() : ArmV8KvmCPU
• getSystem() : BaseGic
• getSystemPort() : System
• getSystemPtr() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• getTableAddr() : X86ISA::IntelMP::FloatingPointer , X86ISA::SMBios::SMBiosTable
• getTableWalker() : ArmISA::TLB
• getTableWalkerPort() : ArmISA::TLB , BaseTLB , X86ISA::TLB
• getTag() : DefaultBTB , SectorBlk , SectorSubBlk , SimpleIndirectPredictor , TaggedEntry
• getTageCtrBits() : TAGEBase
• getTagLatency() : CacheMemory
• getTarget() : LabelOperand , MSHR , QueueEntry , SRegOperand , WriteQueueEntry
• getTargetPc() : GPUStaticInst , HsailISA::BrInstBase< TargetType > , HsailISA::BrnInstBase< TargetType > , HsailISA::CbrInstBase< TargetType >
• getTaskDetails() : DumpStatsPCEvent64 , DumpStatsPCEvent
• getTC() : CpuEvent , O3ThreadState< Impl > , SimpleThread
• getTe() : ArmISA::Stage2LookUp
• getTE() : ArmISA::TLB
• getTemp() : ThermalModel
• getter() : BitfieldBackend::Signed< Storage, first, last > , BitfieldBackend::Unsigned< Storage, first, last > , BitfieldTypeImpl< Base > , X86ISA::SegDescriptorLimit
• getThermalModel() : System
• getThread() : Trace::InstRecord
• getThreadContext() : Arguments , System
• getThreadEntries() : ROB< Impl >
• getThrottle() : Switch
• getTick() : Time
• getTime() : Message
• getTimeCounterFromTicks() : A9GlobalTimer::Timer
• getTimers() : GenericTimer
• getTimingParams() : DRAMPower
• getTlb() : ArmISA::TableWalker
• getTLBEventVaddr() : X86ISA::GpuTLB::TLBEvent
• getTopFlit() : flitBuffer , InputUnit , VirtualChannel
• getTotal() : AccessTraceForAddress , Histogram , StoreTrace
• getTotalCount() : BloomFilter::Base , BloomFilter::Multi , BloomFilter::Perfect
• getTotalReadQueueSize() : QoS::MemCtrl
• getTotalWriteQueueSize() : QoS::MemCtrl
• getTouchedBy() : AccessTraceForAddress
• getTracer() : BaseCPU
• getTranslateLatency() : Request
• getTreeDepth() : StackDistCalc
• getTrueId() : PhysRegFile
• GetTsbPtr() : SparcISA::TLB
• getType() : AbstractController , MachineID , NetworkLink , RubyRequest
• getTypeLatencyHist() : GPUCoalescer , Sequencer
• getUintX() : Packet
• getUnit() : FUPool
• getUnknownPages() : FlashDevice
• getUseAltIdx() : MPP_TAGE , TAGE_SC_L_TAGE , TAGEBase
• getUtilization() : Throttle
• getVaddr() : LSQ< Impl >::LSQRequest , Request
• getValue() : ArmISA::PMU::CounterState , IniFile::Entry
• getVcLoad() : NetworkLink
• getVCpuEvents() : X86KvmCPU
• getVCpuID() : BaseKvmCPU
• getVCPUMMapSize() : Kvm
• getVCsPerVnet() : GarnetNetwork
• getVecElem() : UnifiedFreeList
• getVecPredReg() : UnifiedFreeList
• getVecReg() : UnifiedFreeList
• getVector() : ArmISA::ArmFault , ArmISA::Reset , X86ISA::I8259 , X86ISA::X86FaultBase
• getVector64() : ArmISA::ArmFault
• getVersion() : AbstractController
• getVictim() : BaseReplacementPolicy , BRRIPRP , FIFORP , LFURP , LRURP , MRURP , RandomRP , SecondChanceRP , TreePLRURP , WeightedLRUPolicy
• getVirtProxy() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext , ThreadState
• getVnet() : Message
• getVPENum() : MipsISA::ISA
• getWalker() : X86ISA::GpuTLB , X86ISA::TLB
• getWarmupEnabled() : RubySystem
• getWarn() : Logger
• getWay() : ReplaceableEntry
• getWayAllocationMax() : BaseSetAssoc , BaseTags
• getWhen() : Trace::InstRecord
• getWhenReady() : CacheBlk
• getWindowSize() : TraceCPU::ElasticDataGen::InputStream
• getWire() : TimeBuffer< T >
• getWritableArchVecPredReg() : FullO3CPU< Impl >
• getWritableArchVecReg() : FullO3CPU< Impl >
• getWritableCpuPort() : RubyTester
• getWritableVecPredReg() : CheckerThreadContext< TC > , FullO3CPU< Impl > , Iris::ThreadContext , O3ThreadContext< Impl > , PhysRegFile , SimpleThread , ThreadContext
• getWritableVecPredRegFlat() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• getWritableVecPredRegOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• getWritableVecReg() : CheckerThreadContext< TC > , FullO3CPU< Impl > , Iris::ThreadContext , O3ThreadContext< Impl > , PhysRegFile , SimpleThread , ThreadContext
• getWritableVecRegFlat() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• getWritableVecRegOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• getWriteQueueSize() : QoS::MemCtrl
• getXCRs() : X86KvmCPU
• getXferFeaturesRead() : ArmISA::RemoteGDB , BaseRemoteGDB
• getXSave() : X86KvmCPU
• GHIST() : MultiperspectivePerceptron::GHIST
• GHISTMODPATH() : MultiperspectivePerceptron::GHISTMODPATH
• GHISTPATH() : MultiperspectivePerceptron::GHISTPATH
• GIC() : FastModel::GIC
• GicV2() : GicV2
• Gicv2m() : Gicv2m
• Gicv2mFrame() : Gicv2mFrame
• Gicv3() : Gicv3
• Gicv3CPUInterface() : Gicv3CPUInterface
• Gicv3Distributor() : Gicv3Distributor
• Gicv3Its() : Gicv3Its
• Gicv3Redistributor() : Gicv3Redistributor
• gid() : Process
• gIndex() : StatisticalCorrector
• gindex() : TAGE_SC_L_TAGE , TAGEBase
• gindex_ext() : TAGE_SC_L_TAGE , TAGE_SC_L_TAGE_64KB , TAGE_SC_L_TAGE_8KB
• gIndexLogsSubstr() : MPP_StatisticalCorrector , StatisticalCorrector , TAGE_SC_L_64KB_StatisticalCorrector , TAGE_SC_L_8KB_StatisticalCorrector
• GlbMemUnitId() : ComputeUnit
• global() : ArmISA::TableWalker::DescriptorBase , ArmISA::TableWalker::L1Descriptor , ArmISA::TableWalker::L2Descriptor , ArmISA::TableWalker::LongDescriptor
• Global() : Stats::Global
• globalBarrier() : BaseGlobalEvent::BarrierEvent
• globalEvent() : BaseGlobalEvent::BarrierEvent , Event
• GlobalEvent() : GlobalEvent
• GlobalHistoryEntry() : SignaturePathPrefetcherV2::GlobalHistoryEntry
• globalMask() : RiscvISA::Interrupts
• GlobalMemPipeline() : GlobalMemPipeline
• Globals() : Globals
• GlobalSimLoopExitEvent() : GlobalSimLoopExitEvent
• GlobalSyncEvent() : GlobalSyncEvent
• goesAfter() : Trie< Key, Value >
• GoodbyeObject() : GoodbyeObject
• gPredict() : StatisticalCorrector
• gPredictions() : MPP_StatisticalCorrector_64KB , MPP_StatisticalCorrector_8KB , StatisticalCorrector , TAGE_SC_L_64KB_StatisticalCorrector , TAGE_SC_L_8KB_StatisticalCorrector
• GPUCoalescer() : GPUCoalescer
• GPUCoalescerRequest() : GPUCoalescerRequest
• GpuDispatcher() : GpuDispatcher
• GPUDynInst() : GPUDynInst
• GPUExecContext() : GPUExecContext
• GPUISA() : HsailISA::GPUISA
• gpuISA() : Wavefront
• gpuPanic() : NoMaliGpu
• GPUStaticInst() : GPUStaticInst
• GpuTLB() : X86ISA::GpuTLB
• grant_outport() : InputUnit
• grant_outvc() : InputUnit
• grant_switch() : Router
• granularity() : AddrRange
• greater() : flit
• Group() : Stats::Group
• groupEnabled() : Gicv3CPUInterface , Gicv3Distributor
• groupPriorityMask() : Gicv3CPUInterface
• grow_convert() : Stats::HistStor
• grow_out() : Stats::HistStor
• grow_up() : Stats::HistStor
• gtag() : TAGE_SC_L_TAGE , TAGE_SC_L_TAGE_64KB , TAGE_SC_L_TAGE_8KB , TAGEBase
• gUpdate() : MPP_StatisticalCorrector , StatisticalCorrector
• gUpdates() : MPP_StatisticalCorrector_64KB , MPP_StatisticalCorrector_8KB , StatisticalCorrector , TAGE_SC_L_64KB_StatisticalCorrector , TAGE_SC_L_8KB_StatisticalCorrector