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cpu.cc
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37 
38 #include "cpu/minor/cpu.hh"
39 
40 #include "arch/utility.hh"
41 #include "cpu/minor/dyn_inst.hh"
42 #include "cpu/minor/fetch1.hh"
43 #include "cpu/minor/pipeline.hh"
44 #include "debug/Drain.hh"
45 #include "debug/MinorCPU.hh"
46 #include "debug/Quiesce.hh"
47 
48 MinorCPU::MinorCPU(MinorCPUParams *params) :
49  BaseCPU(params),
50  threadPolicy(params->threadPolicy)
51 {
52  /* This is only written for one thread at the moment */
53  Minor::MinorThread *thread;
54 
55  for (ThreadID i = 0; i < numThreads; i++) {
56  if (FullSystem) {
57  thread = new Minor::MinorThread(this, i, params->system,
58  params->itb, params->dtb, params->isa[i]);
60  } else {
61  thread = new Minor::MinorThread(this, i, params->system,
62  params->workload[i], params->itb, params->dtb,
63  params->isa[i]);
64  }
65 
66  threads.push_back(thread);
67  ThreadContext *tc = thread->getTC();
68  threadContexts.push_back(tc);
69  }
70 
71 
72  if (params->checker) {
73  fatal("The Minor model doesn't support checking (yet)\n");
74  }
75 
77 
78  pipeline = new Minor::Pipeline(*this, *params);
79  activityRecorder = pipeline->getActivityRecorder();
80 }
81 
83 {
84  delete pipeline;
85 
86  for (ThreadID thread_id = 0; thread_id < threads.size(); thread_id++) {
87  delete threads[thread_id];
88  }
89 }
90 
91 void
93 {
94  BaseCPU::init();
95 
96  if (!params()->switched_out &&
97  system->getMemoryMode() != Enums::timing)
98  {
99  fatal("The Minor CPU requires the memory system to be in "
100  "'timing' mode.\n");
101  }
102 
103  /* Initialise the ThreadContext's memory proxies */
104  for (ThreadID thread_id = 0; thread_id < threads.size(); thread_id++) {
105  ThreadContext *tc = getContext(thread_id);
106 
107  tc->initMemProxies(tc);
108  }
109 }
110 
112 void
114 {
116  stats.regStats(name(), *this);
117  pipeline->regStats();
118 }
119 
120 void
122 {
123  threads[thread_id]->serialize(cp);
124 }
125 
126 void
128 {
129  threads[thread_id]->unserialize(cp);
130 }
131 
132 void
134 {
135  pipeline->serialize(cp);
136  BaseCPU::serialize(cp);
137 }
138 
139 void
141 {
142  pipeline->unserialize(cp);
144 }
145 
146 void
148 {
149  DPRINTF(Drain, "[tid:%d] MinorCPU wakeup\n", tid);
150  assert(tid < numThreads);
151 
152  if (threads[tid]->status() == ThreadContext::Suspended) {
153  threads[tid]->activate();
154  }
155 }
156 
157 void
159 {
160  DPRINTF(MinorCPU, "MinorCPU startup\n");
161 
163 
164  for (ThreadID tid = 0; tid < numThreads; tid++) {
165  threads[tid]->startup();
166  pipeline->wakeupFetch(tid);
167  }
168 }
169 
172 {
173  // Deschedule any power gating event (if any)
175 
176  if (switchedOut()) {
177  DPRINTF(Drain, "Minor CPU switched out, draining not needed.\n");
178  return DrainState::Drained;
179  }
180 
181  DPRINTF(Drain, "MinorCPU drain\n");
182 
183  /* Need to suspend all threads and wait for Execute to idle.
184  * Tell Fetch1 not to fetch */
185  if (pipeline->drain()) {
186  DPRINTF(Drain, "MinorCPU drained\n");
187  return DrainState::Drained;
188  } else {
189  DPRINTF(Drain, "MinorCPU not finished draining\n");
190  return DrainState::Draining;
191  }
192 }
193 
194 void
196 {
197  DPRINTF(Drain, "MinorCPU drain done\n");
199 }
200 
201 void
203 {
204  /* When taking over from another cpu make sure lastStopped
205  * is reset since it might have not been defined previously
206  * and might lead to a stats corruption */
207  pipeline->resetLastStopped();
208 
209  if (switchedOut()) {
210  DPRINTF(Drain, "drainResume while switched out. Ignoring\n");
211  return;
212  }
213 
214  DPRINTF(Drain, "MinorCPU drainResume\n");
215 
216  if (!system->isTimingMode()) {
217  fatal("The Minor CPU requires the memory system to be in "
218  "'timing' mode.\n");
219  }
220 
221  for (ThreadID tid = 0; tid < numThreads; tid++){
222  wakeup(tid);
223  }
224 
225  pipeline->drainResume();
226 
227  // Reschedule any power gating event (if any)
229 }
230 
231 void
233 {
234  DPRINTF(Drain, "MinorCPU memWriteback\n");
235 }
236 
237 void
239 {
240  DPRINTF(MinorCPU, "MinorCPU switchOut\n");
241 
242  assert(!switchedOut());
244 
245  /* Check that the CPU is drained? */
247 }
248 
249 void
251 {
252  DPRINTF(MinorCPU, "MinorCPU takeOverFrom\n");
253 
254  BaseCPU::takeOverFrom(old_cpu);
255 }
256 
257 void
259 {
260  DPRINTF(MinorCPU, "ActivateContext thread: %d\n", thread_id);
261 
262  /* Do some cycle accounting. lastStopped is reset to stop the
263  * wakeup call on the pipeline from adding the quiesce period
264  * to BaseCPU::numCycles */
265  stats.quiesceCycles += pipeline->cyclesSinceLastStopped();
266  pipeline->resetLastStopped();
267 
268  /* Wake up the thread, wakeup the pipeline tick */
269  threads[thread_id]->activate();
271  pipeline->wakeupFetch(thread_id);
272 
273  BaseCPU::activateContext(thread_id);
274 }
275 
276 void
278 {
279  DPRINTF(MinorCPU, "SuspendContext %d\n", thread_id);
280 
281  threads[thread_id]->suspend();
282 
283  BaseCPU::suspendContext(thread_id);
284 }
285 
286 void
287 MinorCPU::wakeupOnEvent(unsigned int stage_id)
288 {
289  DPRINTF(Quiesce, "Event wakeup from stage %d\n", stage_id);
290 
291  /* Mark that some activity has taken place and start the pipeline */
292  activityRecorder->activateStage(stage_id);
293  pipeline->start();
294 }
295 
296 MinorCPU *
297 MinorCPUParams::create()
298 {
299  return new MinorCPU(this);
300 }
301 
302 Port &
304 {
305  return pipeline->getInstPort();
306 }
307 
308 Port &
310 {
311  return pipeline->getDataPort();
312 }
313 
314 Counter
316 {
317  Counter ret = 0;
318 
319  for (auto i = threads.begin(); i != threads.end(); i ++)
320  ret += (*i)->numInst;
321 
322  return ret;
323 }
324 
325 Counter
327 {
328  Counter ret = 0;
329 
330  for (auto i = threads.begin(); i != threads.end(); i ++)
331  ret += (*i)->numOp;
332 
333  return ret;
334 }
void signalDrainDone()
Signal from Pipeline that MinorCPU should signal that a drain is complete and set its drainState...
Definition: cpu.cc:195
#define DPRINTF(x,...)
Definition: trace.hh:225
Ports are used to interface objects to each other.
Definition: port.hh:56
void regStats(const std::string &name, BaseCPU &baseCpu)
Definition: stats.cc:47
Port & getInstPort() override
Return a reference to the instruction port.
Definition: cpu.cc:303
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:171
Stats::Scalar quiesceCycles
Number of cycles in quiescent state.
Definition: stats.hh:71
Bitfield< 7 > i
ThreadID numThreads
Number of threads we&#39;re actually simulating (<= SMT_MAX_THREADS).
Definition: base.hh:374
Counter totalOps() const override
Definition: cpu.cc:326
void wakeupOnEvent(unsigned int stage_id)
Interface for stages to signal that they have become active after a callback or eventq event where th...
Definition: cpu.cc:287
void startup() override
startup() is the final initialization call before simulation.
Definition: cpu.cc:158
virtual void activateContext(ThreadID thread_num)
Notify the CPU that the indicated context is now active.
Definition: base.cc:487
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:132
bool switchedOut() const
Determine if the CPU is switched out.
Definition: base.hh:363
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
void setStatus(Status newStatus) override
Minor::Pipeline * pipeline
pipeline is a container for the clockable pipeline stage objects.
Definition: cpu.hh:82
void unserialize(CheckpointIn &cp) override
Reconstruct the state of this object from a checkpoint.
Definition: base.cc:700
void reset()
Clears the time buffer and the activity count.
Definition: activity.cc:124
System * system
Definition: base.hh:382
Definition: cprintf.cc:40
void drainResume() override
Resume execution after a successful drain.
Definition: cpu.cc:202
ThreadContext is the external interface to all thread state for anything outside of the CPU...
DrainState
Object drain/handover states.
Definition: drain.hh:71
DrainState drain() override
Drain interface.
Definition: cpu.cc:171
void regStats() override
Callback to set stat parameters.
Definition: base.cc:384
Bitfield< 5, 0 > status
std::vector< ThreadContext * > threadContexts
Definition: base.hh:263
void unserialize(CheckpointIn &cp) override
Reconstruct the state of this object from a checkpoint.
Definition: cpu.cc:140
Draining buffers pending serialization/handover.
void schedulePowerGatingEvent()
Definition: base.cc:459
void init() override
Starting, waking and initialisation.
Definition: cpu.cc:92
virtual void takeOverFrom(BaseCPU *cpu)
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
Definition: base.cc:555
void unserializeThread(CheckpointIn &cp, ThreadID tid) override
Unserialize one thread.
Definition: cpu.cc:127
void serialize(CheckpointOut &cp) const override
Serialize pipeline data.
Definition: cpu.cc:133
SimpleThread MinorThread
Minor will use the SimpleThread state for now.
Definition: cpu.hh:58
void activateStage(const int idx)
Marks a stage as active.
Definition: activity.cc:90
void startup() override
startup() is the final initialization call before simulation.
Definition: base.cc:320
void memWriteback() override
Write back dirty buffers to memory using functional writes.
Definition: cpu.cc:232
Minor::MinorActivityRecorder * activityRecorder
Activity recording for pipeline.
Definition: cpu.hh:88
static void init()
Initialise the class.
Definition: dyn_inst.cc:79
Enums::MemoryMode getMemoryMode() const
Get the memory mode of the system.
Definition: system.hh:165
ThreadContext * getTC()
Returns the pointer to this SimpleThread&#39;s ThreadContext.
int64_t Counter
Statistics counter type.
Definition: types.hh:56
void takeOverFrom(BaseCPU *old_cpu) override
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
Definition: cpu.cc:250
Port & getDataPort() override
Return a reference to the data port.
Definition: cpu.cc:309
virtual void switchOut()
Prepare for another CPU to take over execution.
Definition: base.cc:539
Fetch1 is responsible for fetching "lines" from memory and passing them to Fetch2.
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:225
virtual const std::string name() const
Definition: sim_object.hh:129
MinorCPU(MinorCPUParams *params)
Definition: cpu.cc:48
std::ostream CheckpointOut
Definition: serialize.hh:63
Permanently shut down.
void deschedulePowerGatingEvent()
Definition: base.cc:451
void suspendContext(ThreadID thread_id) override
Notify the CPU that the indicated context is now suspended.
Definition: cpu.cc:277
Top level definition of the Minor in-order CPU model.
void wakeup(ThreadID tid) override
Definition: cpu.cc:147
The dynamic instruction and instruction/line id (sequence numbers) definition for Minor...
virtual ThreadContext * getContext(int tn)
Given a thread num get tho thread context for it.
Definition: base.hh:294
std::vector< Minor::MinorThread * > threads
These are thread state-representing objects for this CPU.
Definition: cpu.hh:93
void signalDrainDone() const
Signal that an object is drained.
Definition: drain.hh:289
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: base.cc:277
The constructed pipeline.
void serialize(CheckpointOut &cp) const override
Serialize this object to the given output stream.
Definition: base.cc:679
Temporarily inactive.
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Definition: cpu.hh:77
bool isTimingMode() const
Is the system in timing mode?
Definition: system.hh:142
Minor::MinorStats stats
Processor-specific statistics.
Definition: cpu.hh:132
void activateContext(ThreadID thread_id) override
Thread activation interface from BaseCPU.
Definition: cpu.cc:258
virtual void initMemProxies(ThreadContext *tc)=0
Initialise the physical and virtual port proxies and tie them to the data port of the CPU...
Running normally.
The constructed pipeline.
Definition: pipeline.hh:69
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Serialize a single thread.
Definition: cpu.cc:121
const Params * params() const
Definition: base.hh:307
void switchOut() override
Switching interface from BaseCPU.
Definition: cpu.cc:238
void regStats() override
Stats interface from SimObject (by way of BaseCPU)
Definition: cpu.cc:113
Counter totalInsts() const override
Simple inst count interface from BaseCPU.
Definition: cpu.cc:315
~MinorCPU()
Definition: cpu.cc:82
virtual void suspendContext(ThreadID thread_num)
Notify the CPU that the indicated context is now suspended.
Definition: base.cc:501

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