gem5  v20.1.0.0
static_inst.hh
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28 
29 #ifndef __ARCH_POWER_INSTS_STATICINST_HH__
30 #define __ARCH_POWER_INSTS_STATICINST_HH__
31 
32 #include "base/trace.hh"
33 #include "cpu/static_inst.hh"
34 
35 namespace PowerISA
36 {
37 
39 {
40  protected:
41 
42  // Constructor
43  PowerStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
44  : StaticInst(mnem, _machInst, __opClass)
45  {
46  }
47 
48  // Insert a condition value into a CR (condition register) field
49  inline uint32_t
50  insertCRField(uint32_t cr, uint32_t bf, uint32_t value) const
51  {
52  uint32_t bits = value << ((7 - bf) * 4);
53  uint32_t mask = ~(0xf << ((7 - bf) * 4));
54  return (cr & mask) | bits;
55  }
56 
59  void
60  printReg(std::ostream &os, RegId reg) const;
61 
62  std::string generateDisassembly(
63  Addr pc, const Loader::SymbolTable *symtab) const override;
64 
65  void
66  advancePC(PowerISA::PCState &pcState) const override
67  {
68  pcState.advance();
69  }
70 
71  size_t
72  asBytes(void *buf, size_t max_size) override
73  {
74  return simpleAsBytes(buf, max_size, machInst);
75  }
76 };
77 
78 } // namespace PowerISA
79 
80 #endif //__ARCH_POWER_INSTS_STATICINST_HH__
X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:803
PowerISA::PowerStaticInst::insertCRField
uint32_t insertCRField(uint32_t cr, uint32_t bf, uint32_t value) const
Definition: static_inst.hh:50
StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:85
Loader::SymbolTable
Definition: symtab.hh:59
X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:87
RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:75
PowerISA::MachInst
uint32_t MachInst
Definition: types.hh:39
PowerISA
Definition: decoder.cc:31
MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
PowerISA::PowerStaticInst::printReg
void printReg(std::ostream &os, RegId reg) const
Print a register name for disassembly given the unique dependence tag number (FP or int).
Definition: static_inst.cc:37
static_inst.hh
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
StaticInst::simpleAsBytes
size_t simpleAsBytes(void *buf, size_t max_size, const T &t)
Definition: static_inst.hh:355
StaticInst::machInst
const ExtMachInst machInst
The binary machine instruction.
Definition: static_inst.hh:243
MipsISA::PCState
GenericISA::DelaySlotPCState< MachInst > PCState
Definition: types.hh:41
PowerISA::PowerStaticInst::PowerStaticInst
PowerStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
Definition: static_inst.hh:43
trace.hh
PowerISA::bf
Bitfield< 25, 23 > bf
Definition: types.hh:60
PowerISA::PowerStaticInst
Definition: static_inst.hh:38
PowerISA::PowerStaticInst::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: static_inst.cc:57
ArmISA::mask
Bitfield< 28, 24 > mask
Definition: miscregs_types.hh:711
PowerISA::PowerStaticInst::asBytes
size_t asBytes(void *buf, size_t max_size) override
Instruction classes can override this function to return a a representation of themselves as a blob o...
Definition: static_inst.hh:72
PowerISA::PowerStaticInst::advancePC
void advancePC(PowerISA::PCState &pcState) const override
Definition: static_inst.hh:66
bits
T bits(T val, int first, int last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:75

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