gem5  v20.1.0.0
faults.cc
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28 
29 #include "arch/sparc/faults.hh"
30 
31 #include <algorithm>
32 
33 #include "arch/sparc/isa_traits.hh"
34 #include "arch/sparc/process.hh"
35 #include "arch/sparc/tlb.hh"
36 #include "arch/sparc/types.hh"
37 #include "base/bitfield.hh"
38 #include "base/trace.hh"
39 #include "cpu/base.hh"
40 #include "cpu/thread_context.hh"
41 #include "mem/page_table.hh"
42 #include "sim/full_system.hh"
43 #include "sim/process.hh"
44 
45 using namespace std;
46 
47 namespace SparcISA
48 {
49 
50 template<> SparcFaultBase::FaultVals
51  SparcFault<PowerOnReset>::vals
52 ("power_on_reset", 0x001, 0, {{H, H, H}});
53 
54 template<> SparcFaultBase::FaultVals
55  SparcFault<WatchDogReset>::vals
56 ("watch_dog_reset", 0x002, 120, {{H, H, H}});
57 
58 template<> SparcFaultBase::FaultVals
59  SparcFault<ExternallyInitiatedReset>::vals
60 ("externally_initiated_reset", 0x003, 110, {{H, H, H}});
61 
62 template<> SparcFaultBase::FaultVals
63  SparcFault<SoftwareInitiatedReset>::vals
64 ("software_initiated_reset", 0x004, 130, {{SH, SH, H}});
65 
66 template<> SparcFaultBase::FaultVals
67  SparcFault<REDStateException>::vals
68 ("RED_state_exception", 0x005, 1, {{H, H, H}});
69 
70 template<> SparcFaultBase::FaultVals
71  SparcFault<StoreError>::vals
72 ("store_error", 0x007, 201, {{H, H, H}});
73 
74 template<> SparcFaultBase::FaultVals
75  SparcFault<InstructionAccessException>::vals
76 ("instruction_access_exception", 0x008, 300, {{H, H, H}});
77 
78 //XXX This trap is apparently dropped from ua2005
79 /*template<> SparcFaultBase::FaultVals
80  SparcFault<InstructionAccessMMUMiss>::vals
81  ("inst_mmu", 0x009, 2, {{H, H, H}});*/
82 
83 template<> SparcFaultBase::FaultVals
84  SparcFault<InstructionAccessError>::vals
85 ("instruction_access_error", 0x00A, 400, {{H, H, H}});
86 
87 template<> SparcFaultBase::FaultVals
88  SparcFault<IllegalInstruction>::vals
89 ("illegal_instruction", 0x010, 620, {{H, H, H}});
90 
91 template<> SparcFaultBase::FaultVals
92  SparcFault<PrivilegedOpcode>::vals
93 ("privileged_opcode", 0x011, 700, {{P, SH, SH}});
94 
95 //XXX This trap is apparently dropped from ua2005
96 /*template<> SparcFaultBase::FaultVals
97  SparcFault<UnimplementedLDD>::vals
98  ("unimp_ldd", 0x012, 6, {{H, H, H}});*/
99 
100 //XXX This trap is apparently dropped from ua2005
101 /*template<> SparcFaultBase::FaultVals
102  SparcFault<UnimplementedSTD>::vals
103  ("unimp_std", 0x013, 6, {{H, H, H}});*/
104 
105 template<> SparcFaultBase::FaultVals
106  SparcFault<FpDisabled>::vals
107 ("fp_disabled", 0x020, 800, {{P, P, H}});
108 
109 /* SPARCv8 and SPARCv9 define just fp_disabled trap. SIMD is not contemplated
110  * as a separate part. Therefore, we use the same code and TT */
111 template<> SparcFaultBase::FaultVals
112  SparcFault<VecDisabled>::vals
113 ("fp_disabled", 0x020, 800, {{P, P, H}});
114 
115 template<> SparcFaultBase::FaultVals
116  SparcFault<FpExceptionIEEE754>::vals
117 ("fp_exception_ieee_754", 0x021, 1110, {{P, P, H}});
118 
119 template<> SparcFaultBase::FaultVals
120  SparcFault<FpExceptionOther>::vals
121 ("fp_exception_other", 0x022, 1110, {{P, P, H}});
122 
123 template<> SparcFaultBase::FaultVals
124  SparcFault<TagOverflow>::vals
125 ("tag_overflow", 0x023, 1400, {{P, P, H}});
126 
127 template<> SparcFaultBase::FaultVals
128  SparcFault<CleanWindow>::vals
129 ("clean_window", 0x024, 1010, {{P, P, H}});
130 
131 template<> SparcFaultBase::FaultVals
132  SparcFault<DivisionByZero>::vals
133 ("division_by_zero", 0x028, 1500, {{P, P, H}});
134 
135 template<> SparcFaultBase::FaultVals
136  SparcFault<InternalProcessorError>::vals
137 ("internal_processor_error", 0x029, 4, {{H, H, H}});
138 
139 template<> SparcFaultBase::FaultVals
140  SparcFault<InstructionInvalidTSBEntry>::vals
141 ("instruction_invalid_tsb_entry", 0x02A, 210, {{H, H, SH}});
142 
143 template<> SparcFaultBase::FaultVals
144  SparcFault<DataInvalidTSBEntry>::vals
145 ("data_invalid_tsb_entry", 0x02B, 1203, {{H, H, H}});
146 
147 template<> SparcFaultBase::FaultVals
148  SparcFault<DataAccessException>::vals
149 ("data_access_exception", 0x030, 1201, {{H, H, H}});
150 
151 //XXX This trap is apparently dropped from ua2005
152 /*template<> SparcFaultBase::FaultVals
153  SparcFault<DataAccessMMUMiss>::vals
154  ("data_mmu", 0x031, 12, {{H, H, H}});*/
155 
156 template<> SparcFaultBase::FaultVals
157  SparcFault<DataAccessError>::vals
158 ("data_access_error", 0x032, 1210, {{H, H, H}});
159 
160 template<> SparcFaultBase::FaultVals
161  SparcFault<DataAccessProtection>::vals
162 ("data_access_protection", 0x033, 1207, {{H, H, H}});
163 
164 template<> SparcFaultBase::FaultVals
165  SparcFault<MemAddressNotAligned>::vals
166 ("mem_address_not_aligned", 0x034, 1020, {{H, H, H}});
167 
168 template<> SparcFaultBase::FaultVals
169  SparcFault<LDDFMemAddressNotAligned>::vals
170 ("LDDF_mem_address_not_aligned", 0x035, 1010, {{H, H, H}});
171 
172 template<> SparcFaultBase::FaultVals
173  SparcFault<STDFMemAddressNotAligned>::vals
174 ("STDF_mem_address_not_aligned", 0x036, 1010, {{H, H, H}});
175 
176 template<> SparcFaultBase::FaultVals
177  SparcFault<PrivilegedAction>::vals
178 ("privileged_action", 0x037, 1110, {{H, H, SH}});
179 
180 template<> SparcFaultBase::FaultVals
181  SparcFault<LDQFMemAddressNotAligned>::vals
182 ("LDQF_mem_address_not_aligned", 0x038, 1010, {{H, H, H}});
183 
184 template<> SparcFaultBase::FaultVals
185  SparcFault<STQFMemAddressNotAligned>::vals
186 ("STQF_mem_address_not_aligned", 0x039, 1010, {{H, H, H}});
187 
188 template<> SparcFaultBase::FaultVals
189  SparcFault<InstructionRealTranslationMiss>::vals
190 ("instruction_real_translation_miss", 0x03E, 208, {{H, H, SH}});
191 
192 template<> SparcFaultBase::FaultVals
193  SparcFault<DataRealTranslationMiss>::vals
194 ("data_real_translation_miss", 0x03F, 1203, {{H, H, H}});
195 
196 //XXX This trap is apparently dropped from ua2005
197 /*template<> SparcFaultBase::FaultVals
198  SparcFault<AsyncDataError>::vals
199  ("async_data", 0x040, 2, {{H, H, H}});*/
200 
201 template<> SparcFaultBase::FaultVals
202  SparcFault<InterruptLevelN>::vals
203 ("interrupt_level_n", 0x040, 0, {{P, P, SH}});
204 
205 template<> SparcFaultBase::FaultVals
206  SparcFault<HstickMatch>::vals
207 ("hstick_match", 0x05E, 1601, {{H, H, H}});
208 
209 template<> SparcFaultBase::FaultVals
210  SparcFault<TrapLevelZero>::vals
211 ("trap_level_zero", 0x05F, 202, {{H, H, SH}});
212 
213 template<> SparcFaultBase::FaultVals
214  SparcFault<InterruptVector>::vals
215 ("interrupt_vector", 0x060, 2630, {{H, H, H}});
216 
217 template<> SparcFaultBase::FaultVals
218  SparcFault<PAWatchpoint>::vals
219 ("PA_watchpoint", 0x061, 1209, {{H, H, H}});
220 
221 template<> SparcFaultBase::FaultVals
222  SparcFault<VAWatchpoint>::vals
223 ("VA_watchpoint", 0x062, 1120, {{P, P, SH}});
224 
225 template<> SparcFaultBase::FaultVals
226  SparcFault<FastInstructionAccessMMUMiss>::vals
227 ("fast_instruction_access_MMU_miss", 0x064, 208, {{H, H, SH}});
228 
229 template<> SparcFaultBase::FaultVals
230  SparcFault<FastDataAccessMMUMiss>::vals
231 ("fast_data_access_MMU_miss", 0x068, 1203, {{H, H, H}});
232 
233 template<> SparcFaultBase::FaultVals
234  SparcFault<FastDataAccessProtection>::vals
235 ("fast_data_access_protection", 0x06C, 1207, {{H, H, H}});
236 
237 template<> SparcFaultBase::FaultVals
238  SparcFault<InstructionBreakpoint>::vals
239 ("instruction_break", 0x076, 610, {{H, H, H}});
240 
241 template<> SparcFaultBase::FaultVals
242  SparcFault<CpuMondo>::vals
243 ("cpu_mondo", 0x07C, 1608, {{P, P, SH}});
244 
245 template<> SparcFaultBase::FaultVals
246  SparcFault<DevMondo>::vals
247 ("dev_mondo", 0x07D, 1611, {{P, P, SH}});
248 
249 template<> SparcFaultBase::FaultVals
250  SparcFault<ResumableError>::vals
251 ("resume_error", 0x07E, 3330, {{P, P, SH}});
252 
253 template<> SparcFaultBase::FaultVals
254  SparcFault<SpillNNormal>::vals
255 ("spill_n_normal", 0x080, 900, {{P, P, H}});
256 
257 template<> SparcFaultBase::FaultVals
258  SparcFault<SpillNOther>::vals
259 ("spill_n_other", 0x0A0, 900, {{P, P, H}});
260 
261 template<> SparcFaultBase::FaultVals
262  SparcFault<FillNNormal>::vals
263 ("fill_n_normal", 0x0C0, 900, {{P, P, H}});
264 
265 template<> SparcFaultBase::FaultVals
266  SparcFault<FillNOther>::vals
267 ("fill_n_other", 0x0E0, 900, {{P, P, H}});
268 
269 template<> SparcFaultBase::FaultVals
270  SparcFault<TrapInstruction>::vals
271 ("trap_instruction", 0x100, 1602, {{P, P, H}});
272 
278 void
279 enterREDState(ThreadContext *tc)
280 {
281  //@todo Disable the mmu?
282  //@todo Disable watchpoints?
283  HPSTATE hpstate= tc->readMiscRegNoEffect(MISCREG_HPSTATE);
284  hpstate.red = 1;
285  hpstate.hpriv = 1;
286  tc->setMiscReg(MISCREG_HPSTATE, hpstate);
287  // PSTATE.priv is set to 1 here. The manual says it should be 0, but
288  // Legion sets it to 1.
289  PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
290  pstate.priv = 1;
291  tc->setMiscReg(MISCREG_PSTATE, pstate);
292 }
293 
299 void
300 doREDFault(ThreadContext *tc, TrapType tt)
301 {
302  RegVal TL = tc->readMiscRegNoEffect(MISCREG_TL);
303  RegVal TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
304  PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
305  HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
306  CCR ccr = tc->readIntReg(INTREG_CCR);
307  RegVal ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
308  RegVal CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
309  RegVal CANSAVE = tc->readMiscRegNoEffect(INTREG_CANSAVE);
310  RegVal GL = tc->readMiscRegNoEffect(MISCREG_GL);
311  PCState pc = tc->pcState();
312 
313  TL++;
314 
315  Addr pcMask = pstate.am ? mask(32) : mask(64);
316 
317  // set TSTATE.gl to gl
318  replaceBits(TSTATE, 42, 40, GL);
319  // set TSTATE.ccr to ccr
320  replaceBits(TSTATE, 39, 32, ccr);
321  // set TSTATE.asi to asi
322  replaceBits(TSTATE, 31, 24, ASI);
323  // set TSTATE.pstate to pstate
324  replaceBits(TSTATE, 20, 8, pstate);
325  // set TSTATE.cwp to cwp
326  replaceBits(TSTATE, 4, 0, CWP);
327 
328  // Write back TSTATE
329  tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
330 
331  // set TPC to PC
332  tc->setMiscRegNoEffect(MISCREG_TPC, pc.pc() & pcMask);
333  // set TNPC to NPC
334  tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask);
335 
336  // set HTSTATE.hpstate to hpstate
337  tc->setMiscRegNoEffect(MISCREG_HTSTATE, hpstate);
338 
339  // TT = trap type;
340  tc->setMiscRegNoEffect(MISCREG_TT, tt);
341 
342  // Update GL
343  tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxGL));
344 
345  bool priv = pstate.priv; // just save the priv bit
346  pstate = 0;
347  pstate.priv = priv;
348  pstate.pef = 1;
349  tc->setMiscRegNoEffect(MISCREG_PSTATE, pstate);
350 
351  hpstate.red = 1;
352  hpstate.hpriv = 1;
353  hpstate.ibe = 0;
354  hpstate.tlz = 0;
355  tc->setMiscRegNoEffect(MISCREG_HPSTATE, hpstate);
356 
357  bool changedCWP = true;
358  if (tt == 0x24)
359  CWP++;
360  else if (0x80 <= tt && tt <= 0xbf)
361  CWP += (CANSAVE + 2);
362  else if (0xc0 <= tt && tt <= 0xff)
363  CWP--;
364  else
365  changedCWP = false;
366 
367  if (changedCWP) {
368  CWP = (CWP + NWindows) % NWindows;
369  tc->setMiscReg(MISCREG_CWP, CWP);
370  }
371 }
372 
378 void
379 doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
380 {
381  RegVal TL = tc->readMiscRegNoEffect(MISCREG_TL);
382  RegVal TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
383  PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
384  HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
385  CCR ccr = tc->readIntReg(INTREG_CCR);
386  RegVal ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
387  RegVal CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
388  RegVal CANSAVE = tc->readIntReg(INTREG_CANSAVE);
389  RegVal GL = tc->readMiscRegNoEffect(MISCREG_GL);
390  PCState pc = tc->pcState();
391 
392  // Increment the trap level
393  TL++;
394  tc->setMiscRegNoEffect(MISCREG_TL, TL);
395 
396  Addr pcMask = pstate.am ? mask(32) : mask(64);
397 
398  // Save off state
399 
400  // set TSTATE.gl to gl
401  replaceBits(TSTATE, 42, 40, GL);
402  // set TSTATE.ccr to ccr
403  replaceBits(TSTATE, 39, 32, ccr);
404  // set TSTATE.asi to asi
405  replaceBits(TSTATE, 31, 24, ASI);
406  // set TSTATE.pstate to pstate
407  replaceBits(TSTATE, 20, 8, pstate);
408  // set TSTATE.cwp to cwp
409  replaceBits(TSTATE, 4, 0, CWP);
410 
411  // Write back TSTATE
412  tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
413 
414  // set TPC to PC
415  tc->setMiscRegNoEffect(MISCREG_TPC, pc.pc() & pcMask);
416  // set TNPC to NPC
417  tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask);
418 
419  // set HTSTATE.hpstate to hpstate
420  tc->setMiscRegNoEffect(MISCREG_HTSTATE, hpstate);
421 
422  // TT = trap type;
423  tc->setMiscRegNoEffect(MISCREG_TT, tt);
424 
425  // Update the global register level
426  if (!gotoHpriv)
427  tc->setMiscReg(MISCREG_GL, min<int>(GL + 1, MaxPGL));
428  else
429  tc->setMiscReg(MISCREG_GL, min<int>(GL + 1, MaxGL));
430 
431  // pstate.mm is unchanged
432  pstate.pef = 1; // PSTATE.pef = whether or not an fpu is present
433  pstate.am = 0;
434  pstate.ie = 0;
435  // pstate.tle is unchanged
436  // pstate.tct = 0
437 
438  if (gotoHpriv) {
439  pstate.cle = 0;
440  // The manual says PSTATE.priv should be 0, but Legion leaves it alone
441  hpstate.red = 0;
442  hpstate.hpriv = 1;
443  hpstate.ibe = 0;
444  // hpstate.tlz is unchanged
445  tc->setMiscRegNoEffect(MISCREG_HPSTATE, hpstate);
446  } else { // we are going to priv
447  pstate.priv = 1;
448  pstate.cle = pstate.tle;
449  }
450  tc->setMiscRegNoEffect(MISCREG_PSTATE, pstate);
451 
452 
453  bool changedCWP = true;
454  if (tt == 0x24)
455  CWP++;
456  else if (0x80 <= tt && tt <= 0xbf)
457  CWP += (CANSAVE + 2);
458  else if (0xc0 <= tt && tt <= 0xff)
459  CWP--;
460  else
461  changedCWP = false;
462 
463  if (changedCWP) {
464  CWP = (CWP + NWindows) % NWindows;
465  tc->setMiscReg(MISCREG_CWP, CWP);
466  }
467 }
468 
469 void
470 getREDVector(RegVal TT, Addr &PC, Addr &NPC)
471 {
472  //XXX The following constant might belong in a header file.
473  const Addr RSTVAddr = 0xFFF0000000ULL;
474  PC = RSTVAddr | ((TT << 5) & 0xFF);
475  NPC = PC + sizeof(MachInst);
476 }
477 
478 void
479 getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, RegVal TT)
480 {
481  Addr HTBA = tc->readMiscRegNoEffect(MISCREG_HTBA);
482  PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
483  NPC = PC + sizeof(MachInst);
484 }
485 
486 void
487 getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT, RegVal TL)
488 {
489  Addr TBA = tc->readMiscRegNoEffect(MISCREG_TBA);
490  PC = (TBA & ~mask(15)) |
491  (TL > 1 ? (1 << 14) : 0) |
492  ((TT << 5) & mask(14));
493  NPC = PC + sizeof(MachInst);
494 }
495 
496 void
497 SparcFaultBase::invoke(ThreadContext * tc, const StaticInstPtr &inst)
498 {
499  FaultBase::invoke(tc);
500  if (!FullSystem)
501  return;
502 
503  countStat()++;
504 
505  // We can refer to this to see what the trap level -was-, but something
506  // in the middle could change it in the regfile out from under us.
507  RegVal tl = tc->readMiscRegNoEffect(MISCREG_TL);
508  RegVal tt = tc->readMiscRegNoEffect(MISCREG_TT);
509  PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
510  HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
511 
512  Addr PC, NPC;
513 
514  PrivilegeLevel current;
515  if (hpstate.hpriv)
516  current = Hyperprivileged;
517  else if (pstate.priv)
518  current = Privileged;
519  else
520  current = User;
521 
522  PrivilegeLevel level = getNextLevel(current);
523 
524  if (hpstate.red || (tl == MaxTL - 1)) {
525  getREDVector(5, PC, NPC);
526  doREDFault(tc, tt);
527  // This changes the hpstate and pstate, so we need to make sure we
528  // save the old version on the trap stack in doREDFault.
529  enterREDState(tc);
530  } else if (tl == MaxTL) {
531  panic("Should go to error state here.. crap\n");
532  // Do error_state somehow?
533  // Probably inject a WDR fault using the interrupt mechanism.
534  // What should the PC and NPC be set to?
535  } else if (tl > MaxPTL && level == Privileged) {
536  // guest_watchdog fault
537  doNormalFault(tc, trapType(), true);
538  getHyperVector(tc, PC, NPC, 2);
539  } else if (level == Hyperprivileged ||
540  (level == Privileged && trapType() >= 384)) {
541  doNormalFault(tc, trapType(), true);
542  getHyperVector(tc, PC, NPC, trapType());
543  } else {
544  doNormalFault(tc, trapType(), false);
545  getPrivVector(tc, PC, NPC, trapType(), tl + 1);
546  }
547 
548  PCState pc;
549  pc.pc(PC);
550  pc.npc(NPC);
551  pc.nnpc(NPC + sizeof(MachInst));
552  pc.upc(0);
553  pc.nupc(1);
554  tc->pcState(pc);
555 }
556 
557 void
558 PowerOnReset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
559 {
560  // For SPARC, when a system is first started, there is a power
561  // on reset Trap which sets the processor into the following state.
562  // Bits that aren't set aren't defined on startup.
563 
564  tc->setMiscRegNoEffect(MISCREG_TL, MaxTL);
565  tc->setMiscRegNoEffect(MISCREG_TT, trapType());
566  tc->setMiscReg(MISCREG_GL, MaxGL);
567 
568  PSTATE pstate = 0;
569  pstate.pef = 1;
570  pstate.priv = 1;
571  tc->setMiscRegNoEffect(MISCREG_PSTATE, pstate);
572 
573  // Turn on red and hpriv, set everything else to 0
574  HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
575  hpstate.red = 1;
576  hpstate.hpriv = 1;
577  hpstate.ibe = 0;
578  hpstate.tlz = 0;
579  tc->setMiscRegNoEffect(MISCREG_HPSTATE, hpstate);
580 
581  // The tick register is unreadable by nonprivileged software
582  tc->setMiscRegNoEffect(MISCREG_TICK, 1ULL << 63);
583 
584  // Enter RED state. We do this last so that the actual state preserved in
585  // the trap stack is the state from before this fault.
586  enterREDState(tc);
587 
588  Addr PC, NPC;
589  getREDVector(trapType(), PC, NPC);
590 
591  PCState pc;
592  pc.pc(PC);
593  pc.npc(NPC);
594  pc.nnpc(NPC + sizeof(MachInst));
595  pc.upc(0);
596  pc.nupc(1);
597  tc->pcState(pc);
598 
599  // These registers are specified as "undefined" after a POR, and they
600  // should have reasonable values after the miscregfile is reset
601  /*
602  // Clear all the soft interrupt bits
603  softint = 0;
604  // disable timer compare interrupts, reset tick_cmpr
605  tc->setMiscRegNoEffect(MISCREG_
606  tick_cmprFields.int_dis = 1;
607  tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
608  stickFields.npt = 1; // The TICK register is unreadable by by !priv
609  stick_cmprFields.int_dis = 1; // disable timer compare interrupts
610  stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
611 
612  tt[tl] = _trapType;
613 
614  hintp = 0; // no interrupts pending
615  hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
616  hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
617  */
618 }
619 
620 void
621 FastInstructionAccessMMUMiss::invoke(ThreadContext *tc,
622  const StaticInstPtr &inst)
623 {
624  if (FullSystem) {
625  SparcFaultBase::invoke(tc, inst);
626  return;
627  }
628 
629  Process *p = tc->getProcessPtr();
630  const EmulationPageTable::Entry *pte = p->pTable->lookup(vaddr);
631  panic_if(!pte, "Tried to execute unmapped address %#x.\n", vaddr);
632 
633  Addr alignedvaddr = p->pTable->pageAlign(vaddr);
634 
635  // Grab fields used during instruction translation to figure out
636  // which context to use.
637  uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
638 
639  // Inside a VM, a real address is the address that guest OS would
640  // interpret to be a physical address. To map to the physical address,
641  // it still needs to undergo a translation. The instruction
642  // translation code in the SPARC ITLB code assumes that the context is
643  // zero (kernel-level) if real addressing is being used.
644  bool is_real_address = !bits(tlbdata, 4);
645 
646  // The SPARC ITLB code assumes that traps are executed in context
647  // zero so we carry that assumption through here.
648  bool trapped = bits(tlbdata, 18, 16) > 0;
649 
650  // The primary context acts as a PASID. It allows the MMU to
651  // distinguish between virtual addresses that would alias to the
652  // same physical address (if two or more processes shared the same
653  // virtual address mapping).
654  int primary_context = bits(tlbdata, 47, 32);
655 
656  // The partition id distinguishes between virtualized environments.
657  int const partition_id = 0;
658 
659  // Given the assumptions in the translateInst code in the SPARC ITLB,
660  // the logic works out to the following for the context.
661  int context_id = (is_real_address || trapped) ? 0 : primary_context;
662 
663  TlbEntry entry(p->pTable->pid(), alignedvaddr, pte->paddr,
664  pte->flags & EmulationPageTable::Uncacheable,
665  pte->flags & EmulationPageTable::ReadOnly);
666 
667  // Insert the TLB entry.
668  // The entry specifying whether the address is "real" is set to
669  // false for syscall emulation mode regardless of whether the
670  // address is real in preceding code. Not sure sure that this is
671  // correct, but also not sure if it matters at all.
672  dynamic_cast<TLB *>(tc->getITBPtr())->
673  insert(alignedvaddr, partition_id, context_id, false, entry.pte);
674 }
675 
676 void
677 FastDataAccessMMUMiss::invoke(ThreadContext *tc, const StaticInstPtr &inst)
678 {
679  if (FullSystem) {
680  SparcFaultBase::invoke(tc, inst);
681  return;
682  }
683 
684  Process *p = tc->getProcessPtr();
685  const EmulationPageTable::Entry *pte = p->pTable->lookup(vaddr);
686  if (!pte && p->fixupFault(vaddr))
687  pte = p->pTable->lookup(vaddr);
688  panic_if(!pte, "Tried to access unmapped address %#x.\n", vaddr);
689 
690  Addr alignedvaddr = p->pTable->pageAlign(vaddr);
691 
692  // Grab fields used during data translation to figure out
693  // which context to use.
694  uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
695 
696  // The primary context acts as a PASID. It allows the MMU to
697  // distinguish between virtual addresses that would alias to the
698  // same physical address (if two or more processes shared the same
699  // virtual address mapping). There's a secondary context used in the
700  // DTLB translation code, but it should __probably__ be zero for
701  // syscall emulation code. (The secondary context is used by Solaris
702  // to allow kernel privilege code to access user space code:
703  // [ISBN 0-13-022496-0]:PG199.)
704  int primary_context = bits(tlbdata, 47, 32);
705 
706  // "Hyper-Privileged Mode" is in use. There are three main modes of
707  // operation for Sparc: Hyper-Privileged Mode, Privileged Mode, and
708  // User Mode.
709  int hpriv = bits(tlbdata, 0);
710 
711  // Reset, Error and Debug state is in use. Something horrible has
712  // happened or the system is operating in Reset Mode.
713  int red = bits(tlbdata, 1);
714 
715  // Inside a VM, a real address is the address that guest OS would
716  // interpret to be a physical address. To map to the physical address,
717  // it still needs to undergo a translation. The instruction
718  // translation code in the SPARC ITLB code assumes that the context is
719  // zero (kernel-level) if real addressing is being used.
720  int is_real_address = !bits(tlbdata, 5);
721 
722  // Grab the address space identifier register from the thread context.
723  // XXX: Inspecting how setMiscReg and setMiscRegNoEffect behave for
724  // MISCREG_ASI causes me to think that the ASI register implementation
725  // might be bugged. The NoEffect variant changes the ASI register
726  // value in the architectural state while the normal variant changes
727  // the context field in the thread context's currently decoded request
728  // but does not directly affect the ASI register value in the
729  // architectural state. The ASI values and the context field in the
730  // request packet seem to have completely different uses.
731  RegVal reg_asi = tc->readMiscRegNoEffect(MISCREG_ASI);
732  ASI asi = static_cast<ASI>(reg_asi);
733 
734  // The SPARC DTLB code assumes that traps are executed in context
735  // zero if the asi value is ASI_IMPLICIT (which is 0x0). There's also
736  // an assumption that the nucleus address space is being used, but
737  // the context is the relevant issue since we need to pass it to TLB.
738  bool trapped = bits(tlbdata, 18, 16) > 0;
739 
740  // Given the assumptions in the translateData code in the SPARC DTLB,
741  // the logic works out to the following for the context.
742  int context_id = ((!hpriv && !red && is_real_address) ||
743  asiIsReal(asi) ||
744  (trapped && asi == ASI_IMPLICIT))
745  ? 0 : primary_context;
746 
747  // The partition id distinguishes between virtualized environments.
748  int const partition_id = 0;
749 
750  TlbEntry entry(p->pTable->pid(), alignedvaddr, pte->paddr,
751  pte->flags & EmulationPageTable::Uncacheable,
752  pte->flags & EmulationPageTable::ReadOnly);
753 
754  // Insert the TLB entry.
755  // The entry specifying whether the address is "real" is set to
756  // false for syscall emulation mode regardless of whether the
757  // address is real in preceding code. Not sure sure that this is
758  // correct, but also not sure if it matters at all.
759  dynamic_cast<TLB *>(tc->getDTBPtr())->
760  insert(alignedvaddr, partition_id, context_id, false, entry.pte);
761 }
762 
763 void
764 SpillNNormal::invoke(ThreadContext *tc, const StaticInstPtr &inst)
765 {
766  if (FullSystem) {
767  SparcFaultBase::invoke(tc, inst);
768  return;
769  }
770 
771  doNormalFault(tc, trapType(), false);
772 
773  Process *p = tc->getProcessPtr();
774 
775  SparcProcess *sp = dynamic_cast<SparcProcess *>(p);
776  assert(sp);
777 
778  // Then adjust the PC and NPC
779  tc->pcState(sp->readSpillStart());
780 }
781 
782 void
783 FillNNormal::invoke(ThreadContext *tc, const StaticInstPtr &inst)
784 {
785  if (FullSystem) {
786  SparcFaultBase::invoke(tc, inst);
787  return;
788  }
789 
790  doNormalFault(tc, trapType(), false);
791 
792  Process *p = tc->getProcessPtr();
793 
794  SparcProcess *sp = dynamic_cast<SparcProcess *>(p);
795  assert(sp);
796 
797  // Then adjust the PC and NPC
798  tc->pcState(sp->readFillStart());
799 }
800 
801 void
802 TrapInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst)
803 {
804  if (FullSystem) {
805  SparcFaultBase::invoke(tc, inst);
806  return;
807  }
808 
809  // In SE, this mechanism is how the process requests a service from
810  // the operating system. We'll get the process object from the thread
811  // context and let it service the request.
812 
813  Process *p = tc->getProcessPtr();
814 
815  SparcProcess *sp = dynamic_cast<SparcProcess *>(p);
816  assert(sp);
817 
818  sp->handleTrap(_n, tc);
819 
820  // We need to explicitly advance the pc, since that's not done for us
821  // on a faulting instruction
822  PCState pc = tc->pcState();
823  pc.advance();
824  tc->pcState(pc);
825 }
826 
827 } // namespace SparcISA
828 
SparcISA::MachInst
uint32_t MachInst
Definition: types.hh:38
SparcISA::TLB
Definition: tlb.hh:50
ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
SparcISA::MISCREG_PSTATE
@ MISCREG_PSTATE
Definition: miscregs.hh:62
SparcISA::MISCREG_TSTATE
@ MISCREG_TSTATE
Definition: miscregs.hh:58
replaceBits
void replaceBits(T &val, int first, int last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:179
EmulationPageTable::Entry
Definition: page_table.hh:51
SparcISA::ASI_IMPLICIT
@ ASI_IMPLICIT
Definition: asi.hh:36
process.hh
SparcISA::getHyperVector
void getHyperVector(ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT)
Definition: faults.cc:479
SparcISA::getPrivVector
void getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT, RegVal TL)
Definition: faults.cc:487
EmulationPageTable::Uncacheable
@ Uncacheable
Definition: page_table.hh:93
Process
Definition: process.hh:65
SparcISA::MISCREG_HTSTATE
@ MISCREG_HTSTATE
Definition: miscregs.hh:75
ArmISA::MachInst
uint32_t MachInst
Definition: types.hh:52
SparcISA::MaxPGL
const int MaxPGL
Definition: sparc_traits.hh:38
SparcISA::MaxPTL
const int MaxPTL
Definition: sparc_traits.hh:35
SparcISA::MISCREG_TLB_DATA
@ MISCREG_TLB_DATA
Definition: miscregs.hh:112
SparcISA::TlbEntry
Definition: pagetable.hh:221
SparcISA::INTREG_CCR
@ INTREG_CCR
Definition: registers.hh:80
GenericISA::DelaySlotUPCState
Definition: types.hh:391
SparcISA::asiIsReal
bool asiIsReal(ASI asi)
Definition: asi.cc:139
FaultBase::invoke
virtual void invoke(ThreadContext *tc, const StaticInstPtr &inst=StaticInst::nullStaticInstPtr)
Definition: faults.cc:54
FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:132
ThreadContext::getProcessPtr
virtual Process * getProcessPtr()=0
SparcISA::MISCREG_TPC
@ MISCREG_TPC
Privilged Registers.
Definition: miscregs.hh:56
SparcISA::INTREG_CANSAVE
@ INTREG_CANSAVE
Definition: registers.hh:81
SparcISA::NWindows
const int NWindows
Definition: sparc_traits.hh:41
EmulationPageTable::Entry::flags
uint64_t flags
Definition: page_table.hh:54
SparcProcess
Definition: process.hh:44
SparcISA::TrapType
uint32_t TrapType
Definition: faults.hh:40
SparcISA
Definition: asi.cc:31
SparcISA::MISCREG_GL
@ MISCREG_GL
Definition: miscregs.hh:71
SparcISA::priv
Bitfield< 2 > priv
Definition: miscregs.hh:126
SparcISA::MISCREG_TT
@ MISCREG_TT
Definition: miscregs.hh:59
SparcISA::MISCREG_TICK
@ MISCREG_TICK
Definition: miscregs.hh:43
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
X86ISA::SH
SignedBitfield< 15, 8 > SH
Definition: int.hh:56
bitfield.hh
faults.hh
SparcISA::SparcFault< PowerOnReset >::vals
static FaultVals vals
Definition: faults.hh:83
SparcISA::MISCREG_TL
@ MISCREG_TL
Definition: miscregs.hh:63
MipsISA::vaddr
vaddr
Definition: pra_constants.hh:275
MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
isa_traits.hh
process.hh
MipsISA::tl
Bitfield< 23, 20 > tl
Definition: pra_constants.hh:251
SparcISA::SparcFaultBase::PrivilegeLevel
PrivilegeLevel
Definition: faults.hh:48
SparcISA::getREDVector
void getREDVector(RegVal TT, Addr &PC, Addr &NPC)
Definition: faults.cc:470
SparcISA::MaxGL
const int MaxGL
Definition: sparc_traits.hh:37
types.hh
ArmISA::sp
Bitfield< 0 > sp
Definition: miscregs_types.hh:71
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
SparcISA::ASI
ASI
Definition: asi.hh:35
ThreadContext::getITBPtr
virtual BaseTLB * getITBPtr()=0
full_system.hh
ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
SparcISA::doREDFault
void doREDFault(ThreadContext *tc, TrapType tt)
This sets everything up for a RED state trap except for actually jumping to the handler.
Definition: faults.cc:300
SparcISA::MISCREG_HPSTATE
@ MISCREG_HPSTATE
Hyper privileged registers.
Definition: miscregs.hh:74
X86ISA::level
Bitfield< 20 > level
Definition: intmessage.hh:47
MipsISA::FaultVals
MipsFaultBase::FaultVals FaultVals
Definition: faults.cc:43
EmulationPageTable::ReadOnly
@ ReadOnly
Definition: page_table.hh:94
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:197
SparcISA::MISCREG_ASI
@ MISCREG_ASI
Ancillary State Registers.
Definition: miscregs.hh:42
base.hh
SparcISA::red
Bitfield< 5 > red
Definition: miscregs.hh:119
std
Overload hash function for BasicBlockRange type.
Definition: vec_reg.hh:587
SparcISA::enterREDState
void enterREDState(ThreadContext *tc)
This causes the thread context to enter RED state.
Definition: faults.cc:279
EmulationPageTable::Entry::paddr
Addr paddr
Definition: page_table.hh:53
SparcISA::MISCREG_HTBA
@ MISCREG_HTBA
Definition: miscregs.hh:77
ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
SparcISA::hpriv
Bitfield< 2 > hpriv
Definition: miscregs.hh:118
RefCountingPtr< StaticInst >
trace.hh
X86ISA::H
Bitfield< 15, 8 > H
Definition: int.hh:55
ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
SparcISA::TlbEntry::pte
PageTableEntry pte
Definition: pagetable.hh:257
ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
SparcISA::MISCREG_TNPC
@ MISCREG_TNPC
Definition: miscregs.hh:57
page_table.hh
thread_context.hh
SparcISA::doNormalFault
void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
This sets everything up for a normal trap except for actually jumping to the handler.
Definition: faults.cc:379
tlb.hh
ULL
#define ULL(N)
uint64_t constant
Definition: types.hh:50
RegVal
uint64_t RegVal
Definition: types.hh:168
ThreadContext::getDTBPtr
virtual BaseTLB * getDTBPtr()=0
ArmISA::mask
Bitfield< 28, 24 > mask
Definition: miscregs_types.hh:711
SparcISA::MISCREG_CWP
@ MISCREG_CWP
Definition: miscregs.hh:65
SparcISA::MISCREG_TBA
@ MISCREG_TBA
Definition: miscregs.hh:61
SparcISA::MaxTL
const int MaxTL
Definition: sparc_traits.hh:36
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171
bits
T bits(T val, int first, int last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:75
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