gem5  v20.1.0.0
static_inst.cc
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3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
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38 
40 
41 #include "arch/x86/regs/segment.hh"
42 #include "cpu/reg_class.hh"
43 
44 namespace X86ISA
45 {
46  void X86StaticInst::printMnemonic(std::ostream &os,
47  const char * mnemonic) const
48  {
49  ccprintf(os, " %s ", mnemonic);
50  }
51 
52  void X86StaticInst::printMnemonic(std::ostream &os,
53  const char * instMnemonic, const char * mnemonic) const
54  {
55  ccprintf(os, " %s : %s ", instMnemonic, mnemonic);
56  }
57 
58  void X86StaticInst::printSegment(std::ostream &os, int segment) const
59  {
60  switch (segment)
61  {
62  case SEGMENT_REG_ES:
63  ccprintf(os, "ES");
64  break;
65  case SEGMENT_REG_CS:
66  ccprintf(os, "CS");
67  break;
68  case SEGMENT_REG_SS:
69  ccprintf(os, "SS");
70  break;
71  case SEGMENT_REG_DS:
72  ccprintf(os, "DS");
73  break;
74  case SEGMENT_REG_FS:
75  ccprintf(os, "FS");
76  break;
77  case SEGMENT_REG_GS:
78  ccprintf(os, "GS");
79  break;
80  case SEGMENT_REG_HS:
81  ccprintf(os, "HS");
82  break;
83  case SEGMENT_REG_TSL:
84  ccprintf(os, "TSL");
85  break;
86  case SEGMENT_REG_TSG:
87  ccprintf(os, "TSG");
88  break;
89  case SEGMENT_REG_LS:
90  ccprintf(os, "LS");
91  break;
92  case SEGMENT_REG_MS:
93  ccprintf(os, "MS");
94  break;
95  case SYS_SEGMENT_REG_TR:
96  ccprintf(os, "TR");
97  break;
99  ccprintf(os, "IDTR");
100  break;
101  default:
102  panic("Unrecognized segment %d\n", segment);
103  }
104  }
105 
106  void
107  X86StaticInst::printSrcReg(std::ostream &os, int reg, int size) const
108  {
109  if (_numSrcRegs > reg)
110  printReg(os, _srcRegIdx[reg], size);
111  }
112 
113  void
114  X86StaticInst::printDestReg(std::ostream &os, int reg, int size) const
115  {
116  if (_numDestRegs > reg)
117  printReg(os, _destRegIdx[reg], size);
118  }
119 
120  void
121  X86StaticInst::printReg(std::ostream &os, RegId reg, int size) const
122  {
123  assert(size == 1 || size == 2 || size == 4 || size == 8);
124  static const char * abcdFormats[9] =
125  {"", "%s", "%sx", "", "e%sx", "", "", "", "r%sx"};
126  static const char * piFormats[9] =
127  {"", "%s", "%s", "", "e%s", "", "", "", "r%s"};
128  static const char * longFormats[9] =
129  {"", "r%sb", "r%sw", "", "r%sd", "", "", "", "r%s"};
130  static const char * microFormats[9] =
131  {"", "t%db", "t%dw", "", "t%dd", "", "", "", "t%d"};
132 
133  RegIndex reg_idx = reg.index();
134 
135  if (reg.isIntReg()) {
136  const char * suffix = "";
137  bool fold = reg_idx & IntFoldBit;
138  reg_idx &= ~IntFoldBit;
139 
140  if (fold)
141  suffix = "h";
142  else if (reg_idx < 8 && size == 1)
143  suffix = "l";
144 
145  switch (reg_idx) {
146  case INTREG_RAX:
147  ccprintf(os, abcdFormats[size], "a");
148  break;
149  case INTREG_RBX:
150  ccprintf(os, abcdFormats[size], "b");
151  break;
152  case INTREG_RCX:
153  ccprintf(os, abcdFormats[size], "c");
154  break;
155  case INTREG_RDX:
156  ccprintf(os, abcdFormats[size], "d");
157  break;
158  case INTREG_RSP:
159  ccprintf(os, piFormats[size], "sp");
160  break;
161  case INTREG_RBP:
162  ccprintf(os, piFormats[size], "bp");
163  break;
164  case INTREG_RSI:
165  ccprintf(os, piFormats[size], "si");
166  break;
167  case INTREG_RDI:
168  ccprintf(os, piFormats[size], "di");
169  break;
170  case INTREG_R8W:
171  ccprintf(os, longFormats[size], "8");
172  break;
173  case INTREG_R9W:
174  ccprintf(os, longFormats[size], "9");
175  break;
176  case INTREG_R10W:
177  ccprintf(os, longFormats[size], "10");
178  break;
179  case INTREG_R11W:
180  ccprintf(os, longFormats[size], "11");
181  break;
182  case INTREG_R12W:
183  ccprintf(os, longFormats[size], "12");
184  break;
185  case INTREG_R13W:
186  ccprintf(os, longFormats[size], "13");
187  break;
188  case INTREG_R14W:
189  ccprintf(os, longFormats[size], "14");
190  break;
191  case INTREG_R15W:
192  ccprintf(os, longFormats[size], "15");
193  break;
194  default:
195  ccprintf(os, microFormats[size], reg_idx - NUM_INTREGS);
196  }
197  ccprintf(os, suffix);
198 
199  } else if (reg.isFloatReg()) {
200  if (reg_idx < NumMMXRegs) {
201  ccprintf(os, "%%mmx%d", reg_idx);
202  return;
203  }
204  reg_idx -= NumMMXRegs;
205  if (reg_idx < NumXMMRegs * 2) {
206  ccprintf(os, "%%xmm%d_%s", reg_idx / 2,
207  (reg_idx % 2) ? "high": "low");
208  return;
209  }
210  reg_idx -= NumXMMRegs * 2;
211  if (reg_idx < NumMicroFpRegs) {
212  ccprintf(os, "%%ufp%d", reg_idx);
213  return;
214  }
215  reg_idx -= NumMicroFpRegs;
216  ccprintf(os, "%%st(%d)", reg_idx);
217 
218  } else if (reg.isCCReg()) {
219  ccprintf(os, "%%cc%d", reg_idx);
220 
221  } else if (reg.isMiscReg()) {
222  switch (reg_idx) {
223  default:
224  ccprintf(os, "%%ctrl%d", reg_idx);
225  }
226  }
227  }
228 
229  void X86StaticInst::printMem(std::ostream &os, uint8_t segment,
230  uint8_t scale, RegIndex index, RegIndex base,
231  uint64_t disp, uint8_t addressSize, bool rip) const
232  {
233  bool someAddr = false;
234  printSegment(os, segment);
235  os << ":[";
236  if (rip) {
237  os << "rip";
238  someAddr = true;
239  } else {
240  if (scale != 0 && index != ZeroReg)
241  {
242  if (scale != 1)
243  ccprintf(os, "%d*", scale);
244  printReg(os, InstRegIndex(index), addressSize);
245  someAddr = true;
246  }
247  if (base != ZeroReg)
248  {
249  if (someAddr)
250  os << " + ";
251  printReg(os, InstRegIndex(base), addressSize);
252  someAddr = true;
253  }
254  }
255  if (disp != 0)
256  {
257  if (someAddr)
258  os << " + ";
259  ccprintf(os, "%#x", disp);
260  someAddr = true;
261  }
262  if (!someAddr)
263  os << "0";
264  os << "]";
265  }
266 
267  std::string
269  Addr pc, const Loader::SymbolTable *symtab) const
270  {
271  std::stringstream ss;
272 
274 
275  return ss.str();
276  }
277 }
X86ISA::IntFoldBit
static const IntRegIndex IntFoldBit
Definition: int.hh:151
X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:803
static_inst.hh
X86ISA::SEGMENT_REG_FS
@ SEGMENT_REG_FS
Definition: segment.hh:49
X86ISA::SEGMENT_REG_TSG
@ SEGMENT_REG_TSG
Definition: segment.hh:53
Loader::SymbolTable
Definition: symtab.hh:59
X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
X86ISA::X86StaticInst::printDestReg
void printDestReg(std::ostream &os, int reg, int size) const
Definition: static_inst.cc:114
X86ISA::SYS_SEGMENT_REG_IDTR
@ SYS_SEGMENT_REG_IDTR
Definition: segment.hh:60
X86ISA::NumMicroFpRegs
const int NumMicroFpRegs
Definition: x86_traits.hh:59
X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:87
X86ISA::scale
scale
Definition: types.hh:92
X86ISA::SEGMENT_REG_LS
@ SEGMENT_REG_LS
Definition: segment.hh:54
X86ISA::X86StaticInst::printReg
void printReg(std::ostream &os, RegId reg, int size) const
Definition: static_inst.cc:121
RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:75
X86ISA::SEGMENT_REG_HS
@ SEGMENT_REG_HS
Definition: segment.hh:51
X86ISA::InstRegIndex
Class for register indices passed to instruction constructors.
Definition: static_inst.hh:52
X86ISA::SEGMENT_REG_TSL
@ SEGMENT_REG_TSL
Definition: segment.hh:52
X86ISA::index
Bitfield< 5, 3 > index
Definition: types.hh:93
ArmISA::ss
Bitfield< 21 > ss
Definition: miscregs_types.hh:56
X86ISA::SEGMENT_REG_MS
@ SEGMENT_REG_MS
Definition: segment.hh:55
segment.hh
StaticInst::_srcRegIdx
RegId _srcRegIdx[MaxInstSrcRegs]
See srcRegIdx().
Definition: static_inst.hh:250
StaticInst::_destRegIdx
RegId _destRegIdx[MaxInstDestRegs]
See destRegIdx().
Definition: static_inst.hh:248
X86ISA::X86StaticInst::printSegment
void printSegment(std::ostream &os, int segment) const
Definition: static_inst.cc:58
X86ISA::X86StaticInst::printMnemonic
void printMnemonic(std::ostream &os, const char *mnemonic) const
Definition: static_inst.cc:46
X86ISA::X86StaticInst::printMem
void printMem(std::ostream &os, uint8_t segment, uint8_t scale, RegIndex index, RegIndex base, uint64_t disp, uint8_t addressSize, bool rip) const
Definition: static_inst.cc:229
StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:258
X86ISA::X86StaticInst::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: static_inst.cc:268
X86ISA
This is exposed globally, independent of the ISA.
Definition: acpi.hh:55
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
X86ISA::ZeroReg
const int ZeroReg
Definition: registers.hh:84
X86ISA::NumXMMRegs
const int NumXMMRegs
Definition: x86_traits.hh:58
X86ISA::SEGMENT_REG_DS
@ SEGMENT_REG_DS
Definition: segment.hh:48
X86ISA::SEGMENT_REG_SS
@ SEGMENT_REG_SS
Definition: segment.hh:47
X86ISA::SEGMENT_REG_CS
@ SEGMENT_REG_CS
Definition: segment.hh:46
RegIndex
uint16_t RegIndex
Definition: types.hh:52
X86ISA::SYS_SEGMENT_REG_TR
@ SYS_SEGMENT_REG_TR
Definition: segment.hh:59
X86ISA::X86StaticInst::printSrcReg
void printSrcReg(std::ostream &os, int reg, int size) const
Definition: static_inst.cc:107
ArmISA::NUM_INTREGS
@ NUM_INTREGS
Definition: intregs.hh:123
reg_class.hh
ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:127
X86ISA::SEGMENT_REG_ES
@ SEGMENT_REG_ES
Definition: segment.hh:45
X86ISA::SEGMENT_REG_GS
@ SEGMENT_REG_GS
Definition: segment.hh:50
StaticInst::_numSrcRegs
int8_t _numSrcRegs
See numSrcRegs().
Definition: static_inst.hh:105
X86ISA::pc
Bitfield< 19 > pc
Definition: misc.hh:805
StaticInst::_numDestRegs
int8_t _numDestRegs
See numDestRegs().
Definition: static_inst.hh:108
X86ISA::NumMMXRegs
const int NumMMXRegs
Definition: x86_traits.hh:57
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171

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