gem5  v20.1.0.0
isa.hh
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28 
29 #ifndef __ARCH_MIPS_ISA_HH__
30 #define __ARCH_MIPS_ISA_HH__
31 
32 #include <queue>
33 #include <string>
34 #include <vector>
35 
36 #include "arch/generic/isa.hh"
37 #include "arch/mips/registers.hh"
38 #include "arch/mips/types.hh"
39 #include "cpu/reg_class.hh"
40 #include "sim/eventq.hh"
41 #include "sim/sim_object.hh"
42 
43 class BaseCPU;
44 class Checkpoint;
45 class EventManager;
46 struct MipsISAParams;
47 class ThreadContext;
48 
49 namespace MipsISA
50 {
51  class ISA : public BaseISA
52  {
53  public:
54  // The MIPS name for this file is CP0 or Coprocessor 0
55  typedef ISA CP0;
56 
57  typedef MipsISAParams Params;
58 
59  protected:
60  // Number of threads and vpes an individual ISA state can handle
61  uint8_t numThreads;
62  uint8_t numVpes;
63 
64  enum BankType {
68  };
69 
73 
74  public:
75  void clear();
76 
77  public:
78  void configCP();
79 
80  unsigned getVPENum(ThreadID tid) const;
81 
83  //
84  // READ/WRITE CP0 STATE
85  //
86  //
88  //@TODO: MIPS MT's register view automatically connects
89  // Status to TCStatus depending on current thread
90  void updateCP0ReadView(int misc_reg, ThreadID tid) { }
91  RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
92 
93  //template <class TC>
94  RegVal readMiscReg(int misc_reg, ThreadID tid = 0);
95 
96  RegVal filterCP0Write(int misc_reg, int reg_sel, RegVal val);
97  void setRegMask(int misc_reg, RegVal val, ThreadID tid = 0);
98  void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0);
99 
100  //template <class TC>
101  void setMiscReg(int misc_reg, RegVal val, ThreadID tid=0);
102 
104  //
105  // DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0)
106  // TO SCHEDULE EVENTS
107  //
109 
110  // Flag that is set when CP0 state has been written to.
112 
113  // Enumerated List of CP0 Event Types
116  };
117 
120 
121  // Schedule a CP0 Update Event
122  void scheduleCP0Update(BaseCPU *cpu, Cycles delay = Cycles(0));
123 
124  // If any changes have been made, then check the state for changes
125  // and if necessary alert the CPU
126  void updateCPU(BaseCPU *cpu);
127 
128  static std::string miscRegNames[NumMiscRegs];
129 
130  public:
131  const Params *params() const;
132 
133  ISA(Params *p);
134 
135  RegId flattenRegId(const RegId& regId) const { return regId; }
136 
137  int flattenIntIndex(int reg) const { return reg; }
138  int flattenFloatIndex(int reg) const { return reg; }
139  int flattenVecIndex(int reg) const { return reg; }
140  int flattenVecElemIndex(int reg) const { return reg; }
141  int flattenVecPredIndex(int reg) const { return reg; }
142  // dummy
143  int flattenCCIndex(int reg) const { return reg; }
144  int flattenMiscIndex(int reg) const { return reg; }
145  };
146 }
147 
148 #endif
MipsISA::ISA::configCP
void configCP()
Definition: isa.cc:163
MipsISA::ISA::bankType
std::vector< BankType > bankType
Definition: isa.hh:72
MipsISA::ISA
Definition: isa.hh:51
MipsISA::ISA::flattenVecElemIndex
int flattenVecElemIndex(int reg) const
Definition: isa.hh:140
registers.hh
MipsISA::ISA::clear
void clear()
Definition: isa.cc:150
MipsISA::ISA::BankType
BankType
Definition: isa.hh:64
MipsISA::ISA::numVpes
uint8_t numVpes
Definition: isa.hh:62
types.hh
ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:227
MipsISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0)
Definition: isa.cc:446
MipsISA::ISA::flattenRegId
RegId flattenRegId(const RegId &regId) const
Definition: isa.hh:135
MipsISA::ISA::miscRegNames
static std::string miscRegNames[NumMiscRegs]
Definition: isa.hh:128
MipsISA::ISA::params
const Params * params() const
Definition: isa.cc:144
std::vector
STL vector class.
Definition: stl.hh:37
MipsISA::ISA::Params
MipsISAParams Params
Definition: isa.hh:57
MipsISA::ISA::miscRegFile_WriteMask
std::vector< std::vector< RegVal > > miscRegFile_WriteMask
Definition: isa.hh:71
X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:87
MipsISA
Definition: decoder.cc:31
RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:75
MipsISA::ISA::flattenVecIndex
int flattenVecIndex(int reg) const
Definition: isa.hh:139
MipsISA::ISA::CP0
ISA CP0
Definition: isa.hh:55
MipsISA::ISA::perThreadContext
@ perThreadContext
Definition: isa.hh:66
MipsISA::ISA::cp0Updated
bool cp0Updated
Definition: isa.hh:111
MipsISA::ISA::UpdateCP0
@ UpdateCP0
Definition: isa.hh:115
MipsISA::ISA::readMiscReg
RegVal readMiscReg(int misc_reg, ThreadID tid=0)
Definition: isa.cc:433
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
MipsISA::ISA::filterCP0Write
RegVal filterCP0Write(int misc_reg, int reg_sel, RegVal val)
This method doesn't need to adjust the Control Register Offset since it has already been done in the ...
Definition: isa.cc:497
MipsISA::ISA::flattenIntIndex
int flattenIntIndex(int reg) const
Definition: isa.hh:137
MipsISA::ISA::ISA
ISA(Params *p)
Definition: isa.cc:90
sim_object.hh
MipsISA::ISA::flattenVecPredIndex
int flattenVecPredIndex(int reg) const
Definition: isa.hh:141
MipsISA::ISA::miscRegFile
std::vector< std::vector< RegVal > > miscRegFile
Definition: isa.hh:70
X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
MipsISA::ISA::CP0EventType
CP0EventType
Definition: isa.hh:114
MipsISA::ISA::flattenMiscIndex
int flattenMiscIndex(int reg) const
Definition: isa.hh:144
MipsISA::ISA::numThreads
uint8_t numThreads
Definition: isa.hh:61
MipsISA::ISA::updateCPU
void updateCPU(BaseCPU *cpu)
Definition: isa.cc:531
BaseCPU
Definition: cpu_dummy.hh:43
MipsISA::ISA::perProcessor
@ perProcessor
Definition: isa.hh:65
isa.hh
MipsISA::ISA::setMiscReg
void setMiscReg(int misc_reg, RegVal val, ThreadID tid=0)
Definition: isa.cc:474
MipsISA::ISA::processCP0Event
void processCP0Event(BaseCPU *cpu, CP0EventType)
Process a CP0 event.
Definition: isa.cc:560
MipsISA::ISA::flattenFloatIndex
int flattenFloatIndex(int reg) const
Definition: isa.hh:138
MipsISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid=0) const
Definition: isa.cc:419
MipsISA::NumMiscRegs
const int NumMiscRegs
Definition: registers.hh:280
MipsISA::ISA::perVirtProcessor
@ perVirtProcessor
Definition: isa.hh:67
reg_class.hh
Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:83
MipsISA::ISA::updateCP0ReadView
void updateCP0ReadView(int misc_reg, ThreadID tid)
Definition: isa.hh:90
MipsISA::ISA::getVPENum
unsigned getVPENum(ThreadID tid) const
Definition: isa.cc:412
EventManager
Definition: eventq.hh:973
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
MipsISA::ISA::scheduleCP0Update
void scheduleCP0Update(BaseCPU *cpu, Cycles delay=Cycles(0))
Definition: isa.cc:517
BaseISA
Definition: isa.hh:47
MipsISA::ISA::setRegMask
void setRegMask(int misc_reg, RegVal val, ThreadID tid=0)
Definition: isa.cc:459
MipsISA::ISA::flattenCCIndex
int flattenCCIndex(int reg) const
Definition: isa.hh:143
RegVal
uint64_t RegVal
Definition: types.hh:168
eventq.hh

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