gem5  v20.1.0.0
branch.hh
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28 
29 #ifndef __ARCH_POWER_INSTS_BRANCH_HH__
30 #define __ARCH_POWER_INSTS_BRANCH_HH__
31 
33 
34 namespace PowerISA
35 {
36 
47 {
48  protected:
50  mutable Addr cachedPC;
53 
55  PCDependentDisassembly(const char *mnem, ExtMachInst _machInst,
56  OpClass __opClass)
57  : PowerStaticInst(mnem, _machInst, __opClass),
58  cachedPC(0), cachedSymtab(0)
59  {
60  }
61 
62  const std::string &
63  disassemble(Addr pc, const Loader::SymbolTable *symtab) const;
64 };
65 
70 {
71  protected:
72 
74  uint32_t disp;
75 
77  BranchPCRel(const char *mnem, MachInst _machInst, OpClass __opClass)
78  : PCDependentDisassembly(mnem, _machInst, __opClass),
79  disp(machInst.li << 2)
80  {
81  // If bit 26 is 1 then sign extend
82  if (disp & 0x2000000) {
83  disp |= 0xfc000000;
84  }
85  }
86 
87  PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override;
88 
91 
92  std::string generateDisassembly(
93  Addr pc, const Loader::SymbolTable *symtab) const override;
94 };
95 
100 {
101  protected:
102 
104  uint32_t targetAddr;
105 
107  BranchNonPCRel(const char *mnem, MachInst _machInst, OpClass __opClass)
108  : PCDependentDisassembly(mnem, _machInst, __opClass),
109  targetAddr(machInst.li << 2)
110  {
111  // If bit 26 is 1 then sign extend
112  if (targetAddr & 0x2000000) {
113  targetAddr |= 0xfc000000;
114  }
115  }
116 
117  PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override;
118 
121 
122  std::string generateDisassembly(
123  Addr pc, const Loader::SymbolTable *symtab) const override;
124 };
125 
130 {
131  protected:
132 
134  uint32_t bo;
135  uint32_t bi;
136 
138  BranchCond(const char *mnem, MachInst _machInst, OpClass __opClass)
139  : PCDependentDisassembly(mnem, _machInst, __opClass),
140  bo(machInst.bo),
141  bi(machInst.bi)
142  {
143  }
144 
145  inline bool
146  ctrOk(uint32_t& ctr) const
147  {
148  bool ctr_ok;
149  if (bo & 4) {
150  ctr_ok = true;
151  } else {
152  ctr--;
153  if (ctr != 0) {
154  ctr_ok = ((bo & 2) == 0);
155  } else {
156  ctr_ok = ((bo & 2) != 0);
157  }
158  }
159  return ctr_ok;
160  }
161 
162  inline bool
163  condOk(uint32_t cr) const
164  {
165  bool cond_ok;
166  if (bo & 16) {
167  cond_ok = true;
168  } else {
169  cond_ok = (((cr >> (31 - bi)) & 1) == ((bo >> 3) & 1));
170  }
171  return cond_ok;
172  }
173 };
174 
179 {
180  protected:
181 
183  uint32_t disp;
184 
186  BranchPCRelCond(const char *mnem, MachInst _machInst, OpClass __opClass)
187  : BranchCond(mnem, _machInst, __opClass),
188  disp(machInst.bd << 2)
189  {
190  // If bit 16 is 1 then sign extend
191  if (disp & 0x8000) {
192  disp |= 0xffff0000;
193  }
194  }
195 
196  PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override;
197 
200 
201  std::string generateDisassembly(
202  Addr pc, const Loader::SymbolTable *symtab) const override;
203 };
204 
209 {
210  protected:
211 
213  uint32_t targetAddr;
214 
216  BranchNonPCRelCond(const char *mnem, MachInst _machInst, OpClass __opClass)
217  : BranchCond(mnem, _machInst, __opClass),
218  targetAddr(machInst.bd << 2)
219  {
220  // If bit 16 is 1 then sign extend
221  if (targetAddr & 0x8000) {
222  targetAddr |= 0xffff0000;
223  }
224  }
225 
226  PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override;
227 
230 
231  std::string generateDisassembly(
232  Addr pc, const Loader::SymbolTable *symtab) const override;
233 };
234 
238 class BranchRegCond : public BranchCond
239 {
240  protected:
241 
243  BranchRegCond(const char *mnem, MachInst _machInst, OpClass __opClass)
244  : BranchCond(mnem, _machInst, __opClass)
245  {
246  }
247 
248  PowerISA::PCState branchTarget(ThreadContext *tc) const override;
249 
252 
253  std::string generateDisassembly(
254  Addr pc, const Loader::SymbolTable *symtab) const override;
255 };
256 
257 } // namespace PowerISA
258 
259 #endif //__ARCH_POWER_INSTS_BRANCH_HH__
PowerISA::BranchCond::BranchCond
BranchCond(const char *mnem, MachInst _machInst, OpClass __opClass)
Constructor.
Definition: branch.hh:138
PowerISA::BranchNonPCRel::BranchNonPCRel
BranchNonPCRel(const char *mnem, MachInst _machInst, OpClass __opClass)
Constructor.
Definition: branch.hh:107
PowerISA::BranchCond::bi
uint32_t bi
Definition: branch.hh:135
PowerISA::BranchRegCond::branchTarget
PowerISA::PCState branchTarget(ThreadContext *tc) const override
Return the target address for an indirect branch (jump).
Definition: branch.cc:156
PowerISA::BranchCond::ctrOk
bool ctrOk(uint32_t &ctr) const
Definition: branch.hh:146
PowerISA::BranchNonPCRel::branchTarget
PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override
Definition: branch.cc:81
PowerISA::PCDependentDisassembly::cachedSymtab
const Loader::SymbolTable * cachedSymtab
Cached symbol table pointer from last disassembly.
Definition: branch.hh:52
Loader::SymbolTable
Definition: symtab.hh:59
PowerISA::BranchPCRelCond::disp
uint32_t disp
Displacement.
Definition: branch.hh:183
PowerISA::BranchPCRel::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:62
PowerISA::BranchPCRel::BranchPCRel
BranchPCRel(const char *mnem, MachInst _machInst, OpClass __opClass)
Constructor.
Definition: branch.hh:77
PowerISA::BranchNonPCRelCond
Base class for conditional, non PC-relative branches.
Definition: branch.hh:208
PowerISA::BranchRegCond::BranchRegCond
BranchRegCond(const char *mnem, MachInst _machInst, OpClass __opClass)
Constructor.
Definition: branch.hh:243
PowerISA::BranchPCRel::disp
uint32_t disp
Displacement.
Definition: branch.hh:74
PowerISA::BranchPCRelCond::branchTarget
PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override
Definition: branch.cc:104
PowerISA::BranchPCRelCond::BranchPCRelCond
BranchPCRelCond(const char *mnem, MachInst _machInst, OpClass __opClass)
Constructor.
Definition: branch.hh:186
PowerISA::BranchNonPCRel
Base class for unconditional, non PC-relative branches.
Definition: branch.hh:99
PowerISA::MachInst
uint32_t MachInst
Definition: types.hh:39
PowerISA::BranchNonPCRelCond::BranchNonPCRelCond
BranchNonPCRelCond(const char *mnem, MachInst _machInst, OpClass __opClass)
Constructor.
Definition: branch.hh:216
PowerISA::BranchPCRelCond::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:110
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
PowerISA
Definition: decoder.cc:31
StaticInst::branchTarget
virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const
Return the target address for a PC-relative branch.
Definition: static_inst.cc:105
MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
PowerISA::BranchPCRel::branchTarget
PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override
Definition: branch.cc:56
PowerISA::BranchCond::bo
uint32_t bo
Fields needed for conditions.
Definition: branch.hh:134
StaticInst::ExtMachInst
TheISA::ExtMachInst ExtMachInst
Binary extended machine instruction type.
Definition: static_inst.hh:89
PowerISA::PCDependentDisassembly::PCDependentDisassembly
PCDependentDisassembly(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Constructor.
Definition: branch.hh:55
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
PowerISA::li
Bitfield< 25, 2 > li
Definition: types.hh:58
PowerISA::BranchPCRel
Base class for unconditional, PC-relative branches.
Definition: branch.hh:69
PowerISA::BranchNonPCRel::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:87
PowerISA::BranchRegCond::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:163
PowerISA::PCDependentDisassembly::cachedPC
Addr cachedPC
Cached program counter from last disassembly.
Definition: branch.hh:50
StaticInst::machInst
const ExtMachInst machInst
The binary machine instruction.
Definition: static_inst.hh:243
MipsISA::PCState
GenericISA::DelaySlotPCState< MachInst > PCState
Definition: types.hh:41
PowerISA::BranchCond::condOk
bool condOk(uint32_t cr) const
Definition: branch.hh:163
PowerISA::BranchPCRelCond
Base class for conditional, PC-relative branches.
Definition: branch.hh:178
PowerISA::BranchNonPCRel::targetAddr
uint32_t targetAddr
Target address.
Definition: branch.hh:104
PowerISA::PCDependentDisassembly::disassemble
const std::string & disassemble(Addr pc, const Loader::SymbolTable *symtab) const
Return string representation of disassembled instruction.
Definition: branch.cc:37
PowerISA::BranchCond
Base class for conditional branches.
Definition: branch.hh:129
PowerISA::BranchNonPCRelCond::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:137
PowerISA::PowerStaticInst
Definition: static_inst.hh:38
PowerISA::BranchNonPCRelCond::branchTarget
PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override
Definition: branch.cc:131
static_inst.hh
PowerISA::bd
Bitfield< 15, 2 > bd
Definition: types.hh:61
PowerISA::BranchNonPCRelCond::targetAddr
uint32_t targetAddr
Target address.
Definition: branch.hh:213
PowerISA::BranchRegCond
Base class for conditional, register-based branches.
Definition: branch.hh:238
PowerISA::PCDependentDisassembly
Base class for instructions whose disassembly is not purely a function of the machine instruction (i....
Definition: branch.hh:46

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