branch.hh

Go to the documentation of this file.

/* Copyright (c) 2007-2008 The Florida State University
 * Copyright (c) 2009 The University of Edinburgh
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __ARCH_POWER_INSTS_BRANCH_HH__
#define __ARCH_POWER_INSTS_BRANCH_HH__
 
#include "arch/power/insts/static_inst.hh"
 
namespace PowerISA
{
 
class PCDependentDisassembly : public PowerStaticInst
{
  protected:
    mutable Addr cachedPC;
    mutable const Loader::SymbolTable *cachedSymtab;
 
    PCDependentDisassembly(const char *mnem, ExtMachInst _machInst,
                           OpClass __opClass)
        : PowerStaticInst(mnem, _machInst, __opClass),
          cachedPC(0), cachedSymtab(0)
    {
    }
 
    const std::string &
    disassemble(Addr pc, const Loader::SymbolTable *symtab) const;
};
 
class BranchPCRel : public PCDependentDisassembly
{
  protected:
 
    uint32_t disp;
 
    BranchPCRel(const char *mnem, MachInst _machInst, OpClass __opClass)
        : PCDependentDisassembly(mnem, _machInst, __opClass),
          disp(machInst.li << 2)
    {
        // If bit 26 is 1 then sign extend
        if (disp & 0x2000000) {
            disp |= 0xfc000000;
        }
    }
 
    PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override;
 
    using StaticInst::branchTarget;
 
    std::string generateDisassembly(
            Addr pc, const Loader::SymbolTable *symtab) const override;
};
 
class BranchNonPCRel : public PCDependentDisassembly
{
  protected:
 
    uint32_t targetAddr;
 
    BranchNonPCRel(const char *mnem, MachInst _machInst, OpClass __opClass)
        : PCDependentDisassembly(mnem, _machInst, __opClass),
          targetAddr(machInst.li << 2)
    {
        // If bit 26 is 1 then sign extend
        if (targetAddr & 0x2000000) {
            targetAddr |= 0xfc000000;
        }
    }
 
    PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override;
 
    using StaticInst::branchTarget;
 
    std::string generateDisassembly(
            Addr pc, const Loader::SymbolTable *symtab) const override;
};
 
class BranchCond : public PCDependentDisassembly
{
  protected:
 
    uint32_t bo;
    uint32_t bi;
 
    BranchCond(const char *mnem, MachInst _machInst, OpClass __opClass)
        : PCDependentDisassembly(mnem, _machInst, __opClass),
          bo(machInst.bo),
          bi(machInst.bi)
    {
    }
 
    inline bool
    ctrOk(uint32_t& ctr) const
    {
        bool ctr_ok;
        if (bo & 4) {
            ctr_ok = true;
        } else {
            ctr--;
            if (ctr != 0) {
                ctr_ok = ((bo & 2) == 0);
            } else {
                ctr_ok = ((bo & 2) != 0);
            }
        }
        return ctr_ok;
    }
 
    inline bool
    condOk(uint32_t cr) const
    {
        bool cond_ok;
        if (bo & 16) {
            cond_ok = true;
        } else {
            cond_ok = (((cr >> (31 - bi)) & 1) == ((bo >> 3) & 1));
        }
        return cond_ok;
    }
};
 
class BranchPCRelCond : public BranchCond
{
  protected:
 
    uint32_t disp;
 
    BranchPCRelCond(const char *mnem, MachInst _machInst, OpClass __opClass)
        : BranchCond(mnem, _machInst, __opClass),
          disp(machInst.bd << 2)
    {
        // If bit 16 is 1 then sign extend
        if (disp & 0x8000) {
            disp |= 0xffff0000;
        }
    }
 
    PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override;
 
    using StaticInst::branchTarget;
 
    std::string generateDisassembly(
            Addr pc, const Loader::SymbolTable *symtab) const override;
};
 
class BranchNonPCRelCond : public BranchCond
{
  protected:
 
    uint32_t targetAddr;
 
    BranchNonPCRelCond(const char *mnem, MachInst _machInst, OpClass __opClass)
        : BranchCond(mnem, _machInst, __opClass),
          targetAddr(machInst.bd << 2)
    {
        // If bit 16 is 1 then sign extend
        if (targetAddr & 0x8000) {
            targetAddr |= 0xffff0000;
        }
    }
 
    PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override;
 
    using StaticInst::branchTarget;
 
    std::string generateDisassembly(
            Addr pc, const Loader::SymbolTable *symtab) const override;
};
 
class BranchRegCond : public BranchCond
{
  protected:
 
    BranchRegCond(const char *mnem, MachInst _machInst, OpClass __opClass)
        : BranchCond(mnem, _machInst, __opClass)
    {
    }
 
    PowerISA::PCState branchTarget(ThreadContext *tc) const override;
 
    using StaticInst::branchTarget;
 
    std::string generateDisassembly(
            Addr pc, const Loader::SymbolTable *symtab) const override;
};
 
} // namespace PowerISA
 
#endif //__ARCH_POWER_INSTS_BRANCH_HH__