gem5  v20.1.0.0
branch.cc
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28 
30 
31 #include "base/loader/symtab.hh"
32 #include "cpu/thread_context.hh"
33 
34 using namespace PowerISA;
35 
36 const std::string &
38  Addr pc, const Loader::SymbolTable *symtab) const
39 {
40  if (!cachedDisassembly ||
41  pc != cachedPC || symtab != cachedSymtab)
42  {
44  delete cachedDisassembly;
45 
47  new std::string(generateDisassembly(pc, symtab));
48  cachedPC = pc;
49  cachedSymtab = symtab;
50  }
51 
52  return *cachedDisassembly;
53 }
54 
57 {
58  return (uint32_t)(pc.pc() + disp);
59 }
60 
61 std::string
63  Addr pc, const Loader::SymbolTable *symtab) const
64 {
65  std::stringstream ss;
66 
67  ccprintf(ss, "%-10s ", mnemonic);
68 
69  Addr target = pc + disp;
70 
72  if (symtab && (it = symtab->find(target)) != symtab->end())
73  ss << it->name;
74  else
75  ccprintf(ss, "%#x", target);
76 
77  return ss.str();
78 }
79 
82 {
83  return targetAddr;
84 }
85 
86 std::string
88  Addr pc, const Loader::SymbolTable *symtab) const
89 {
90  std::stringstream ss;
91 
92  ccprintf(ss, "%-10s ", mnemonic);
93 
95  if (symtab && (it = symtab->find(targetAddr)) != symtab->end())
96  ss << it->name;
97  else
98  ccprintf(ss, "%#x", targetAddr);
99 
100  return ss.str();
101 }
102 
105 {
106  return (uint32_t)(pc.pc() + disp);
107 }
108 
109 std::string
111  Addr pc, const Loader::SymbolTable *symtab) const
112 {
113  std::stringstream ss;
114 
115  ccprintf(ss, "%-10s ", mnemonic);
116 
117  ss << bo << ", " << bi << ", ";
118 
119  Addr target = pc + disp;
120 
122  if (symtab && (it = symtab->find(target)) != symtab->end())
123  ss << it->name;
124  else
125  ccprintf(ss, "%#x", target);
126 
127  return ss.str();
128 }
129 
132 {
133  return targetAddr;
134 }
135 
136 std::string
138  Addr pc, const Loader::SymbolTable *symtab) const
139 {
140  std::stringstream ss;
141 
142  ccprintf(ss, "%-10s ", mnemonic);
143 
144  ss << bo << ", " << bi << ", ";
145 
147  if (symtab && (it = symtab->find(targetAddr)) != symtab->end())
148  ss << it->name;
149  else
150  ccprintf(ss, "%#x", targetAddr);
151 
152  return ss.str();
153 }
154 
157 {
158  uint32_t regVal = tc->readIntReg(_srcRegIdx[_numSrcRegs - 1].index());
159  return regVal & 0xfffffffc;
160 }
161 
162 std::string
164  Addr pc, const Loader::SymbolTable *symtab) const
165 {
166  std::stringstream ss;
167 
168  ccprintf(ss, "%-10s ", mnemonic);
169 
170  ss << bo << ", " << bi << ", ";
171 
172  return ss.str();
173 }
PowerISA::BranchCond::bi
uint32_t bi
Definition: branch.hh:135
PowerISA::BranchRegCond::branchTarget
PowerISA::PCState branchTarget(ThreadContext *tc) const override
Return the target address for an indirect branch (jump).
Definition: branch.cc:156
MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:44
PowerISA::BranchNonPCRel::branchTarget
PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override
Definition: branch.cc:81
PowerISA::PCDependentDisassembly::cachedSymtab
const Loader::SymbolTable * cachedSymtab
Cached symbol table pointer from last disassembly.
Definition: branch.hh:52
Loader::SymbolTable
Definition: symtab.hh:59
PowerISA::BranchPCRelCond::disp
uint32_t disp
Displacement.
Definition: branch.hh:183
PowerISA::BranchPCRel::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:62
PowerISA::BranchPCRel::disp
uint32_t disp
Displacement.
Definition: branch.hh:74
PowerISA::BranchPCRelCond::branchTarget
PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override
Definition: branch.cc:104
Loader::SymbolTable::find
const_iterator find(Addr address) const
Definition: symtab.hh:181
PowerISA::BranchPCRelCond::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:110
StaticInst::cachedDisassembly
std::string * cachedDisassembly
String representation of disassembly (lazily evaluated via disassemble()).
Definition: static_inst.hh:264
ArmISA::ss
Bitfield< 21 > ss
Definition: miscregs_types.hh:56
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
PowerISA
Definition: decoder.cc:31
MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
StaticInst::_srcRegIdx
RegId _srcRegIdx[MaxInstSrcRegs]
See srcRegIdx().
Definition: static_inst.hh:250
PowerISA::BranchPCRel::branchTarget
PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override
Definition: branch.cc:56
StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:258
PowerISA::BranchCond::bo
uint32_t bo
Fields needed for conditions.
Definition: branch.hh:134
branch.hh
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
PowerISA::BranchNonPCRel::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:87
PowerISA::BranchRegCond::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:163
PowerISA::PCDependentDisassembly::cachedPC
Addr cachedPC
Cached program counter from last disassembly.
Definition: branch.hh:50
Loader::SymbolTable::end
const_iterator end() const
Definition: symtab.hh:126
Loader::SymbolTable::const_iterator
SymbolVector::const_iterator const_iterator
Definition: symtab.hh:123
MipsISA::PCState
GenericISA::DelaySlotPCState< MachInst > PCState
Definition: types.hh:41
PowerISA::BranchNonPCRel::targetAddr
uint32_t targetAddr
Target address.
Definition: branch.hh:104
ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:127
StaticInst::_numSrcRegs
int8_t _numSrcRegs
See numSrcRegs().
Definition: static_inst.hh:105
PowerISA::PCDependentDisassembly::disassemble
const std::string & disassemble(Addr pc, const Loader::SymbolTable *symtab) const
Return string representation of disassembled instruction.
Definition: branch.cc:37
symtab.hh
PowerISA::BranchNonPCRelCond::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:137
ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
PowerISA::BranchNonPCRelCond::branchTarget
PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override
Definition: branch.cc:131
thread_context.hh
PowerISA::PowerStaticInst::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: static_inst.cc:57
PowerISA::BranchNonPCRelCond::targetAddr
uint32_t targetAddr
Target address.
Definition: branch.hh:213

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