gem5  v20.1.0.0
isa.cc
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28 
29 #include "arch/sparc/isa.hh"
30 
31 #include "arch/sparc/asi.hh"
32 #include "arch/sparc/decoder.hh"
33 #include "arch/sparc/interrupts.hh"
34 #include "base/bitfield.hh"
35 #include "base/trace.hh"
36 #include "cpu/base.hh"
37 #include "cpu/thread_context.hh"
38 #include "debug/MiscRegs.hh"
39 #include "debug/Timer.hh"
40 #include "params/SparcISA.hh"
41 
42 namespace SparcISA
43 {
44 
45 static PSTATE
47 {
48  PSTATE mask = 0;
49  mask.ie = 1;
50  mask.priv = 1;
51  mask.am = 1;
52  mask.pef = 1;
53  mask.mm = 3;
54  mask.tle = 1;
55  mask.cle = 1;
56  mask.pid1 = 1;
57  return mask;
58 }
59 
60 static const PSTATE PstateMask = buildPstateMask();
61 
63 {
64  clear();
65 }
66 
67 const SparcISAParams *
68 ISA::params() const
69 {
70  return dynamic_cast<const Params *>(_params);
71 }
72 
73 void
75 {
78  // Microcode registers.
79  for (int i = 0; i < NumMicroIntRegs; i++)
85 }
86 
87 void
89 {
90  assert(offset >= 0 && offset + NumWindowedRegs <= NumIntRegs);
91  RegIndex *mapChunk = intRegMap + offset;
92  for (int i = 0; i < NumWindowedRegs; i++)
93  mapChunk[i] = TotalGlobals +
95 }
96 
97 void
99 {
100  assert(offset >= 0 && offset + NumGlobalRegs <= NumIntRegs);
101  RegIndex *mapChunk = intRegMap + offset;
102  mapChunk[0] = 0;
103  for (int i = 1; i < NumGlobalRegs; i++)
104  mapChunk[i] = i + gl * NumGlobalRegs;
105 }
106 
107 void
109 {
110  cwp = 0;
111  gl = 0;
112  reloadRegMap();
113 
114  // y = 0;
115  // ccr = 0;
116  asi = 0;
117  tick = ULL(1) << 63;
118  fprs = 0;
119  gsr = 0;
120  softint = 0;
121  tick_cmpr = 0;
122  stick = 0;
123  stick_cmpr = 0;
124  memset(tpc, 0, sizeof(tpc));
125  memset(tnpc, 0, sizeof(tnpc));
126  memset(tstate, 0, sizeof(tstate));
127  memset(tt, 0, sizeof(tt));
128  tba = 0;
129  pstate = 0;
130  tl = 0;
131  pil = 0;
132  // cansave = 0;
133  // canrestore = 0;
134  // cleanwin = 0;
135  // otherwin = 0;
136  // wstate = 0;
137  // In a T1, bit 11 is apparently always 1
138  hpstate = 0;
139  hpstate.id = 1;
140  memset(htstate, 0, sizeof(htstate));
141  hintp = 0;
142  htba = 0;
143  hstick_cmpr = 0;
144  // This is set this way in Legion for some reason
145  strandStatusReg = 0x50000;
146  fsr = 0;
147 
148  priContext = 0;
149  secContext = 0;
150  partId = 0;
151  lsuCtrlReg = 0;
152 
153  memset(scratchPad, 0, sizeof(scratchPad));
154 
155  cpu_mondo_head = 0;
156  cpu_mondo_tail = 0;
157  dev_mondo_head = 0;
158  dev_mondo_tail = 0;
159  res_error_head = 0;
160  res_error_tail = 0;
161  nres_error_head = 0;
162  nres_error_tail = 0;
163 
164  // If one of these events is active, it's not obvious to me how to get
165  // rid of it cleanly. For now we'll just assert that they're not.
166  if (tickCompare != NULL && sTickCompare != NULL && hSTickCompare != NULL)
167  panic("Tick comparison event active when clearing the ISA object.\n");
168 }
169 
170 RegVal
171 ISA::readMiscRegNoEffect(int miscReg) const
172 {
173 
174  // The three miscRegs are moved up from the switch statement
175  // due to more frequent calls.
176 
177  if (miscReg == MISCREG_GL)
178  return gl;
179  if (miscReg == MISCREG_CWP)
180  return cwp;
181  if (miscReg == MISCREG_TLB_DATA) {
182  /* Package up all the data for the tlb:
183  * 6666555555555544444444443333333333222222222211111111110000000000
184  * 3210987654321098765432109876543210987654321098765432109876543210
185  * secContext | priContext | |tl|partid| |||||^hpriv
186  * ||||^red
187  * |||^priv
188  * ||^am
189  * |^lsuim
190  * ^lsudm
191  */
192  return (uint64_t)hpstate.hpriv |
193  (uint64_t)hpstate.red << 1 |
194  (uint64_t)pstate.priv << 2 |
195  (uint64_t)pstate.am << 3 |
196  bits((uint64_t)lsuCtrlReg,3,2) << 4 |
197  bits((uint64_t)partId,7,0) << 8 |
198  bits((uint64_t)tl,2,0) << 16 |
199  (uint64_t)priContext << 32 |
200  (uint64_t)secContext << 48;
201  }
202 
203  switch (miscReg) {
204  // case MISCREG_TLB_DATA:
205  // [original contents see above]
206  // case MISCREG_Y:
207  // return y;
208  // case MISCREG_CCR:
209  // return ccr;
210  case MISCREG_ASI:
211  return asi;
212  case MISCREG_FPRS:
213  return fprs;
214  case MISCREG_TICK:
215  return tick;
216  case MISCREG_PCR:
217  panic("PCR not implemented\n");
218  case MISCREG_PIC:
219  panic("PIC not implemented\n");
220  case MISCREG_GSR:
221  return gsr;
222  case MISCREG_SOFTINT:
223  return softint;
224  case MISCREG_TICK_CMPR:
225  return tick_cmpr;
226  case MISCREG_STICK:
227  return stick;
228  case MISCREG_STICK_CMPR:
229  return stick_cmpr;
230 
232  case MISCREG_TPC:
233  return tpc[tl-1];
234  case MISCREG_TNPC:
235  return tnpc[tl-1];
236  case MISCREG_TSTATE:
237  return tstate[tl-1];
238  case MISCREG_TT:
239  return tt[tl-1];
240  case MISCREG_PRIVTICK:
241  panic("Priviliged access to tick registers not implemented\n");
242  case MISCREG_TBA:
243  return tba;
244  case MISCREG_PSTATE:
245  return (RegVal)pstate;
246  case MISCREG_TL:
247  return tl;
248  case MISCREG_PIL:
249  return pil;
250  // CWP, GL moved
251  // case MISCREG_CWP:
252  // return cwp;
253  // case MISCREG_CANSAVE:
254  // return cansave;
255  // case MISCREG_CANRESTORE:
256  // return canrestore;
257  // case MISCREG_CLEANWIN:
258  // return cleanwin;
259  // case MISCREG_OTHERWIN:
260  // return otherwin;
261  // case MISCREG_WSTATE:
262  // return wstate;
263  // case MISCREG_GL:
264  // return gl;
265 
267  case MISCREG_HPSTATE:
268  return (RegVal)hpstate;
269  case MISCREG_HTSTATE:
270  return htstate[tl-1];
271  case MISCREG_HINTP:
272  return hintp;
273  case MISCREG_HTBA:
274  return htba;
276  return strandStatusReg;
277  case MISCREG_HSTICK_CMPR:
278  return hstick_cmpr;
279 
281  case MISCREG_FSR:
282  DPRINTF(MiscRegs, "FSR read as: %#x\n", fsr);
283  return fsr;
284 
286  return priContext;
288  return secContext;
289  case MISCREG_MMU_PART_ID:
290  return partId;
292  return lsuCtrlReg;
293 
295  return scratchPad[0];
297  return scratchPad[1];
299  return scratchPad[2];
301  return scratchPad[3];
303  return scratchPad[4];
305  return scratchPad[5];
307  return scratchPad[6];
309  return scratchPad[7];
311  return cpu_mondo_head;
313  return cpu_mondo_tail;
315  return dev_mondo_head;
317  return dev_mondo_tail;
319  return res_error_head;
321  return res_error_tail;
323  return nres_error_head;
325  return nres_error_tail;
326  default:
327  panic("Miscellaneous register %d not implemented\n", miscReg);
328  }
329 }
330 
331 RegVal
332 ISA::readMiscReg(int miscReg)
333 {
334  switch (miscReg) {
335  // tick and stick are aliased to each other in niagra
336  // well store the tick data in stick and the interrupt bit in tick
337  case MISCREG_STICK:
338  case MISCREG_TICK:
339  case MISCREG_PRIVTICK:
340  // I'm not sure why legion ignores the lowest two bits, but we'll go
341  // with it
342  // change from curCycle() to instCount() until we're done with legion
343  DPRINTF(Timer, "Instruction Count when TICK read: %#X stick=%#X\n",
344  tc->getCpuPtr()->instCount(), stick);
345  return mbits(tc->getCpuPtr()->instCount() + (int64_t)stick,62,2) |
346  mbits(tick,63,63);
347  case MISCREG_FPRS:
348  // in legion if fp is enabled du and dl are set
349  return fprs | 0x3;
350  case MISCREG_PCR:
351  case MISCREG_PIC:
352  panic("Performance Instrumentation not impl\n");
353  case MISCREG_SOFTINT_CLR:
354  case MISCREG_SOFTINT_SET:
355  panic("Can read from softint clr/set\n");
356  case MISCREG_SOFTINT:
357  case MISCREG_TICK_CMPR:
358  case MISCREG_STICK_CMPR:
359  case MISCREG_HINTP:
360  case MISCREG_HTSTATE:
361  case MISCREG_HTBA:
362  case MISCREG_HVER:
364  case MISCREG_HSTICK_CMPR:
373  case MISCREG_HPSTATE:
374  return readFSReg(miscReg);
375  }
376  return readMiscRegNoEffect(miscReg);
377 }
378 
379 void
381 {
382  switch (miscReg) {
383 // case MISCREG_Y:
384 // y = val;
385 // break;
386 // case MISCREG_CCR:
387 // ccr = val;
388 // break;
389  case MISCREG_ASI:
390  asi = val;
391  break;
392  case MISCREG_FPRS:
393  fprs = val;
394  break;
395  case MISCREG_TICK:
396  tick = val;
397  break;
398  case MISCREG_PCR:
399  panic("PCR not implemented\n");
400  case MISCREG_PIC:
401  panic("PIC not implemented\n");
402  case MISCREG_GSR:
403  gsr = val;
404  break;
405  case MISCREG_SOFTINT:
406  softint = val;
407  break;
408  case MISCREG_TICK_CMPR:
409  tick_cmpr = val;
410  break;
411  case MISCREG_STICK:
412  stick = val;
413  break;
414  case MISCREG_STICK_CMPR:
415  stick_cmpr = val;
416  break;
417 
419  case MISCREG_TPC:
420  tpc[tl-1] = val;
421  break;
422  case MISCREG_TNPC:
423  tnpc[tl-1] = val;
424  break;
425  case MISCREG_TSTATE:
426  tstate[tl-1] = val;
427  break;
428  case MISCREG_TT:
429  tt[tl-1] = val;
430  break;
431  case MISCREG_PRIVTICK:
432  panic("Priviliged access to tick regesiters not implemented\n");
433  case MISCREG_TBA:
434  // clear lower 7 bits on writes.
435  tba = val & ULL(~0x7FFF);
436  break;
437  case MISCREG_PSTATE:
438  pstate = (val & PstateMask);
439  break;
440  case MISCREG_TL:
441  tl = val;
442  break;
443  case MISCREG_PIL:
444  pil = val;
445  break;
446  case MISCREG_CWP:
447  cwp = val;
448  break;
449 // case MISCREG_CANSAVE:
450 // cansave = val;
451 // break;
452 // case MISCREG_CANRESTORE:
453 // canrestore = val;
454 // break;
455 // case MISCREG_CLEANWIN:
456 // cleanwin = val;
457 // break;
458 // case MISCREG_OTHERWIN:
459 // otherwin = val;
460 // break;
461 // case MISCREG_WSTATE:
462 // wstate = val;
463 // break;
464  case MISCREG_GL:
465  gl = val;
466  break;
467 
469  case MISCREG_HPSTATE:
470  hpstate = val;
471  break;
472  case MISCREG_HTSTATE:
473  htstate[tl-1] = val;
474  break;
475  case MISCREG_HINTP:
476  hintp = val;
477  break;
478  case MISCREG_HTBA:
479  htba = val;
480  break;
483  break;
484  case MISCREG_HSTICK_CMPR:
485  hstick_cmpr = val;
486  break;
487 
489  case MISCREG_FSR:
490  fsr = val;
491  DPRINTF(MiscRegs, "FSR written with: %#x\n", fsr);
492  break;
493 
495  priContext = val;
496  break;
498  secContext = val;
499  break;
500  case MISCREG_MMU_PART_ID:
501  partId = val;
502  break;
504  lsuCtrlReg = val;
505  break;
506 
508  scratchPad[0] = val;
509  break;
511  scratchPad[1] = val;
512  break;
514  scratchPad[2] = val;
515  break;
517  scratchPad[3] = val;
518  break;
520  scratchPad[4] = val;
521  break;
523  scratchPad[5] = val;
524  break;
526  scratchPad[6] = val;
527  break;
529  scratchPad[7] = val;
530  break;
533  break;
536  break;
539  break;
542  break;
545  break;
548  break;
551  break;
554  break;
555  default:
556  panic("Miscellaneous register %d not implemented\n", miscReg);
557  }
558 }
559 
560 void
562 {
563  RegVal new_val = val;
564 
565  switch (miscReg) {
566  case MISCREG_ASI:
567  tc->getDecoderPtr()->setContext(val);
568  break;
569  case MISCREG_STICK:
570  case MISCREG_TICK:
571  // stick and tick are same thing on niagra
572  // use stick for offset and tick for holding intrrupt bit
573  stick = mbits(val,62,0) - tc->getCpuPtr()->instCount();
574  tick = mbits(val,63,63);
575  DPRINTF(Timer, "Writing TICK=%#X\n", val);
576  break;
577  case MISCREG_FPRS:
578  // Configure the fpu based on the fprs
579  break;
580  case MISCREG_PCR:
581  // Set up performance counting based on pcr value
582  break;
583  case MISCREG_PSTATE:
584  pstate = val & PstateMask;
585  return;
586  case MISCREG_TL:
587  {
588  tl = val;
589  if (hpstate.tlz && tl == 0 && !hpstate.hpriv)
591  else
593  return;
594  }
595  case MISCREG_CWP:
596  new_val = val >= NWindows ? NWindows - 1 : val;
597  if (val >= NWindows)
598  new_val = NWindows - 1;
599 
601  installWindow(new_val - 1, NextWindowOffset);
602  installWindow(new_val + 1, PreviousWindowOffset);
603  break;
604  case MISCREG_GL:
608  break;
609  case MISCREG_PIL:
610  case MISCREG_SOFTINT:
611  case MISCREG_SOFTINT_SET:
612  case MISCREG_SOFTINT_CLR:
613  case MISCREG_TICK_CMPR:
614  case MISCREG_STICK_CMPR:
615  case MISCREG_HINTP:
616  case MISCREG_HTSTATE:
617  case MISCREG_HTBA:
618  case MISCREG_HVER:
620  case MISCREG_HSTICK_CMPR:
629  case MISCREG_HPSTATE:
630  setFSReg(miscReg, val);
631  return;
632  }
633  setMiscRegNoEffect(miscReg, new_val);
634 }
635 
636 void
638 {
677 
678  Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
680  tick_cmp = tickCompare->when();
682  stick_cmp = sTickCompare->when();
684  hstick_cmp = hSTickCompare->when();
685 
686  SERIALIZE_SCALAR(tick_cmp);
687  SERIALIZE_SCALAR(stick_cmp);
688  SERIALIZE_SCALAR(hstick_cmp);
689 }
690 
691 void
693 {
707  {
708  uint16_t pstate;
710  this->pstate = pstate;
711  }
716  reloadRegMap();
717  {
718  uint64_t hpstate;
720  this->hpstate = hpstate;
721  }
741 
742  Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
743  UNSERIALIZE_SCALAR(tick_cmp);
744  UNSERIALIZE_SCALAR(stick_cmp);
745  UNSERIALIZE_SCALAR(hstick_cmp);
746 
747  if (tick_cmp) {
748  tickCompare = new TickCompareEvent(this);
749  schedule(tickCompare, tick_cmp);
750  }
751  if (stick_cmp) {
752  sTickCompare = new STickCompareEvent(this);
753  schedule(sTickCompare, stick_cmp);
754  }
755  if (hstick_cmp) {
756  hSTickCompare = new HSTickCompareEvent(this);
757  schedule(hSTickCompare, hstick_cmp);
758  }
759 }
760 
761 }
762 
764 SparcISAParams::create()
765 {
766  return new SparcISA::ISA(this);
767 }
SparcISA::ISA::reloadRegMap
void reloadRegMap()
Definition: isa.cc:74
SparcISA::MISCREG_PSTATE
@ MISCREG_PSTATE
Definition: miscregs.hh:62
Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:460
SparcISA::ISA::nres_error_tail
uint64_t nres_error_tail
Definition: isa.hh:113
SparcISA::MISCREG_TSTATE
@ MISCREG_TSTATE
Definition: miscregs.hh:58
SparcISA::MISCREG_PIC
@ MISCREG_PIC
Definition: miscregs.hh:46
SparcISA::MISCREG_QUEUE_CPU_MONDO_TAIL
@ MISCREG_QUEUE_CPU_MONDO_TAIL
Definition: miscregs.hh:103
SparcISA::ISA::tstate
uint64_t tstate[MaxTL]
Definition: isa.hh:70
SparcISA::NumIntRegs
const int NumIntRegs
Definition: registers.hh:101
SparcISA::ISA::secContext
uint16_t secContext
Definition: isa.hh:100
SparcISA::MISCREG_TICK_CMPR
@ MISCREG_TICK_CMPR
Definition: miscregs.hh:51
SparcISA::ISA::NumWindowedRegs
static const int NumWindowedRegs
Definition: isa.hh:139
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:797
SparcISA::MISCREG_PIL
@ MISCREG_PIL
Definition: miscregs.hh:64
SparcISA::ISA::sTickCompare
STickCompareEvent * sTickCompare
Definition: isa.hh:133
SparcISA::MISCREG_SCRATCHPAD_R3
@ MISCREG_SCRATCHPAD_R3
Definition: miscregs.hh:95
SparcISA::MISCREG_HINTP
@ MISCREG_HINTP
Definition: miscregs.hh:76
SparcISA::ISA::cwp
uint8_t cwp
Definition: isa.hh:78
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
SparcISA::MISCREG_SCRATCHPAD_R5
@ MISCREG_SCRATCHPAD_R5
Definition: miscregs.hh:97
SparcISA::MISCREG_HTSTATE
@ MISCREG_HTSTATE
Definition: miscregs.hh:75
SparcISA::MISCREG_SCRATCHPAD_R1
@ MISCREG_SCRATCHPAD_R1
Definition: miscregs.hh:93
SparcISA::ISA::STickCompareEvent
EventWrapper< ISA, &ISA::processSTickCompare > STickCompareEvent
Definition: isa.hh:132
SparcISA::PstateMask
static const PSTATE PstateMask
Definition: isa.cc:60
SparcISA::ISA::tt
uint16_t tt[MaxTL]
Definition: isa.hh:71
SparcISA::ISA::cpu_mondo_head
uint64_t cpu_mondo_head
Definition: isa.hh:106
SparcISA::ISA::PreviousGlobalsOffset
@ PreviousGlobalsOffset
Definition: isa.hh:152
Tick
uint64_t Tick
Tick count type.
Definition: types.hh:63
SparcISA::MISCREG_TLB_DATA
@ MISCREG_TLB_DATA
Definition: miscregs.hh:112
SparcISA::MISCREG_SOFTINT
@ MISCREG_SOFTINT
Definition: miscregs.hh:50
SparcISA::ISA::hintp
uint64_t hintp
Definition: isa.hh:89
BaseCPU::postInterrupt
void postInterrupt(ThreadID tid, int int_num, int index)
Definition: base.cc:189
SparcISA::MISCREG_FSR
@ MISCREG_FSR
Floating Point Status Register.
Definition: miscregs.hh:83
SparcISA::MISCREG_PCR
@ MISCREG_PCR
Definition: miscregs.hh:45
SparcISA::ISA::params
const Params * params() const
Definition: isa.cc:68
SparcISA::MISCREG_QUEUE_DEV_MONDO_HEAD
@ MISCREG_QUEUE_DEV_MONDO_HEAD
Definition: miscregs.hh:104
SparcISA::NumMicroIntRegs
@ NumMicroIntRegs
Definition: registers.hh:88
SparcISA::MISCREG_TPC
@ MISCREG_TPC
Privilged Registers.
Definition: miscregs.hh:56
mbits
T mbits(T val, int first, int last)
Mask off the given bits in place like bits() but without shifting.
Definition: bitfield.hh:104
SparcISA::NWindows
const int NWindows
Definition: sparc_traits.hh:41
SparcISA::ISA::fprs
uint8_t fprs
Definition: isa.hh:57
SparcISA::MISCREG_GSR
@ MISCREG_GSR
Definition: miscregs.hh:47
Event::when
Tick when() const
Get the time that the event is scheduled.
Definition: eventq.hh:503
SparcISA::MISCREG_SCRATCHPAD_R6
@ MISCREG_SCRATCHPAD_R6
Definition: miscregs.hh:98
SparcISA::ISA::setFSReg
void setFSReg(int miscReg, RegVal val)
Definition: ua2005.cc:90
SparcISA::ISA::strandStatusReg
uint64_t strandStatusReg
Definition: isa.hh:93
SparcISA::MISCREG_QUEUE_DEV_MONDO_TAIL
@ MISCREG_QUEUE_DEV_MONDO_TAIL
Definition: miscregs.hh:105
SparcISA::MISCREG_PRIVTICK
@ MISCREG_PRIVTICK
Definition: miscregs.hh:60
SparcISA::ISA::MicroIntOffset
@ MicroIntOffset
Definition: isa.hh:149
SparcISA::ISA::CurrentWindowOffset
@ CurrentWindowOffset
Definition: isa.hh:148
SparcISA::MISCREG_SOFTINT_CLR
@ MISCREG_SOFTINT_CLR
Definition: miscregs.hh:49
SparcISA::ISA::tpc
uint64_t tpc[MaxTL]
Definition: isa.hh:66
SparcISA::ISA::hpstate
HPSTATE hpstate
Hyperprivileged Registers.
Definition: isa.hh:87
SparcISA::ISA::asi
uint8_t asi
Definition: isa.hh:55
SparcISA::ISA::NextWindowOffset
@ NextWindowOffset
Definition: isa.hh:151
SparcISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int miscReg) const
Definition: isa.cc:171
SparcISA
Definition: asi.cc:31
SparcISA::ISA::stick_cmpr
uint64_t stick_cmpr
Definition: isa.hh:62
SparcISA::IT_TRAP_LEVEL_ZERO
@ IT_TRAP_LEVEL_ZERO
Definition: interrupts.hh:46
SparcISA::MISCREG_GL
@ MISCREG_GL
Definition: miscregs.hh:71
SparcISA::ISA::installGlobals
void installGlobals(int gl, int offset)
Definition: isa.cc:98
SparcISA::ISA::fsr
uint64_t fsr
Floating point misc registers.
Definition: isa.hh:96
SparcISA::MISCREG_TT
@ MISCREG_TT
Definition: miscregs.hh:59
SparcISA::MISCREG_TICK
@ MISCREG_TICK
Definition: miscregs.hh:43
SparcISA::ISA::res_error_head
uint64_t res_error_head
Definition: isa.hh:110
cp
Definition: cprintf.cc:40
EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1005
SparcISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int miscReg, RegVal val)
Definition: isa.cc:380
SparcISA::ISA::readMiscReg
RegVal readMiscReg(int miscReg)
Definition: isa.cc:332
SparcISA::buildPstateMask
static PSTATE buildPstateMask()
Definition: isa.cc:46
SparcISA::ISA::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: isa.cc:637
SparcISA::MISCREG_QUEUE_NRES_ERROR_TAIL
@ MISCREG_QUEUE_NRES_ERROR_TAIL
Definition: miscregs.hh:109
bitfield.hh
SparcISA::ISA::CurrentGlobalsOffset
@ CurrentGlobalsOffset
Definition: isa.hh:147
SparcISA::MISCREG_TL
@ MISCREG_TL
Definition: miscregs.hh:63
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
BaseISA::tc
ThreadContext * tc
Definition: isa.hh:52
asi.hh
SparcISA::ISA::installWindow
void installWindow(int cwp, int offset)
Definition: isa.cc:88
SparcISA::MISCREG_SOFTINT_SET
@ MISCREG_SOFTINT_SET
Definition: miscregs.hh:48
SparcISA::ISA::gsr
uint64_t gsr
Definition: isa.hh:58
SparcISA::ISA::priContext
uint16_t priContext
MMU Internal Registers.
Definition: isa.hh:99
SparcISA::ISA::TotalWindowed
static const int TotalWindowed
Definition: isa.hh:144
SparcISA::ISA::partId
uint16_t partId
Definition: isa.hh:101
SparcISA::ISA::dev_mondo_head
uint64_t dev_mondo_head
Definition: isa.hh:108
SparcISA::ISA::res_error_tail
uint64_t res_error_tail
Definition: isa.hh:111
BaseCPU::clearInterrupt
void clearInterrupt(ThreadID tid, int int_num, int index)
Definition: base.hh:234
SparcISA::MISCREG_QUEUE_CPU_MONDO_HEAD
@ MISCREG_QUEUE_CPU_MONDO_HEAD
Definition: miscregs.hh:102
SparcISA::ISA::cpu_mondo_tail
uint64_t cpu_mondo_tail
Definition: isa.hh:107
SparcISA::ISA::ISA
ISA(Params *p)
Definition: isa.cc:62
SERIALIZE_ARRAY
#define SERIALIZE_ARRAY(member, size)
Definition: serialize.hh:832
SparcISA::MISCREG_QUEUE_RES_ERROR_HEAD
@ MISCREG_QUEUE_RES_ERROR_HEAD
Definition: miscregs.hh:106
SparcISA::ISA::tick_cmpr
uint64_t tick_cmpr
Definition: isa.hh:60
SparcISA::ISA::pil
uint8_t pil
Definition: isa.hh:77
SparcISA::ISA::tick
uint64_t tick
Definition: isa.hh:56
SparcISA::MISCREG_MMU_LSU_CTRL
@ MISCREG_MMU_LSU_CTRL
Definition: miscregs.hh:89
SparcISA::MISCREG_STRAND_STS_REG
@ MISCREG_STRAND_STS_REG
Definition: miscregs.hh:79
X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
SparcISA::MISCREG_STICK_CMPR
@ MISCREG_STICK_CMPR
Definition: miscregs.hh:53
SparcISA::ISA::setMiscReg
void setMiscReg(int miscReg, RegVal val)
Definition: isa.cc:561
SparcISA::ISA::TotalGlobals
static const int TotalGlobals
Definition: isa.hh:142
SparcISA::ISA::softint
uint64_t softint
Definition: isa.hh:59
SparcISA::MISCREG_HSTICK_CMPR
@ MISCREG_HSTICK_CMPR
Definition: miscregs.hh:80
SparcISA::ISA::scratchPad
uint64_t scratchPad[8]
Definition: isa.hh:104
SparcISA::ISA::NextGlobalsOffset
@ NextGlobalsOffset
Definition: isa.hh:150
SparcISA::ISA::htba
uint64_t htba
Definition: isa.hh:90
SparcISA::MISCREG_MMU_PART_ID
@ MISCREG_MMU_PART_ID
Definition: miscregs.hh:88
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:790
SparcISA::ISA::htstate
uint64_t htstate[MaxTL]
Definition: isa.hh:88
SparcISA::ISA::RegsPerWindow
static const int RegsPerWindow
Definition: isa.hh:143
SparcISA::MISCREG_SCRATCHPAD_R0
@ MISCREG_SCRATCHPAD_R0
Scratchpad regiscers.
Definition: miscregs.hh:92
SparcISA::ISA::clear
void clear()
Definition: isa.cc:108
SparcISA::ISA::lsuCtrlReg
uint64_t lsuCtrlReg
Definition: isa.hh:102
SparcISA::MISCREG_HPSTATE
@ MISCREG_HPSTATE
Hyper privileged registers.
Definition: miscregs.hh:74
SparcISA::MISCREG_STICK
@ MISCREG_STICK
Definition: miscregs.hh:52
SparcISA::MISCREG_ASI
@ MISCREG_ASI
Ancillary State Registers.
Definition: miscregs.hh:42
base.hh
UNSERIALIZE_ARRAY
#define UNSERIALIZE_ARRAY(member, size)
Definition: serialize.hh:840
RegIndex
uint16_t RegIndex
Definition: types.hh:52
SparcISA::MISCREG_SCRATCHPAD_R7
@ MISCREG_SCRATCHPAD_R7
Definition: miscregs.hh:99
SimObject::_params
const SimObjectParams * _params
Cached copy of the object parameters.
Definition: sim_object.hh:110
SparcISA::MISCREG_QUEUE_NRES_ERROR_HEAD
@ MISCREG_QUEUE_NRES_ERROR_HEAD
Definition: miscregs.hh:108
decoder.hh
SparcISA::MISCREG_HTBA
@ MISCREG_HTBA
Definition: miscregs.hh:77
SparcISA::ISA::tl
uint8_t tl
Definition: isa.hh:76
interrupts.hh
SparcISA::MISCREG_QUEUE_RES_ERROR_TAIL
@ MISCREG_QUEUE_RES_ERROR_TAIL
Definition: miscregs.hh:107
SparcISA::ISA::tnpc
uint64_t tnpc[MaxTL]
Definition: isa.hh:68
CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:63
ThreadContext::getDecoderPtr
virtual TheISA::Decoder * getDecoderPtr()=0
SparcISA::ISA::hSTickCompare
HSTickCompareEvent * hSTickCompare
Definition: isa.hh:136
SparcISA::ISA::hstick_cmpr
uint64_t hstick_cmpr
Definition: isa.hh:91
SparcISA::ISA::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: isa.cc:692
trace.hh
SparcISA::ISA
Definition: isa.hh:48
SparcISA::ISA::tickCompare
TickCompareEvent * tickCompare
Definition: isa.hh:130
SparcISA::ISA::nres_error_head
uint64_t nres_error_head
Definition: isa.hh:112
SparcISA::MISCREG_SCRATCHPAD_R4
@ MISCREG_SCRATCHPAD_R4
Definition: miscregs.hh:96
SparcISA::ISA::Params
SparcISAParams Params
Definition: isa.hh:219
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
SparcISA::MISCREG_MMU_P_CONTEXT
@ MISCREG_MMU_P_CONTEXT
MMU Internal Registers.
Definition: miscregs.hh:86
BaseCPU::instCount
Tick instCount()
Definition: base.hh:212
SparcISA::ISA::stick
uint64_t stick
Definition: isa.hh:61
SparcISA::MISCREG_TNPC
@ MISCREG_TNPC
Definition: miscregs.hh:57
SparcISA::ISA::PreviousWindowOffset
@ PreviousWindowOffset
Definition: isa.hh:153
CheckpointIn
Definition: serialize.hh:67
SparcISA::ISA::TickCompareEvent
EventWrapper< ISA, &ISA::processTickCompare > TickCompareEvent
Definition: isa.hh:129
SparcISA::ISA::readFSReg
RegVal readFSReg(int miscReg)
Definition: ua2005.cc:246
SparcISA::ISA::HSTickCompareEvent
EventWrapper< ISA, &ISA::processHSTickCompare > HSTickCompareEvent
Definition: isa.hh:135
ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
SparcISA::ISA::dev_mondo_tail
uint64_t dev_mondo_tail
Definition: isa.hh:109
SparcISA::ISA::pstate
PSTATE pstate
Definition: isa.hh:75
BaseISA
Definition: isa.hh:47
SparcISA::MISCREG_SCRATCHPAD_R2
@ MISCREG_SCRATCHPAD_R2
Definition: miscregs.hh:94
isa.hh
SparcISA::MISCREG_HVER
@ MISCREG_HVER
Definition: miscregs.hh:78
thread_context.hh
SparcISA::MISCREG_MMU_S_CONTEXT
@ MISCREG_MMU_S_CONTEXT
Definition: miscregs.hh:87
ULL
#define ULL(N)
uint64_t constant
Definition: types.hh:50
SparcISA::ISA::intRegMap
RegIndex intRegMap[TotalInstIntRegs]
Definition: isa.hh:157
RegVal
uint64_t RegVal
Definition: types.hh:168
SparcISA::ISA::gl
uint8_t gl
Definition: isa.hh:84
SparcISA::MISCREG_FPRS
@ MISCREG_FPRS
Definition: miscregs.hh:44
ArmISA::mask
Bitfield< 28, 24 > mask
Definition: miscregs_types.hh:711
SparcISA::ISA::tba
uint64_t tba
Definition: isa.hh:73
SparcISA::MISCREG_CWP
@ MISCREG_CWP
Definition: miscregs.hh:65
SparcISA::MISCREG_TBA
@ MISCREG_TBA
Definition: miscregs.hh:61
SparcISA::MaxTL
const int MaxTL
Definition: sparc_traits.hh:36
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171
SparcISA::ISA::NumGlobalRegs
static const int NumGlobalRegs
Definition: isa.hh:138
ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:153
bits
T bits(T val, int first, int last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:75

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