gem5  v20.1.0.0
ufs_device.cc
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37 
70 #include "dev/arm/ufs_device.hh"
71 
75 UFSHostDevice::UFSSCSIDevice::UFSSCSIDevice(const UFSHostDeviceParams* p,
76  uint32_t lun_id, const Callback &transfer_cb,
77  const Callback &read_cb):
78  SimObject(p),
79  flashDisk(p->image[lun_id]),
80  flashDevice(p->internalflash[lun_id]),
81  blkSize(p->img_blk_size),
82  lunAvail(p->image.size()),
83  diskSize(flashDisk->size()),
84  capacityLower((diskSize - 1) & 0xffffffff),
85  capacityUpper((diskSize - SectorSize) >> 32),
86  lunID(lun_id),
87  transferCompleted(false),
88  readCompleted(false),
89  totalRead(0),
90  totalWrite(0),
91  amountOfWriteTransfers(0),
92  amountOfReadTransfers(0)
93 {
99  signalDone = transfer_cb;
100  memReadCallback = [this]() { readCallback(); };
101  deviceReadCallback = read_cb;
102  memWriteCallback = [this]() { SSDWriteDone(); };
103 
108  uint32_t temp_id = ((lun_id | 0x30) << 24) | 0x3A4449;
109  lunInfo.dWord0 = 0x02060000; //data
110  lunInfo.dWord1 = 0x0200001F;
111  lunInfo.vendor0 = 0x484D5241; //ARMH (HMRA)
112  lunInfo.vendor1 = 0x424D4143; //CAMB (BMAC)
113  lunInfo.product0 = 0x356D6567; //gem5 (5meg)
114  lunInfo.product1 = 0x4D534655; //UFSM (MSFU)
115  lunInfo.product2 = 0x4C45444F; //ODEL (LEDO)
116  lunInfo.product3 = temp_id; // ID:"lun_id" ("lun_id":DI)
117  lunInfo.productRevision = 0x01000000; //0x01
118 
119  DPRINTF(UFSHostDevice, "Logic unit %d assumes that %d logic units are"
120  " present in the system\n", lunID, lunAvail);
121  DPRINTF(UFSHostDevice,"The disksize of lun: %d should be %d blocks\n",
122  lunID, diskSize);
123  flashDevice->initializeMemory(diskSize, SectorSize);
124 }
125 
126 
132 const unsigned int UFSHostDevice::UFSSCSIDevice::controlPage[3] =
133  {0x01400A0A, 0x00000000,
134  0x0000FFFF};
135 const unsigned int UFSHostDevice::UFSSCSIDevice::recoveryPage[3] =
136  {0x03800A01, 0x00000000,
137  0xFFFF0003};
138 const unsigned int UFSHostDevice::UFSSCSIDevice::cachingPage[5] =
139  {0x00011208, 0x00000000,
140  0x00000000, 0x00000020,
141  0x00000000};
142 
143 UFSHostDevice::UFSSCSIDevice::~UFSSCSIDevice() {}
144 
156 struct UFSHostDevice::SCSIReply
157 UFSHostDevice::UFSSCSIDevice::SCSICMDHandle(uint32_t* SCSI_msg)
158 {
159  struct SCSIReply scsi_out;
160  scsi_out.reset();
161 
166  scsi_out.message.header.dWord0 = UPIUHeaderDataIndWord0 |
167  lunID << 16;
168  scsi_out.message.header.dWord1 = UPIUHeaderDataIndWord1;
169  scsi_out.message.header.dWord2 = UPIUHeaderDataIndWord2;
170  statusCheck(SCSIGood, scsi_out.senseCode);
171  scsi_out.senseSize = scsi_out.senseCode[0];
172  scsi_out.LUN = lunID;
173  scsi_out.status = SCSIGood;
174 
175  DPRINTF(UFSHostDevice, "SCSI command:%2x\n", SCSI_msg[4]);
178  switch (SCSI_msg[4] & 0xFF) {
179 
180  case SCSIInquiry: {
184  scsi_out.msgSize = 36;
185  scsi_out.message.dataMsg.resize(9);
186 
187  for (uint8_t count = 0; count < 9; count++)
188  scsi_out.message.dataMsg[count] =
189  (reinterpret_cast<uint32_t*> (&lunInfo))[count];
190  } break;
191 
192  case SCSIRead6: {
196  scsi_out.expectMore = 0x02;
197  scsi_out.msgSize = 0;
198 
199  uint8_t* tempptr = reinterpret_cast<uint8_t*>(&SCSI_msg[4]);
200 
205  uint32_t tmp = *reinterpret_cast<uint32_t*>(tempptr);
206  uint64_t read_offset = betoh(tmp) & 0x1FFFFF;
207 
208  uint32_t read_size = tempptr[4];
209 
210 
211  scsi_out.msgSize = read_size * blkSize;
212  scsi_out.offset = read_offset * blkSize;
213 
214  if ((read_offset + read_size) > diskSize)
215  scsi_out.status = SCSIIllegalRequest;
216 
217  DPRINTF(UFSHostDevice, "Read6 offset: 0x%8x, for %d blocks\n",
218  read_offset, read_size);
219 
223  statusCheck(scsi_out.status, scsi_out.senseCode);
224  scsi_out.senseSize = scsi_out.senseCode[0];
225  scsi_out.status = (scsi_out.status == SCSIGood) ? SCSIGood :
226  SCSICheckCondition;
227 
228  } break;
229 
230  case SCSIRead10: {
231  scsi_out.expectMore = 0x02;
232  scsi_out.msgSize = 0;
233 
234  uint8_t* tempptr = reinterpret_cast<uint8_t*>(&SCSI_msg[4]);
235 
237  uint32_t tmp = *reinterpret_cast<uint32_t*>(&tempptr[2]);
238  uint64_t read_offset = betoh(tmp);
239 
240  uint16_t tmpsize = *reinterpret_cast<uint16_t*>(&tempptr[7]);
241  uint32_t read_size = betoh(tmpsize);
242 
243  scsi_out.msgSize = read_size * blkSize;
244  scsi_out.offset = read_offset * blkSize;
245 
246  if ((read_offset + read_size) > diskSize)
247  scsi_out.status = SCSIIllegalRequest;
248 
249  DPRINTF(UFSHostDevice, "Read10 offset: 0x%8x, for %d blocks\n",
250  read_offset, read_size);
251 
255  statusCheck(scsi_out.status, scsi_out.senseCode);
256  scsi_out.senseSize = scsi_out.senseCode[0];
257  scsi_out.status = (scsi_out.status == SCSIGood) ? SCSIGood :
258  SCSICheckCondition;
259 
260  } break;
261 
262  case SCSIRead16: {
263  scsi_out.expectMore = 0x02;
264  scsi_out.msgSize = 0;
265 
266  uint8_t* tempptr = reinterpret_cast<uint8_t*>(&SCSI_msg[4]);
267 
269  uint32_t tmp = *reinterpret_cast<uint32_t*>(&tempptr[2]);
270  uint64_t read_offset = betoh(tmp);
271 
272  tmp = *reinterpret_cast<uint32_t*>(&tempptr[6]);
273  read_offset = (read_offset << 32) | betoh(tmp);
274 
275  tmp = *reinterpret_cast<uint32_t*>(&tempptr[10]);
276  uint32_t read_size = betoh(tmp);
277 
278  scsi_out.msgSize = read_size * blkSize;
279  scsi_out.offset = read_offset * blkSize;
280 
281  if ((read_offset + read_size) > diskSize)
282  scsi_out.status = SCSIIllegalRequest;
283 
284  DPRINTF(UFSHostDevice, "Read16 offset: 0x%8x, for %d blocks\n",
285  read_offset, read_size);
286 
290  statusCheck(scsi_out.status, scsi_out.senseCode);
291  scsi_out.senseSize = scsi_out.senseCode[0];
292  scsi_out.status = (scsi_out.status == SCSIGood) ? SCSIGood :
293  SCSICheckCondition;
294 
295  } break;
296 
297  case SCSIReadCapacity10: {
301  scsi_out.msgSize = 8;
302  scsi_out.message.dataMsg.resize(2);
303  scsi_out.message.dataMsg[0] =
304  betoh(capacityLower);//last block
305  scsi_out.message.dataMsg[1] = betoh(blkSize);//blocksize
306 
307  } break;
308  case SCSIReadCapacity16: {
309  scsi_out.msgSize = 32;
310  scsi_out.message.dataMsg.resize(8);
311  scsi_out.message.dataMsg[0] =
312  betoh(capacityUpper);//last block
313  scsi_out.message.dataMsg[1] =
314  betoh(capacityLower);//last block
315  scsi_out.message.dataMsg[2] = betoh(blkSize);//blocksize
316  scsi_out.message.dataMsg[3] = 0x00;//
317  scsi_out.message.dataMsg[4] = 0x00;//reserved
318  scsi_out.message.dataMsg[5] = 0x00;//reserved
319  scsi_out.message.dataMsg[6] = 0x00;//reserved
320  scsi_out.message.dataMsg[7] = 0x00;//reserved
321 
322  } break;
323 
324  case SCSIReportLUNs: {
328  scsi_out.msgSize = (lunAvail * 8) + 8;//list + overhead
329  scsi_out.message.dataMsg.resize(2 * lunAvail + 2);
330  scsi_out.message.dataMsg[0] = (lunAvail * 8) << 24;//LUN listlength
331  scsi_out.message.dataMsg[1] = 0x00;
332 
333  for (uint8_t count = 0; count < lunAvail; count++) {
334  //LUN "count"
335  scsi_out.message.dataMsg[2 + 2 * count] = (count & 0x7F) << 8;
336  scsi_out.message.dataMsg[3 + 2 * count] = 0x00;
337  }
338 
339  } break;
340 
341  case SCSIStartStop: {
342  //Just acknowledge; not deemed relevant ATM
343  scsi_out.msgSize = 0;
344 
345  } break;
346 
347  case SCSITestUnitReady: {
348  //Just acknowledge; not deemed relevant ATM
349  scsi_out.msgSize = 0;
350 
351  } break;
352 
353  case SCSIVerify10: {
358  scsi_out.msgSize = 0;
359 
360  uint8_t* tempptr = reinterpret_cast<uint8_t*>(&SCSI_msg[4]);
361 
363  uint32_t tmp = *reinterpret_cast<uint32_t*>(&tempptr[2]);
364  uint64_t read_offset = betoh(tmp);
365 
366  uint16_t tmpsize = *reinterpret_cast<uint16_t*>(&tempptr[7]);
367  uint32_t read_size = betoh(tmpsize);
368 
369  if ((read_offset + read_size) > diskSize)
370  scsi_out.status = SCSIIllegalRequest;
371 
375  statusCheck(scsi_out.status, scsi_out.senseCode);
376  scsi_out.senseSize = scsi_out.senseCode[0];
377  scsi_out.status = (scsi_out.status == SCSIGood) ? SCSIGood :
378  SCSICheckCondition;
379 
380  } break;
381 
382  case SCSIWrite6: {
387  uint8_t* tempptr = reinterpret_cast<uint8_t*>(&SCSI_msg[4]);
388 
393  uint32_t tmp = *reinterpret_cast<uint32_t*>(tempptr);
394  uint64_t write_offset = betoh(tmp) & 0x1FFFFF;
395 
396  uint32_t write_size = tempptr[4];
397 
398  scsi_out.msgSize = write_size * blkSize;
399  scsi_out.offset = write_offset * blkSize;
400  scsi_out.expectMore = 0x01;
401 
402  if ((write_offset + write_size) > diskSize)
403  scsi_out.status = SCSIIllegalRequest;
404 
405  DPRINTF(UFSHostDevice, "Write6 offset: 0x%8x, for %d blocks\n",
406  write_offset, write_size);
407 
411  statusCheck(scsi_out.status, scsi_out.senseCode);
412  scsi_out.senseSize = scsi_out.senseCode[0];
413  scsi_out.status = (scsi_out.status == SCSIGood) ? SCSIGood :
414  SCSICheckCondition;
415 
416  } break;
417 
418  case SCSIWrite10: {
419  uint8_t* tempptr = reinterpret_cast<uint8_t*>(&SCSI_msg[4]);
420 
422  uint32_t tmp = *reinterpret_cast<uint32_t*>(&tempptr[2]);
423  uint64_t write_offset = betoh(tmp);
424 
425  uint16_t tmpsize = *reinterpret_cast<uint16_t*>(&tempptr[7]);
426  uint32_t write_size = betoh(tmpsize);
427 
428  scsi_out.msgSize = write_size * blkSize;
429  scsi_out.offset = write_offset * blkSize;
430  scsi_out.expectMore = 0x01;
431 
432  if ((write_offset + write_size) > diskSize)
433  scsi_out.status = SCSIIllegalRequest;
434 
435  DPRINTF(UFSHostDevice, "Write10 offset: 0x%8x, for %d blocks\n",
436  write_offset, write_size);
437 
441  statusCheck(scsi_out.status, scsi_out.senseCode);
442  scsi_out.senseSize = scsi_out.senseCode[0];
443  scsi_out.status = (scsi_out.status == SCSIGood) ? SCSIGood :
444  SCSICheckCondition;
445 
446  } break;
447 
448  case SCSIWrite16: {
449  uint8_t* tempptr = reinterpret_cast<uint8_t*>(&SCSI_msg[4]);
450 
452  uint32_t tmp = *reinterpret_cast<uint32_t*>(&tempptr[2]);
453  uint64_t write_offset = betoh(tmp);
454 
455  tmp = *reinterpret_cast<uint32_t*>(&tempptr[6]);
456  write_offset = (write_offset << 32) | betoh(tmp);
457 
458  tmp = *reinterpret_cast<uint32_t*>(&tempptr[10]);
459  uint32_t write_size = betoh(tmp);
460 
461  scsi_out.msgSize = write_size * blkSize;
462  scsi_out.offset = write_offset * blkSize;
463  scsi_out.expectMore = 0x01;
464 
465  if ((write_offset + write_size) > diskSize)
466  scsi_out.status = SCSIIllegalRequest;
467 
468  DPRINTF(UFSHostDevice, "Write16 offset: 0x%8x, for %d blocks\n",
469  write_offset, write_size);
470 
474  statusCheck(scsi_out.status, scsi_out.senseCode);
475  scsi_out.senseSize = scsi_out.senseCode[0];
476  scsi_out.status = (scsi_out.status == SCSIGood) ? SCSIGood :
477  SCSICheckCondition;
478 
479  } break;
480 
481  case SCSIFormatUnit: {//not yet verified
482  scsi_out.msgSize = 0;
483  scsi_out.expectMore = 0x01;
484 
485  } break;
486 
487  case SCSISendDiagnostic: {//not yet verified
488  scsi_out.msgSize = 0;
489 
490  } break;
491 
492  case SCSISynchronizeCache: {
493  //do we have cache (we don't have cache at this moment)
494  //TODO: here will synchronization happen when cache is modelled
495  scsi_out.msgSize = 0;
496 
497  } break;
498 
499  //UFS SCSI additional command set for full functionality
500  case SCSIModeSelect10:
501  //TODO:
502  //scsi_out.expectMore = 0x01;//not supported due to modepage support
503  //code isn't dead, code suggest what is to be done when implemented
504  break;
505 
506  case SCSIModeSense6: case SCSIModeSense10: {
511  if ((SCSI_msg[4] & 0x3F0000) >> 16 == 0x0A) {//control page
512  scsi_out.message.dataMsg.resize((sizeof(controlPage) >> 2) + 2);
513  scsi_out.message.dataMsg[0] = 0x00000A00;//control page code
514  scsi_out.message.dataMsg[1] = 0x00000000;//See JEDEC220 ch8
515 
516  for (uint8_t count = 0; count < 3; count++)
517  scsi_out.message.dataMsg[2 + count] = controlPage[count];
518 
519  scsi_out.msgSize = 20;
520  DPRINTF(UFSHostDevice, "CONTROL page\n");
521 
522  } else if ((SCSI_msg[4] & 0x3F0000) >> 16 == 0x01) {//recovery page
523  scsi_out.message.dataMsg.resize((sizeof(recoveryPage) >> 2)
524  + 2);
525 
526  scsi_out.message.dataMsg[0] = 0x00000100;//recovery page code
527  scsi_out.message.dataMsg[1] = 0x00000000;//See JEDEC220 ch8
528 
529  for (uint8_t count = 0; count < 3; count++)
530  scsi_out.message.dataMsg[2 + count] = recoveryPage[count];
531 
532  scsi_out.msgSize = 20;
533  DPRINTF(UFSHostDevice, "RECOVERY page\n");
534 
535  } else if ((SCSI_msg[4] & 0x3F0000) >> 16 == 0x08) {//caching page
536 
537  scsi_out.message.dataMsg.resize((sizeof(cachingPage) >> 2) + 2);
538  scsi_out.message.dataMsg[0] = 0x00001200;//caching page code
539  scsi_out.message.dataMsg[1] = 0x00000000;//See JEDEC220 ch8
540 
541  for (uint8_t count = 0; count < 5; count++)
542  scsi_out.message.dataMsg[2 + count] = cachingPage[count];
543 
544  scsi_out.msgSize = 20;
545  DPRINTF(UFSHostDevice, "CACHE page\n");
546 
547  } else if ((SCSI_msg[4] & 0x3F0000) >> 16 == 0x3F) {//ALL the pages!
548 
549  scsi_out.message.dataMsg.resize(((sizeof(controlPage) +
550  sizeof(recoveryPage) +
551  sizeof(cachingPage)) >> 2)
552  + 2);
553  scsi_out.message.dataMsg[0] = 0x00003200;//all page code
554  scsi_out.message.dataMsg[1] = 0x00000000;//See JEDEC220 ch8
555 
556  for (uint8_t count = 0; count < 3; count++)
557  scsi_out.message.dataMsg[2 + count] = recoveryPage[count];
558 
559  for (uint8_t count = 0; count < 5; count++)
560  scsi_out.message.dataMsg[5 + count] = cachingPage[count];
561 
562  for (uint8_t count = 0; count < 3; count++)
563  scsi_out.message.dataMsg[10 + count] = controlPage[count];
564 
565  scsi_out.msgSize = 52;
566  DPRINTF(UFSHostDevice, "Return ALL the pages!!!\n");
567 
568  } else inform("Wrong mode page requested\n");
569 
570  scsi_out.message.dataCount = scsi_out.msgSize << 24;
571  } break;
572 
573  case SCSIRequestSense: {
574  scsi_out.msgSize = 0;
575 
576  } break;
577 
578  case SCSIUnmap:break;//not yet verified
579 
580  case SCSIWriteBuffer: {
581  scsi_out.expectMore = 0x01;
582 
583  uint8_t* tempptr = reinterpret_cast<uint8_t*>(&SCSI_msg[4]);
584 
586  uint32_t tmp = *reinterpret_cast<uint32_t*>(&tempptr[2]);
587  uint64_t write_offset = betoh(tmp) & 0xFFFFFF;
588 
589  tmp = *reinterpret_cast<uint32_t*>(&tempptr[5]);
590  uint32_t write_size = betoh(tmp) & 0xFFFFFF;
591 
592  scsi_out.msgSize = write_size;
593  scsi_out.offset = write_offset;
594 
595  } break;
596 
597  case SCSIReadBuffer: {
603  scsi_out.expectMore = 0x02;
604 
605  uint8_t* tempptr = reinterpret_cast<uint8_t*>(&SCSI_msg[4]);
606 
608  uint32_t tmp = *reinterpret_cast<uint32_t*>(&tempptr[2]);
609  uint64_t read_offset = betoh(tmp) & 0xFFFFFF;
610 
611  tmp = *reinterpret_cast<uint32_t*>(&tempptr[5]);
612  uint32_t read_size = betoh(tmp) & 0xFFFFFF;
613 
614  scsi_out.msgSize = read_size;
615  scsi_out.offset = read_offset;
616 
617  if ((read_offset + read_size) > capacityLower * blkSize)
618  scsi_out.status = SCSIIllegalRequest;
619 
620  DPRINTF(UFSHostDevice, "Read buffer location: 0x%8x\n",
621  read_offset);
622  DPRINTF(UFSHostDevice, "Number of bytes: 0x%8x\n", read_size);
623 
624  statusCheck(scsi_out.status, scsi_out.senseCode);
625  scsi_out.senseSize = scsi_out.senseCode[0];
626  scsi_out.status = (scsi_out.status == SCSIGood) ? SCSIGood :
627  SCSICheckCondition;
628 
629  } break;
630 
631  case SCSIMaintenanceIn: {
638  DPRINTF(UFSHostDevice, "Ignoring Maintenance In command\n");
639  statusCheck(SCSIIllegalRequest, scsi_out.senseCode);
640  scsi_out.senseSize = scsi_out.senseCode[0];
641  scsi_out.status = (scsi_out.status == SCSIGood) ? SCSIGood :
642  SCSICheckCondition;
643  scsi_out.msgSize = 0;
644  } break;
645 
646  default: {
647  statusCheck(SCSIIllegalRequest, scsi_out.senseCode);
648  scsi_out.senseSize = scsi_out.senseCode[0];
649  scsi_out.status = (scsi_out.status == SCSIGood) ? SCSIGood :
650  SCSICheckCondition;
651  scsi_out.msgSize = 0;
652  inform("Unsupported scsi message type: %2x\n", SCSI_msg[4] & 0xFF);
653  inform("0x%8x\n", SCSI_msg[0]);
654  inform("0x%8x\n", SCSI_msg[1]);
655  inform("0x%8x\n", SCSI_msg[2]);
656  inform("0x%8x\n", SCSI_msg[3]);
657  inform("0x%8x\n", SCSI_msg[4]);
658  } break;
659  }
660 
661  return scsi_out;
662 }
663 
670 void
671 UFSHostDevice::UFSSCSIDevice::statusCheck(uint8_t status,
672  uint8_t* sensecodelist)
673 {
674  for (uint8_t count = 0; count < 19; count++)
675  sensecodelist[count] = 0;
676 
677  sensecodelist[0] = 18; //sense length
678  sensecodelist[1] = 0x70; //we send a valid frame
679  sensecodelist[3] = status & 0xF; //mask to be sure + sensecode
680  sensecodelist[8] = 0x1F; //data length
681 }
682 
687 void
688 UFSHostDevice::UFSSCSIDevice::readFlash(uint8_t* readaddr, uint64_t offset,
689  uint32_t size)
690 {
692  for (int count = 0; count < (size / SectorSize); count++)
693  flashDisk->read(&(readaddr[SectorSize*count]), (offset /
694  SectorSize) + count);
695 }
696 
701 void
702 UFSHostDevice::UFSSCSIDevice::writeFlash(uint8_t* writeaddr, uint64_t offset,
703  uint32_t size)
704 {
706  for (int count = 0; count < (size / SectorSize); count++)
707  flashDisk->write(&(writeaddr[SectorSize * count]),
708  (offset / SectorSize) + count);
709 }
710 
715 UFSHostDevice::UFSHostDevice(const UFSHostDeviceParams* p) :
716  DmaDevice(p),
717  pioAddr(p->pio_addr),
718  pioSize(0x0FFF),
719  pioDelay(p->pio_latency),
720  intNum(p->int_num),
721  gic(p->gic),
722  lunAvail(p->image.size()),
723  UFSSlots(p->ufs_slots - 1),
724  readPendingNum(0),
725  writePendingNum(0),
726  activeDoorbells(0),
727  pendingDoorbells(0),
728  countInt(0),
729  transferTrack(0),
730  taskCommandTrack(0),
731  idlePhaseStart(0),
732  SCSIResumeEvent([this]{ SCSIStart(); }, name()),
733  UTPEvent([this]{ finalUTP(); }, name())
734 {
735  DPRINTF(UFSHostDevice, "The hostcontroller hosts %d Logic units\n",
736  lunAvail);
737  UFSDevice.resize(lunAvail);
738 
739  for (int count = 0; count < lunAvail; count++) {
740  UFSDevice[count] = new UFSSCSIDevice(p, count,
741  [this]() { LUNSignal(); },
742  [this]() { readCallback(); });
743  }
744 
745  if (UFSSlots > 31)
746  warn("UFSSlots = %d, this will results in %d command slots",
747  UFSSlots, (UFSSlots & 0x1F));
748 
749  if ((UFSSlots & 0x1F) == 0)
750  fatal("Number of UFS command slots should be between 1 and 32.");
751 
752  setValues();
753 }
754 
759 UFSHostDevice*
760 UFSHostDeviceParams::create()
761 {
762  return new UFSHostDevice(this);
763 }
764 
765 
766 void
767 UFSHostDevice::regStats()
768 {
769  DmaDevice::regStats();
770 
771  using namespace Stats;
772 
773  std::string UFSHost_name = name() + ".UFSDiskHost";
774 
775  // Register the stats
777  stats.currentSCSIQueue
778  .name(UFSHost_name + ".currentSCSIQueue")
779  .desc("Most up to date length of the command queue")
780  .flags(none);
781  stats.currentReadSSDQueue
782  .name(UFSHost_name + ".currentReadSSDQueue")
783  .desc("Most up to date length of the read SSD queue")
784  .flags(none);
785  stats.currentWriteSSDQueue
786  .name(UFSHost_name + ".currentWriteSSDQueue")
787  .desc("Most up to date length of the write SSD queue")
788  .flags(none);
789 
791  stats.totalReadSSD
792  .name(UFSHost_name + ".totalReadSSD")
793  .desc("Number of bytes read from SSD")
794  .flags(none);
795 
796  stats.totalWrittenSSD
797  .name(UFSHost_name + ".totalWrittenSSD")
798  .desc("Number of bytes written to SSD")
799  .flags(none);
800 
801  stats.totalReadDiskTransactions
802  .name(UFSHost_name + ".totalReadDiskTransactions")
803  .desc("Number of transactions from disk")
804  .flags(none);
805  stats.totalWriteDiskTransactions
806  .name(UFSHost_name + ".totalWriteDiskTransactions")
807  .desc("Number of transactions to disk")
808  .flags(none);
809  stats.totalReadUFSTransactions
810  .name(UFSHost_name + ".totalReadUFSTransactions")
811  .desc("Number of transactions from device")
812  .flags(none);
813  stats.totalWriteUFSTransactions
814  .name(UFSHost_name + ".totalWriteUFSTransactions")
815  .desc("Number of transactions to device")
816  .flags(none);
817 
819  stats.averageReadSSDBW
820  .name(UFSHost_name + ".averageReadSSDBandwidth")
821  .desc("Average read bandwidth (bytes/s)")
822  .flags(nozero);
823 
824  stats.averageReadSSDBW = stats.totalReadSSD / simSeconds;
825 
826  stats.averageWriteSSDBW
827  .name(UFSHost_name + ".averageWriteSSDBandwidth")
828  .desc("Average write bandwidth (bytes/s)")
829  .flags(nozero);
830 
831  stats.averageWriteSSDBW = stats.totalWrittenSSD / simSeconds;
832 
833  stats.averageSCSIQueue
834  .name(UFSHost_name + ".averageSCSIQueueLength")
835  .desc("Average command queue length")
836  .flags(nozero);
837  stats.averageReadSSDQueue
838  .name(UFSHost_name + ".averageReadSSDQueueLength")
839  .desc("Average read queue length")
840  .flags(nozero);
841  stats.averageWriteSSDQueue
842  .name(UFSHost_name + ".averageWriteSSDQueueLength")
843  .desc("Average write queue length")
844  .flags(nozero);
845 
847  stats.curDoorbell
848  .name(UFSHost_name + ".curDoorbell")
849  .desc("Most up to date number of doorbells used")
850  .flags(none);
851 
852  stats.curDoorbell = activeDoorbells;
853 
854  stats.maxDoorbell
855  .name(UFSHost_name + ".maxDoorbell")
856  .desc("Maximum number of doorbells utilized")
857  .flags(none);
858  stats.averageDoorbell
859  .name(UFSHost_name + ".averageDoorbell")
860  .desc("Average number of Doorbells used")
861  .flags(nozero);
862 
864  stats.transactionLatency
865  .init(100)
866  .name(UFSHost_name + ".transactionLatency")
867  .desc("Histogram of transaction times")
868  .flags(pdf);
869 
870  stats.idleTimes
871  .init(100)
872  .name(UFSHost_name + ".idlePeriods")
873  .desc("Histogram of idle times")
874  .flags(pdf);
875 
876 }
877 
881 void UFSHostDevice::setValues()
882 {
888  UFSHCIMem.HCCAP = 0x06070000 | (UFSSlots & 0x1F);
889  UFSHCIMem.HCversion = 0x00010000; //version is 1.0
890  UFSHCIMem.HCHCDDID = 0xAA003C3C;// Arbitrary number
891  UFSHCIMem.HCHCPMID = 0x41524D48; //ARMH (not an official MIPI number)
892  UFSHCIMem.TRUTRLDBR = 0x00;
893  UFSHCIMem.TMUTMRLDBR = 0x00;
894  UFSHCIMem.CMDUICCMDR = 0x00;
895  // We can process CMD, TM, TR, device present
896  UFSHCIMem.ORHostControllerStatus = 0x08;
897  UFSHCIMem.TRUTRLBA = 0x00;
898  UFSHCIMem.TRUTRLBAU = 0x00;
899  UFSHCIMem.TMUTMRLBA = 0x00;
900  UFSHCIMem.TMUTMRLBAU = 0x00;
901 }
902 
907 AddrRangeList
908 UFSHostDevice::getAddrRanges() const
909 {
910  AddrRangeList ranges;
911  ranges.push_back(RangeSize(pioAddr, pioSize));
912  return ranges;
913 }
914 
920 Tick
921 UFSHostDevice::read(PacketPtr pkt)
922 {
923  uint32_t data = 0;
924 
925  switch (pkt->getAddr() & 0xFF)
926  {
927 
928  case regControllerCapabilities:
929  data = UFSHCIMem.HCCAP;
930  break;
931 
932  case regUFSVersion:
933  data = UFSHCIMem.HCversion;
934  break;
935 
936  case regControllerDEVID:
937  data = UFSHCIMem.HCHCDDID;
938  break;
939 
940  case regControllerPRODID:
941  data = UFSHCIMem.HCHCPMID;
942  break;
943 
944  case regInterruptStatus:
945  data = UFSHCIMem.ORInterruptStatus;
946  UFSHCIMem.ORInterruptStatus = 0x00;
947  //TODO: Revise and extend
948  clearInterrupt();
949  break;
950 
951  case regInterruptEnable:
952  data = UFSHCIMem.ORInterruptEnable;
953  break;
954 
955  case regControllerStatus:
956  data = UFSHCIMem.ORHostControllerStatus;
957  break;
958 
959  case regControllerEnable:
960  data = UFSHCIMem.ORHostControllerEnable;
961  break;
962 
963  case regUICErrorCodePHYAdapterLayer:
964  data = UFSHCIMem.ORUECPA;
965  break;
966 
967  case regUICErrorCodeDataLinkLayer:
968  data = UFSHCIMem.ORUECDL;
969  break;
970 
971  case regUICErrorCodeNetworkLayer:
972  data = UFSHCIMem.ORUECN;
973  break;
974 
975  case regUICErrorCodeTransportLayer:
976  data = UFSHCIMem.ORUECT;
977  break;
978 
979  case regUICErrorCodeDME:
980  data = UFSHCIMem.ORUECDME;
981  break;
982 
983  case regUTPTransferREQINTAGGControl:
984  data = UFSHCIMem.ORUTRIACR;
985  break;
986 
987  case regUTPTransferREQListBaseL:
988  data = UFSHCIMem.TRUTRLBA;
989  break;
990 
991  case regUTPTransferREQListBaseH:
992  data = UFSHCIMem.TRUTRLBAU;
993  break;
994 
995  case regUTPTransferREQDoorbell:
996  data = UFSHCIMem.TRUTRLDBR;
997  break;
998 
999  case regUTPTransferREQListClear:
1000  data = UFSHCIMem.TRUTRLCLR;
1001  break;
1002 
1003  case regUTPTransferREQListRunStop:
1004  data = UFSHCIMem.TRUTRLRSR;
1005  break;
1006 
1007  case regUTPTaskREQListBaseL:
1008  data = UFSHCIMem.TMUTMRLBA;
1009  break;
1010 
1011  case regUTPTaskREQListBaseH:
1012  data = UFSHCIMem.TMUTMRLBAU;
1013  break;
1014 
1015  case regUTPTaskREQDoorbell:
1016  data = UFSHCIMem.TMUTMRLDBR;
1017  break;
1018 
1019  case regUTPTaskREQListClear:
1020  data = UFSHCIMem.TMUTMRLCLR;
1021  break;
1022 
1023  case regUTPTaskREQListRunStop:
1024  data = UFSHCIMem.TMUTMRLRSR;
1025  break;
1026 
1027  case regUICCommand:
1028  data = UFSHCIMem.CMDUICCMDR;
1029  break;
1030 
1031  case regUICCommandArg1:
1032  data = UFSHCIMem.CMDUCMDARG1;
1033  break;
1034 
1035  case regUICCommandArg2:
1036  data = UFSHCIMem.CMDUCMDARG2;
1037  break;
1038 
1039  case regUICCommandArg3:
1040  data = UFSHCIMem.CMDUCMDARG3;
1041  break;
1042 
1043  default:
1044  data = 0x00;
1045  break;
1046  }
1047 
1048  pkt->setLE<uint32_t>(data);
1049  pkt->makeResponse();
1050  return pioDelay;
1051 }
1052 
1058 Tick
1059 UFSHostDevice::write(PacketPtr pkt)
1060 {
1061  uint32_t data = 0;
1062 
1063  switch (pkt->getSize()) {
1064 
1065  case 1:
1066  data = pkt->getLE<uint8_t>();
1067  break;
1068 
1069  case 2:
1070  data = pkt->getLE<uint16_t>();
1071  break;
1072 
1073  case 4:
1074  data = pkt->getLE<uint32_t>();
1075  break;
1076 
1077  default:
1078  panic("Undefined UFSHCD controller write size!\n");
1079  break;
1080  }
1081 
1082  switch (pkt->getAddr() & 0xFF)
1083  {
1084  case regControllerCapabilities://you shall not write to this
1085  break;
1086 
1087  case regUFSVersion://you shall not write to this
1088  break;
1089 
1090  case regControllerDEVID://you shall not write to this
1091  break;
1092 
1093  case regControllerPRODID://you shall not write to this
1094  break;
1095 
1096  case regInterruptStatus://you shall not write to this
1097  break;
1098 
1099  case regInterruptEnable:
1100  UFSHCIMem.ORInterruptEnable = data;
1101  break;
1102 
1103  case regControllerStatus:
1104  UFSHCIMem.ORHostControllerStatus = data;
1105  break;
1106 
1107  case regControllerEnable:
1108  UFSHCIMem.ORHostControllerEnable = data;
1109  break;
1110 
1111  case regUICErrorCodePHYAdapterLayer:
1112  UFSHCIMem.ORUECPA = data;
1113  break;
1114 
1115  case regUICErrorCodeDataLinkLayer:
1116  UFSHCIMem.ORUECDL = data;
1117  break;
1118 
1119  case regUICErrorCodeNetworkLayer:
1120  UFSHCIMem.ORUECN = data;
1121  break;
1122 
1123  case regUICErrorCodeTransportLayer:
1124  UFSHCIMem.ORUECT = data;
1125  break;
1126 
1127  case regUICErrorCodeDME:
1128  UFSHCIMem.ORUECDME = data;
1129  break;
1130 
1131  case regUTPTransferREQINTAGGControl:
1132  UFSHCIMem.ORUTRIACR = data;
1133  break;
1134 
1135  case regUTPTransferREQListBaseL:
1136  UFSHCIMem.TRUTRLBA = data;
1137  if (((UFSHCIMem.TRUTRLBA | UFSHCIMem.TRUTRLBAU) != 0x00) &&
1138  ((UFSHCIMem.TMUTMRLBA | UFSHCIMem.TMUTMRLBAU)!= 0x00))
1139  UFSHCIMem.ORHostControllerStatus |= UICCommandReady;
1140  break;
1141 
1142  case regUTPTransferREQListBaseH:
1143  UFSHCIMem.TRUTRLBAU = data;
1144  if (((UFSHCIMem.TRUTRLBA | UFSHCIMem.TRUTRLBAU) != 0x00) &&
1145  ((UFSHCIMem.TMUTMRLBA | UFSHCIMem.TMUTMRLBAU) != 0x00))
1146  UFSHCIMem.ORHostControllerStatus |= UICCommandReady;
1147  break;
1148 
1149  case regUTPTransferREQDoorbell:
1150  if (!(UFSHCIMem.TRUTRLDBR) && data)
1151  stats.idleTimes.sample(curTick() - idlePhaseStart);
1152  UFSHCIMem.TRUTRLDBR |= data;
1153  requestHandler();
1154  break;
1155 
1156  case regUTPTransferREQListClear:
1157  UFSHCIMem.TRUTRLCLR = data;
1158  break;
1159 
1160  case regUTPTransferREQListRunStop:
1161  UFSHCIMem.TRUTRLRSR = data;
1162  break;
1163 
1164  case regUTPTaskREQListBaseL:
1165  UFSHCIMem.TMUTMRLBA = data;
1166  if (((UFSHCIMem.TRUTRLBA | UFSHCIMem.TRUTRLBAU) != 0x00) &&
1167  ((UFSHCIMem.TMUTMRLBA | UFSHCIMem.TMUTMRLBAU) != 0x00))
1168  UFSHCIMem.ORHostControllerStatus |= UICCommandReady;
1169  break;
1170 
1171  case regUTPTaskREQListBaseH:
1172  UFSHCIMem.TMUTMRLBAU = data;
1173  if (((UFSHCIMem.TRUTRLBA | UFSHCIMem.TRUTRLBAU) != 0x00) &&
1174  ((UFSHCIMem.TMUTMRLBA | UFSHCIMem.TMUTMRLBAU) != 0x00))
1175  UFSHCIMem.ORHostControllerStatus |= UICCommandReady;
1176  break;
1177 
1178  case regUTPTaskREQDoorbell:
1179  UFSHCIMem.TMUTMRLDBR |= data;
1180  requestHandler();
1181  break;
1182 
1183  case regUTPTaskREQListClear:
1184  UFSHCIMem.TMUTMRLCLR = data;
1185  break;
1186 
1187  case regUTPTaskREQListRunStop:
1188  UFSHCIMem.TMUTMRLRSR = data;
1189  break;
1190 
1191  case regUICCommand:
1192  UFSHCIMem.CMDUICCMDR = data;
1193  requestHandler();
1194  break;
1195 
1196  case regUICCommandArg1:
1197  UFSHCIMem.CMDUCMDARG1 = data;
1198  break;
1199 
1200  case regUICCommandArg2:
1201  UFSHCIMem.CMDUCMDARG2 = data;
1202  break;
1203 
1204  case regUICCommandArg3:
1205  UFSHCIMem.CMDUCMDARG3 = data;
1206  break;
1207 
1208  default:break;//nothing happens, you try to access a register that
1209  //does not exist
1210 
1211  }
1212 
1213  pkt->makeResponse();
1214  return pioDelay;
1215 }
1216 
1222 void
1223 UFSHostDevice::requestHandler()
1224 {
1225  Addr address = 0x00;
1226  int mask = 0x01;
1227  int size;
1228  int count = 0;
1229  struct taskStart task_info;
1230  struct transferStart transferstart_info;
1231  transferstart_info.done = 0;
1232 
1238  while (((UFSHCIMem.CMDUICCMDR > 0x00) |
1239  ((UFSHCIMem.TMUTMRLDBR ^ taskCommandTrack) > 0x00) |
1240  ((UFSHCIMem.TRUTRLDBR ^ transferTrack) > 0x00)) ) {
1241 
1242  if (UFSHCIMem.CMDUICCMDR > 0x00) {
1247  commandHandler();
1248  UFSHCIMem.ORInterruptStatus |= UICCommandCOMPL;
1249  generateInterrupt();
1250  UFSHCIMem.CMDUICCMDR = 0x00;
1251  return; //command, nothing more we can do
1252 
1253  } else if ((UFSHCIMem.TMUTMRLDBR ^ taskCommandTrack) > 0x00) {
1258  size = sizeof(UTPUPIUTaskReq);
1260  count = findLsbSet((UFSHCIMem.TMUTMRLDBR ^ taskCommandTrack));
1261  address = UFSHCIMem.TMUTMRLBAU;
1262  //<-64 bit
1263  address = (count * size) + (address << 32) +
1264  UFSHCIMem.TMUTMRLBA;
1265  taskCommandTrack |= mask << count;
1266 
1267  inform("UFSmodel received a task from the system; this might"
1268  " lead to untested behaviour.\n");
1269 
1270  task_info.mask = mask << count;
1271  task_info.address = address;
1272  task_info.size = size;
1273  task_info.done = UFSHCIMem.TMUTMRLDBR;
1274  taskInfo.push_back(task_info);
1275  taskEventQueue.push_back(
1276  EventFunctionWrapper([this]{ taskStart(); }, name()));
1277  writeDevice(&taskEventQueue.back(), false, address, size,
1278  reinterpret_cast<uint8_t*>
1279  (&taskInfo.back().destination), 0, 0);
1280 
1281  } else if ((UFSHCIMem.TRUTRLDBR ^ transferTrack) > 0x00) {
1287  size = sizeof(UTPTransferReqDesc);
1289  count = findLsbSet((UFSHCIMem.TRUTRLDBR ^ transferTrack));
1290  address = UFSHCIMem.TRUTRLBAU;
1291  //<-64 bit
1292  address = (count * size) + (address << 32) + UFSHCIMem.TRUTRLBA;
1293 
1294  transferTrack |= mask << count;
1295  DPRINTF(UFSHostDevice, "Doorbell register: 0x%8x select #:"
1296  " 0x%8x completion info: 0x%8x\n", UFSHCIMem.TRUTRLDBR,
1297  count, transferstart_info.done);
1298 
1299  transferstart_info.done = UFSHCIMem.TRUTRLDBR;
1300 
1302  transactionStart[count] = curTick(); //note the start time
1303  ++activeDoorbells;
1304  stats.maxDoorbell = (stats.maxDoorbell.value() < activeDoorbells)
1305  ? activeDoorbells : stats.maxDoorbell.value();
1306  stats.averageDoorbell = stats.maxDoorbell.value();
1307 
1313  transferstart_info.mask = mask << count;
1314  transferstart_info.address = address;
1315  transferstart_info.size = size;
1316  transferstart_info.done = UFSHCIMem.TRUTRLDBR;
1317  transferStartInfo.push_back(transferstart_info);
1318 
1320  transferStartInfo.back().destination = new struct
1321  UTPTransferReqDesc;
1322  DPRINTF(UFSHostDevice, "Initial transfer start: 0x%8x\n",
1323  transferstart_info.done);
1324  transferEventQueue.push_back(
1325  EventFunctionWrapper([this]{ transferStart(); }, name()));
1326 
1327  if (transferEventQueue.size() < 2) {
1328  writeDevice(&transferEventQueue.front(), false,
1329  address, size, reinterpret_cast<uint8_t*>
1330  (transferStartInfo.front().destination),0, 0);
1331  DPRINTF(UFSHostDevice, "Transfer scheduled\n");
1332  }
1333  }
1334  }
1335 }
1336 
1341 void
1342 UFSHostDevice::taskStart()
1343 {
1344  DPRINTF(UFSHostDevice, "Task start");
1345  taskHandler(&taskInfo.front().destination, taskInfo.front().mask,
1346  taskInfo.front().address, taskInfo.front().size);
1347  taskInfo.pop_front();
1348  taskEventQueue.pop_front();
1349 }
1350 
1355 void
1356 UFSHostDevice::transferStart()
1357 {
1358  DPRINTF(UFSHostDevice, "Enter transfer event\n");
1359  transferHandler(transferStartInfo.front().destination,
1360  transferStartInfo.front().mask,
1361  transferStartInfo.front().address,
1362  transferStartInfo.front().size,
1363  transferStartInfo.front().done);
1364 
1365  transferStartInfo.pop_front();
1366  DPRINTF(UFSHostDevice, "Transfer queue size at end of event: "
1367  "0x%8x\n", transferEventQueue.size());
1368 }
1369 
1375 void
1376 UFSHostDevice::commandHandler()
1377 {
1378  if (UFSHCIMem.CMDUICCMDR == 0x16) {
1379  UFSHCIMem.ORHostControllerStatus |= 0x0F;//link startup
1380  }
1381 
1382 }
1383 
1389 void
1390 UFSHostDevice::taskHandler(struct UTPUPIUTaskReq* request_in,
1391  uint32_t req_pos, Addr finaladdress, uint32_t
1392  finalsize)
1393 {
1398  inform("taskHandler\n");
1399  inform("%8x\n", request_in->header.dWord0);
1400  inform("%8x\n", request_in->header.dWord1);
1401  inform("%8x\n", request_in->header.dWord2);
1402 
1403  request_in->header.dWord2 &= 0xffffff00;
1404 
1405  UFSHCIMem.TMUTMRLDBR &= ~(req_pos);
1406  taskCommandTrack &= ~(req_pos);
1407  UFSHCIMem.ORInterruptStatus |= UTPTaskREQCOMPL;
1408 
1409  readDevice(true, finaladdress, finalsize, reinterpret_cast<uint8_t*>
1410  (request_in), true, NULL);
1411 
1412 }
1413 
1425 void
1426 UFSHostDevice::transferHandler(struct UTPTransferReqDesc* request_in,
1427  int req_pos, Addr finaladdress, uint32_t
1428  finalsize, uint32_t done)
1429 {
1430 
1431  Addr cmd_desc_addr = 0x00;
1432 
1433 
1434  //acknowledge handling of the message
1435  DPRINTF(UFSHostDevice, "SCSI message detected\n");
1436  request_in->header.dWord2 &= 0xffffff00;
1437  SCSIInfo.RequestIn = request_in;
1438  SCSIInfo.reqPos = req_pos;
1439  SCSIInfo.finalAddress = finaladdress;
1440  SCSIInfo.finalSize = finalsize;
1441  SCSIInfo.destination.resize(request_in->PRDTableOffset * 4
1442  + request_in->PRDTableLength * sizeof(UFSHCDSGEntry));
1443  SCSIInfo.done = done;
1444 
1445  assert(!SCSIResumeEvent.scheduled());
1449  cmd_desc_addr = request_in->commandDescBaseAddrHi;
1450  cmd_desc_addr = (cmd_desc_addr << 32) |
1451  (request_in->commandDescBaseAddrLo & 0xffffffff);
1452 
1453  writeDevice(&SCSIResumeEvent, false, cmd_desc_addr,
1454  SCSIInfo.destination.size(), &SCSIInfo.destination[0],0, 0);
1455 
1456  DPRINTF(UFSHostDevice, "SCSI scheduled\n");
1457 
1458  transferEventQueue.pop_front();
1459 }
1460 
1468 void
1469 UFSHostDevice::SCSIStart()
1470 {
1471  DPRINTF(UFSHostDevice, "SCSI message on hold until ready\n");
1472  uint32_t LUN = SCSIInfo.destination[2];
1473  UFSDevice[LUN]->SCSIInfoQueue.push_back(SCSIInfo);
1474 
1475  DPRINTF(UFSHostDevice, "SCSI queue %d has %d elements\n", LUN,
1476  UFSDevice[LUN]->SCSIInfoQueue.size());
1477 
1479  if (UFSDevice[LUN]->SCSIInfoQueue.size() < 2) //LUN is available
1480  SCSIResume(LUN);
1481 
1482  else if (UFSDevice[LUN]->SCSIInfoQueue.size() > 32)
1483  panic("SCSI queue is getting too big %d\n", UFSDevice[LUN]->
1484  SCSIInfoQueue.size());
1485 
1490  if (!transferEventQueue.empty()) {
1491 
1496  writeDevice(&transferEventQueue.front(), false,
1497  transferStartInfo.front().address,
1498  transferStartInfo.front().size, reinterpret_cast<uint8_t*>
1499  (transferStartInfo.front().destination), 0, 0);
1500 
1501  DPRINTF(UFSHostDevice, "Transfer scheduled");
1502  }
1503 }
1504 
1513 void
1514 UFSHostDevice::SCSIResume(uint32_t lun_id)
1515 {
1516  DPRINTF(UFSHostDevice, "SCSIresume\n");
1517  if (UFSDevice[lun_id]->SCSIInfoQueue.empty())
1518  panic("No SCSI message scheduled lun:%d Doorbell: 0x%8x", lun_id,
1519  UFSHCIMem.TRUTRLDBR);
1520 
1522  struct UTPTransferReqDesc* request_in = UFSDevice[lun_id]->
1523  SCSIInfoQueue.front().RequestIn;
1524 
1525  uint32_t req_pos = UFSDevice[lun_id]->SCSIInfoQueue.front().reqPos;
1526 
1527  Addr finaladdress = UFSDevice[lun_id]->SCSIInfoQueue.front().
1528  finalAddress;
1529 
1530  uint32_t finalsize = UFSDevice[lun_id]->SCSIInfoQueue.front().finalSize;
1531 
1532  uint32_t* transfercommand = reinterpret_cast<uint32_t*>
1533  (&(UFSDevice[lun_id]->SCSIInfoQueue.front().destination[0]));
1534 
1535  DPRINTF(UFSHostDevice, "Task tag: 0x%8x\n", transfercommand[0]>>24);
1537  request_out_datain = UFSDevice[(transfercommand[0] & 0xFF0000) >> 16]->
1538  SCSICMDHandle(transfercommand);
1539 
1540  DPRINTF(UFSHostDevice, "LUN: %d\n", request_out_datain.LUN);
1541 
1546  request_in->header.dWord0 = ((request_in->header.dWord0 >> 24) == 0x21)
1547  ? 0x36 : 0x21;
1548  UFSDevice[lun_id]->transferInfo.requestOut.header.dWord0 =
1549  request_in->header.dWord0 | (request_out_datain.LUN << 8)
1550  | (transfercommand[0] & 0xFF000000);
1552  UFSDevice[lun_id]->transferInfo.requestOut.header.dWord1 = 0x00000000 |
1553  (request_out_datain.status << 24);
1555  UFSDevice[lun_id]->transferInfo.requestOut.header.dWord2 = 0x00000000 |
1556  ((request_out_datain.senseSize + 2) << 24) | 0x05;
1558  UFSDevice[lun_id]->transferInfo.requestOut.senseDataLen =
1559  request_out_datain.senseSize;
1560 
1561  //data
1562  for (uint8_t count = 0; count<request_out_datain.senseSize; count++) {
1563  UFSDevice[lun_id]->transferInfo.requestOut.senseData[count] =
1564  request_out_datain.senseCode[count + 1];
1565  }
1566 
1567  /*
1568  * At position defined by "request_in->PRDTableOffset" (counting 32 bit
1569  * words) in array "transfercommand" we have a scatter gather list, which
1570  * is usefull to us if we interpreted it as a UFSHCDSGEntry structure.
1571  */
1572  struct UFSHCDSGEntry* sglist = reinterpret_cast<UFSHCDSGEntry*>
1573  (&(transfercommand[(request_in->PRDTableOffset)]));
1574 
1575  uint32_t length = request_in->PRDTableLength;
1576  DPRINTF(UFSHostDevice, "# PRDT entries: %d\n", length);
1577 
1578  Addr response_addr = request_in->commandDescBaseAddrHi;
1579  response_addr = (response_addr << 32) |
1580  ((request_in->commandDescBaseAddrLo +
1581  (request_in->responseUPIULength << 2)) & 0xffffffff);
1582 
1584  UFSDevice[lun_id]->transferInfo.responseStartAddr = response_addr;
1585  UFSDevice[lun_id]->transferInfo.reqPos = req_pos;
1586  UFSDevice[lun_id]->transferInfo.size = finalsize;
1587  UFSDevice[lun_id]->transferInfo.address = finaladdress;
1588  UFSDevice[lun_id]->transferInfo.destination = reinterpret_cast<uint8_t*>
1589  (UFSDevice[lun_id]->SCSIInfoQueue.front().RequestIn);
1590  UFSDevice[lun_id]->transferInfo.finished = true;
1591  UFSDevice[lun_id]->transferInfo.lunID = request_out_datain.LUN;
1592 
1598  if (request_out_datain.expectMore == 0x01) {
1600  manageWriteTransfer(request_out_datain.LUN, request_out_datain.offset,
1601  length, sglist);
1602 
1603  } else if (request_out_datain.expectMore == 0x02) {
1605  manageReadTransfer(request_out_datain.msgSize, request_out_datain.LUN,
1606  request_out_datain.offset, length, sglist);
1607 
1608  } else {
1610  uint32_t count = 0;
1611  uint32_t size_accum = 0;
1612  DPRINTF(UFSHostDevice, "Data DMA size: 0x%8x\n",
1613  request_out_datain.msgSize);
1614 
1616  while ((length > count) && size_accum
1617  < (request_out_datain.msgSize - 1) &&
1618  (request_out_datain.msgSize != 0x00)) {
1619  Addr SCSI_start = sglist[count].upperAddr;
1620  SCSI_start = (SCSI_start << 32) |
1621  (sglist[count].baseAddr & 0xFFFFFFFF);
1622  DPRINTF(UFSHostDevice, "Data DMA start: 0x%8x\n", SCSI_start);
1623  DPRINTF(UFSHostDevice, "Data DMA size: 0x%8x\n",
1624  (sglist[count].size + 1));
1632  uint32_t size_to_send = sglist[count].size + 1;
1633 
1634  if (request_out_datain.msgSize < (size_to_send + size_accum))
1635  size_to_send = request_out_datain.msgSize - size_accum;
1636 
1637  readDevice(false, SCSI_start, size_to_send,
1638  reinterpret_cast<uint8_t*>
1639  (&(request_out_datain.message.dataMsg[size_accum])),
1640  false, NULL);
1641 
1642  size_accum += size_to_send;
1643  DPRINTF(UFSHostDevice, "Total remaining: 0x%8x,accumulated so far"
1644  " : 0x%8x\n", (request_out_datain.msgSize - size_accum),
1645  size_accum);
1646 
1647  ++count;
1648  DPRINTF(UFSHostDevice, "Transfer #: %d\n", count);
1649  }
1650 
1652  transferDone(response_addr, req_pos, UFSDevice[lun_id]->
1653  transferInfo.requestOut, finalsize, finaladdress,
1654  reinterpret_cast<uint8_t*>(request_in), true, lun_id);
1655  }
1656 
1657  DPRINTF(UFSHostDevice, "SCSI resume done\n");
1658 }
1659 
1665 void
1666 UFSHostDevice::LUNSignal()
1667 {
1668  uint8_t this_lun = 0;
1669 
1670  //while we haven't found the right lun, keep searching
1671  while ((this_lun < lunAvail) && !UFSDevice[this_lun]->finishedCommand())
1672  ++this_lun;
1673 
1674  if (this_lun < lunAvail) {
1675  //Clear signal.
1676  UFSDevice[this_lun]->clearSignal();
1677  //found it; call transferDone
1678  transferDone(UFSDevice[this_lun]->transferInfo.responseStartAddr,
1679  UFSDevice[this_lun]->transferInfo.reqPos,
1680  UFSDevice[this_lun]->transferInfo.requestOut,
1681  UFSDevice[this_lun]->transferInfo.size,
1682  UFSDevice[this_lun]->transferInfo.address,
1683  UFSDevice[this_lun]->transferInfo.destination,
1684  UFSDevice[this_lun]->transferInfo.finished,
1685  UFSDevice[this_lun]->transferInfo.lunID);
1686  }
1687 
1688  else
1689  panic("no LUN finished in tick %d\n", curTick());
1690 }
1691 
1697 void
1698 UFSHostDevice::transferDone(Addr responseStartAddr, uint32_t req_pos,
1699  struct UTPUPIURSP request_out, uint32_t size,
1700  Addr address, uint8_t* destination,
1701  bool finished, uint32_t lun_id)
1702 {
1704  if (UFSDevice[lun_id]->SCSIInfoQueue.empty())
1705  panic("No SCSI message scheduled lun:%d Doorbell: 0x%8x", lun_id,
1706  UFSHCIMem.TRUTRLDBR);
1707 
1708  DPRINTF(UFSHostDevice, "DMA start: 0x%8x; DMA size: 0x%8x\n",
1709  responseStartAddr, sizeof(request_out));
1710 
1711  struct transferStart lastinfo;
1712  lastinfo.mask = req_pos;
1713  lastinfo.done = finished;
1714  lastinfo.address = address;
1715  lastinfo.size = size;
1716  lastinfo.destination = reinterpret_cast<UTPTransferReqDesc*>
1717  (destination);
1718  lastinfo.lun_id = lun_id;
1719 
1720  transferEnd.push_back(lastinfo);
1721 
1722  DPRINTF(UFSHostDevice, "Transfer done start\n");
1723 
1724  readDevice(false, responseStartAddr, sizeof(request_out),
1725  reinterpret_cast<uint8_t*>
1726  (&(UFSDevice[lun_id]->transferInfo.requestOut)),
1727  true, &UTPEvent);
1728 }
1729 
1736 void
1737 UFSHostDevice::finalUTP()
1738 {
1739  uint32_t lun_id = transferEnd.front().lun_id;
1740 
1741  UFSDevice[lun_id]->SCSIInfoQueue.pop_front();
1742  DPRINTF(UFSHostDevice, "SCSIInfoQueue size: %d, lun: %d\n",
1743  UFSDevice[lun_id]->SCSIInfoQueue.size(), lun_id);
1744 
1746  if (UFSHCIMem.TRUTRLDBR & transferEnd.front().mask) {
1747  uint8_t count = 0;
1748  while (!(transferEnd.front().mask & (0x1 << count)))
1749  ++count;
1750  stats.transactionLatency.sample(curTick() -
1751  transactionStart[count]);
1752  }
1753 
1755  readDevice(true, transferEnd.front().address,
1756  transferEnd.front().size, reinterpret_cast<uint8_t*>
1757  (transferEnd.front().destination), true, NULL);
1758 
1760  transferTrack &= ~(transferEnd.front().mask);
1761  --activeDoorbells;
1762  ++pendingDoorbells;
1763  garbage.push_back(transferEnd.front().destination);
1764  transferEnd.pop_front();
1765  DPRINTF(UFSHostDevice, "UTP handled\n");
1766 
1768  stats.averageDoorbell = stats.maxDoorbell.value();
1769 
1770  DPRINTF(UFSHostDevice, "activeDoorbells: %d, pendingDoorbells: %d,"
1771  " garbage: %d, TransferEvent: %d\n", activeDoorbells,
1772  pendingDoorbells, garbage.size(), transferEventQueue.size());
1773 
1775  if (!UFSDevice[lun_id]->SCSIInfoQueue.empty())
1776  SCSIResume(lun_id);
1777 }
1778 
1782 void
1783 UFSHostDevice::readDone()
1784 {
1785  DPRINTF(UFSHostDevice, "Read done start\n");
1786  --readPendingNum;
1787 
1789  if (garbage.size() > 0) {
1790  delete garbage.front();
1791  garbage.pop_front();
1792  }
1793 
1795  if (!(UFSHCIMem.ORInterruptStatus & 0x01)) {
1796  UFSHCIMem.ORInterruptStatus |= UTPTransferREQCOMPL;
1797  generateInterrupt();
1798  }
1799 
1800 
1801  if (!readDoneEvent.empty()) {
1802  readDoneEvent.pop_front();
1803  }
1804 }
1805 
1810 void
1811 UFSHostDevice::generateInterrupt()
1812 {
1814  countInt++;
1815 
1817  UFSHCIMem.TRUTRLDBR &= transferTrack;
1818  pendingDoorbells = 0;
1819  DPRINTF(UFSHostDevice, "Clear doorbell %X\n", UFSHCIMem.TRUTRLDBR);
1820 
1821  checkDrain();
1822 
1824  gic->sendInt(intNum);
1825  DPRINTF(UFSHostDevice, "Send interrupt @ transaction: 0x%8x!\n",
1826  countInt);
1827 }
1828 
1833 void
1834 UFSHostDevice::clearInterrupt()
1835 {
1836  gic->clearInt(intNum);
1837  DPRINTF(UFSHostDevice, "Clear interrupt: 0x%8x!\n", countInt);
1838 
1839  checkDrain();
1840 
1841  if (!(UFSHCIMem.TRUTRLDBR)) {
1842  idlePhaseStart = curTick();
1843  }
1845 }
1846 
1871 void
1872 UFSHostDevice::writeDevice(Event* additional_action, bool toDisk, Addr
1873  start, int size, uint8_t* destination, uint64_t
1874  SCSIDiskOffset, uint32_t lun_id)
1875 {
1876  DPRINTF(UFSHostDevice, "Write transaction Start: 0x%8x; Size: %d\n",
1877  start, size);
1878 
1880  if (toDisk) {
1881  ++writePendingNum;
1882 
1883  while (!writeDoneEvent.empty() && (writeDoneEvent.front().when()
1884  < curTick()))
1885  writeDoneEvent.pop_front();
1886 
1887  writeDoneEvent.push_back(
1888  EventFunctionWrapper([this]{ writeDone(); },
1889  name()));
1890  assert(!writeDoneEvent.back().scheduled());
1891 
1893  struct transferInfo new_transfer;
1894  new_transfer.offset = SCSIDiskOffset;
1895  new_transfer.size = size;
1896  new_transfer.lunID = lun_id;
1897  new_transfer.filePointer = 0;
1898  SSDWriteinfo.push_back(new_transfer);
1899 
1901  SSDWriteinfo.back().buffer.resize(size);
1902 
1904  dmaPort.dmaAction(MemCmd::ReadReq, start, size,
1905  &writeDoneEvent.back(),
1906  &SSDWriteinfo.back().buffer[0], 0);
1907  //yes, a readreq at a write device function is correct.
1908  DPRINTF(UFSHostDevice, "Write to disk scheduled\n");
1909 
1910  } else {
1911  assert(!additional_action->scheduled());
1912  dmaPort.dmaAction(MemCmd::ReadReq, start, size,
1913  additional_action, destination, 0);
1914  DPRINTF(UFSHostDevice, "Write scheduled\n");
1915  }
1916 }
1917 
1923 void
1924 UFSHostDevice::manageWriteTransfer(uint8_t LUN, uint64_t offset, uint32_t
1925  sg_table_length, struct UFSHCDSGEntry*
1926  sglist)
1927 {
1928  struct writeToDiskBurst next_packet;
1929 
1930  next_packet.SCSIDiskOffset = offset;
1931 
1932  UFSDevice[LUN]->setTotalWrite(sg_table_length);
1933 
1938  for (uint32_t count = 0; count < sg_table_length; count++) {
1939  next_packet.start = sglist[count].upperAddr;
1940  next_packet.start = (next_packet.start << 32) |
1941  (sglist[count].baseAddr & 0xFFFFFFFF);
1942  next_packet.LUN = LUN;
1943  DPRINTF(UFSHostDevice, "Write data DMA start: 0x%8x\n",
1944  next_packet.start);
1945  DPRINTF(UFSHostDevice, "Write data DMA size: 0x%8x\n",
1946  (sglist[count].size + 1));
1947  assert(sglist[count].size > 0);
1948 
1949  if (count != 0)
1950  next_packet.SCSIDiskOffset = next_packet.SCSIDiskOffset +
1951  (sglist[count - 1].size + 1);
1952 
1953  next_packet.size = sglist[count].size + 1;
1954 
1956  if (dmaWriteInfo.empty())
1957  writeDevice(NULL, true, next_packet.start, next_packet.size,
1958  NULL, next_packet.SCSIDiskOffset, next_packet.LUN);
1959  else
1960  DPRINTF(UFSHostDevice, "Write not initiated queue: %d\n",
1961  dmaWriteInfo.size());
1962 
1963  dmaWriteInfo.push_back(next_packet);
1964  DPRINTF(UFSHostDevice, "Write Location: 0x%8x\n",
1965  next_packet.SCSIDiskOffset);
1966 
1967  DPRINTF(UFSHostDevice, "Write transfer #: 0x%8x\n", count + 1);
1968 
1970  stats.totalWrittenSSD += (sglist[count].size + 1);
1971  }
1972 
1974  ++stats.totalWriteUFSTransactions;
1975 }
1976 
1982 void
1983 UFSHostDevice::writeDone()
1984 {
1986  assert(dmaWriteInfo.size() > 0);
1987  dmaWriteInfo.pop_front();
1988  assert(SSDWriteinfo.size() > 0);
1989  uint32_t lun = SSDWriteinfo.front().lunID;
1990 
1992  DPRINTF(UFSHostDevice, "Write done entered, queue: %d\n",
1993  UFSDevice[lun]->SSDWriteDoneInfo.size());
1995  UFSDevice[lun]->writeFlash(&SSDWriteinfo.front().buffer[0],
1996  SSDWriteinfo.front().offset,
1997  SSDWriteinfo.front().size);
1998 
2004  UFSDevice[lun]->SSDWriteDoneInfo.push_back(SSDWriteinfo.front());
2005  SSDWriteinfo.pop_front();
2006 
2007  --writePendingNum;
2009  UFSDevice[lun]->SSDWriteStart();
2010 
2012  stats.currentWriteSSDQueue = UFSDevice[lun]->SSDWriteDoneInfo.size();
2013  stats.averageWriteSSDQueue = UFSDevice[lun]->SSDWriteDoneInfo.size();
2014  ++stats.totalWriteDiskTransactions;
2015 
2017  if (!dmaWriteInfo.empty())
2018  writeDevice(NULL, true, dmaWriteInfo.front().start,
2019  dmaWriteInfo.front().size, NULL,
2020  dmaWriteInfo.front().SCSIDiskOffset,
2021  dmaWriteInfo.front().LUN);
2022  DPRINTF(UFSHostDevice, "Write done end\n");
2023 }
2024 
2028 void
2029 UFSHostDevice::UFSSCSIDevice::SSDWriteStart()
2030 {
2031  assert(SSDWriteDoneInfo.size() > 0);
2032  flashDevice->writeMemory(
2033  SSDWriteDoneInfo.front().offset,
2034  SSDWriteDoneInfo.front().size, memWriteCallback);
2035 
2036  SSDWriteDoneInfo.pop_front();
2037 
2038  DPRINTF(UFSHostDevice, "Write is started; left in queue: %d\n",
2039  SSDWriteDoneInfo.size());
2040 }
2041 
2042 
2047 void
2048 UFSHostDevice::UFSSCSIDevice::SSDWriteDone()
2049 {
2050  DPRINTF(UFSHostDevice, "Write disk, aiming for %d messages, %d so far\n",
2051  totalWrite, amountOfWriteTransfers);
2052 
2053  //we have done one extra transfer
2054  ++amountOfWriteTransfers;
2055 
2057  assert(totalWrite >= amountOfWriteTransfers && totalWrite != 0);
2058 
2060  if (totalWrite == amountOfWriteTransfers) {
2061  DPRINTF(UFSHostDevice, "Write transactions finished\n");
2062  totalWrite = 0;
2063  amountOfWriteTransfers = 0;
2064 
2065  //Callback UFS Host
2066  setSignal();
2067  signalDone();
2068  }
2069 
2070 }
2071 
2077 void
2078 UFSHostDevice::readDevice(bool lastTransfer, Addr start, uint32_t size,
2079  uint8_t* destination, bool no_cache, Event*
2080  additional_action)
2081 {
2082  DPRINTF(UFSHostDevice, "Read start: 0x%8x; Size: %d, data[0]: 0x%8x\n",
2083  start, size, (reinterpret_cast<uint32_t *>(destination))[0]);
2084 
2086  if (lastTransfer) {
2087  ++readPendingNum;
2088  readDoneEvent.push_back(
2089  EventFunctionWrapper([this]{ readDone(); },
2090  name()));
2091  assert(!readDoneEvent.back().scheduled());
2092  dmaPort.dmaAction(MemCmd::WriteReq, start, size,
2093  &readDoneEvent.back(), destination, 0);
2094  //yes, a writereq at a read device function is correct.
2095 
2096  } else {
2097  if (additional_action != NULL)
2098  assert(!additional_action->scheduled());
2099 
2100  dmaPort.dmaAction(MemCmd::WriteReq, start, size,
2101  additional_action, destination, 0);
2102 
2103  }
2104 
2105 }
2106 
2112 void
2113 UFSHostDevice::manageReadTransfer(uint32_t size, uint32_t LUN, uint64_t
2114  offset, uint32_t sg_table_length,
2115  struct UFSHCDSGEntry* sglist)
2116 {
2117  uint32_t size_accum = 0;
2118 
2119  DPRINTF(UFSHostDevice, "Data READ size: %d\n", size);
2120 
2125  for (uint32_t count = 0; count < sg_table_length; count++) {
2126  struct transferInfo new_transfer;
2127  new_transfer.offset = sglist[count].upperAddr;
2128  new_transfer.offset = (new_transfer.offset << 32) |
2129  (sglist[count].baseAddr & 0xFFFFFFFF);
2130  new_transfer.filePointer = offset + size_accum;
2131  new_transfer.size = (sglist[count].size + 1);
2132  new_transfer.lunID = LUN;
2133 
2134  DPRINTF(UFSHostDevice, "Data READ start: 0x%8x; size: %d\n",
2135  new_transfer.offset, new_transfer.size);
2136 
2137  UFSDevice[LUN]->SSDReadInfo.push_back(new_transfer);
2138  UFSDevice[LUN]->SSDReadInfo.back().buffer.resize(sglist[count].size
2139  + 1);
2140 
2146  UFSDevice[LUN]->readFlash(&UFSDevice[LUN]->
2147  SSDReadInfo.back().buffer[0],
2148  offset + size_accum,
2149  sglist[count].size + 1);
2150 
2151  size_accum += (sglist[count].size + 1);
2152 
2153  DPRINTF(UFSHostDevice, "Transfer %d; Remaining: 0x%8x, Accumulated:"
2154  " 0x%8x\n", (count + 1), (size-size_accum), size_accum);
2155 
2157  stats.totalReadSSD += (sglist[count].size + 1);
2158  stats.currentReadSSDQueue = UFSDevice[LUN]->SSDReadInfo.size();
2159  stats.averageReadSSDQueue = UFSDevice[LUN]->SSDReadInfo.size();
2160  }
2161 
2162  UFSDevice[LUN]->SSDReadStart(sg_table_length);
2163 
2165  ++stats.totalReadUFSTransactions;
2166 
2167 }
2168 
2169 
2170 
2177 void
2178 UFSHostDevice::UFSSCSIDevice::SSDReadStart(uint32_t total_read)
2179 {
2180  totalRead = total_read;
2181  for (uint32_t number_handled = 0; number_handled < SSDReadInfo.size();
2182  number_handled++) {
2187  flashDevice->readMemory(SSDReadInfo.front().filePointer,
2188  SSDReadInfo.front().size, memReadCallback);
2189  }
2190 
2191 }
2192 
2193 
2198 void
2199 UFSHostDevice::UFSSCSIDevice::SSDReadDone()
2200 {
2201  DPRINTF(UFSHostDevice, "SSD read done at lun %d, Aiming for %d messages,"
2202  " %d so far\n", lunID, totalRead, amountOfReadTransfers);
2203 
2204  if (totalRead == amountOfReadTransfers) {
2205  totalRead = 0;
2206  amountOfReadTransfers = 0;
2207 
2209  setSignal();
2210  signalDone();
2211  }
2212 
2213 }
2214 
2219 void
2220 UFSHostDevice::UFSSCSIDevice::readCallback()
2221 {
2222  ++amountOfReadTransfers;
2223 
2227  setReadSignal();
2228  deviceReadCallback();
2229 
2230  //Are we done yet?
2231  SSDReadDone();
2232 }
2233 
2239 void
2240 UFSHostDevice::readCallback()
2241 {
2242  DPRINTF(UFSHostDevice, "Read Callback\n");
2243  uint8_t this_lun = 0;
2244 
2245  //while we haven't found the right lun, keep searching
2246  while ((this_lun < lunAvail) && !UFSDevice[this_lun]->finishedRead())
2247  ++this_lun;
2248 
2249  DPRINTF(UFSHostDevice, "Found LUN %d messages pending for clean: %d\n",
2250  this_lun, SSDReadPending.size());
2251 
2252  if (this_lun < lunAvail) {
2253  //Clear signal.
2254  UFSDevice[this_lun]->clearReadSignal();
2255  SSDReadPending.push_back(UFSDevice[this_lun]->SSDReadInfo.front());
2256  UFSDevice[this_lun]->SSDReadInfo.pop_front();
2257  readGarbageEventQueue.push_back(
2258  EventFunctionWrapper([this]{ readGarbage(); }, name()));
2259 
2260  //make sure the queue is popped a the end of the dma transaction
2261  readDevice(false, SSDReadPending.front().offset,
2262  SSDReadPending.front().size,
2263  &SSDReadPending.front().buffer[0], false,
2264  &readGarbageEventQueue.back());
2265 
2267  ++stats.totalReadDiskTransactions;
2268  }
2269  else
2270  panic("no read finished in tick %d\n", curTick());
2271 }
2272 
2277 void
2278 UFSHostDevice::readGarbage()
2279 {
2280  DPRINTF(UFSHostDevice, "Clean read data, %d\n", SSDReadPending.size());
2281  SSDReadPending.pop_front();
2282  readGarbageEventQueue.pop_front();
2283 }
2284 
2289 void
2290 UFSHostDevice::serialize(CheckpointOut &cp) const
2291 {
2292  DmaDevice::serialize(cp);
2293 
2294  const uint8_t* temp_HCI_mem = reinterpret_cast<const uint8_t*>(&UFSHCIMem);
2295  SERIALIZE_ARRAY(temp_HCI_mem, sizeof(HCIMem));
2296 
2297  uint32_t lun_avail = lunAvail;
2298  SERIALIZE_SCALAR(lun_avail);
2299 }
2300 
2301 
2306 void
2307 UFSHostDevice::unserialize(CheckpointIn &cp)
2308 {
2309  DmaDevice::unserialize(cp);
2310  uint8_t* temp_HCI_mem = reinterpret_cast<uint8_t*>(&UFSHCIMem);
2311  UNSERIALIZE_ARRAY(temp_HCI_mem, sizeof(HCIMem));
2312 
2313  uint32_t lun_avail;
2314  UNSERIALIZE_SCALAR(lun_avail);
2315  assert(lunAvail == lun_avail);
2316 }
2317 
2318 
2323 DrainState
2324 UFSHostDevice::drain()
2325 {
2326  if (UFSHCIMem.TRUTRLDBR) {
2327  DPRINTF(UFSHostDevice, "UFSDevice is draining...\n");
2328  return DrainState::Draining;
2329  } else {
2330  DPRINTF(UFSHostDevice, "UFSDevice drained\n");
2331  return DrainState::Drained;
2332  }
2333 }
2334 
2339 void
2340 UFSHostDevice::checkDrain()
2341 {
2342  if (drainState() != DrainState::Draining)
2343  return;
2344 
2345  if (UFSHCIMem.TRUTRLDBR) {
2346  DPRINTF(UFSHostDevice, "UFSDevice is still draining; with %d active"
2347  " doorbells\n", activeDoorbells);
2348  } else {
2349  DPRINTF(UFSHostDevice, "UFSDevice is done draining\n");
2350  signalDrainDone();
2351  }
2352 }
UFSHostDevice::setValues
void setValues()
Initialization function.
Definition: ufs_device.cc:881
UFSHostDevice::UFSHostDeviceStats::totalWriteUFSTransactions
Stats::Scalar totalWriteUFSTransactions
Definition: ufs_device.hh:510
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:183
UFSHostDevice::HCIMem::TRUTRLDBR
uint32_t TRUTRLDBR
Definition: ufs_device.hh:221
UFSHostDevice::readDevice
void readDevice(bool lastTransfer, Addr SCSIStart, uint32_t SCSISize, uint8_t *SCSIDestination, bool no_cache, Event *additional_action)
Dma transaction function: read device.
Definition: ufs_device.cc:2078
UFSHostDevice::transferStart::size
uint32_t size
Definition: ufs_device.hh:455
ArmISA::status
Bitfield< 5, 0 > status
Definition: miscregs_types.hh:417
UFSHostDevice::LUNInfo::vendor0
uint32_t vendor0
Definition: ufs_device.hh:397
UFSHostDevice::HCIMem
Host Controller Interface This is a set of registers that allow the driver to control the transaction...
Definition: ufs_device.hh:188
UFSHostDevice::UFSSCSIDevice::SCSICMDHandle
struct SCSIReply SCSICMDHandle(uint32_t *SCSI_msg)
SCSI command handle function; determines what the command is and returns a reply structure that allow...
Definition: ufs_device.cc:157
Stats::Group::regStats
virtual void regStats()
Callback to set stat parameters.
Definition: group.cc:64
Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:460
UFSHostDevice::regControllerCapabilities
@ regControllerCapabilities
Definition: ufs_device.hh:1184
UFSHostDevice::transferStart::destination
struct UTPTransferReqDesc * destination
Definition: ufs_device.hh:452
UFSHostDevice::writeToDiskBurst
Disk transfer burst information.
Definition: ufs_device.hh:488
UFSHostDevice::gic
BaseGic * gic
Definition: ufs_device.hh:1005
warn
#define warn(...)
Definition: logging.hh:239
length
uint8_t length
Definition: inet.hh:422
UFSHostDevice::regUTPTaskREQListClear
@ regUTPTaskREQListClear
Definition: ufs_device.hh:1206
UFSHostDevice::commandHandler
void commandHandler()
Command handler function.
Definition: ufs_device.cc:1376
UFSHostDevice::SSDReadPending
std::deque< struct transferInfo > SSDReadPending
Information from the Disk, waiting to be pushed to the DMA.
Definition: ufs_device.hh:1116
UFSHostDevice::transferInfo
Different events, and scenarios require different types of information.
Definition: ufs_device.hh:425
data
const char data[]
Definition: circlebuf.test.cc:42
UFSHostDevice::LUNInfo::dWord1
uint32_t dWord1
Definition: ufs_device.hh:396
UFSHostDevice::transferStart
void transferStart()
Transfer Start function.
Definition: ufs_device.cc:1356
UFSHostDevice::SCSIResumeInfo::finalSize
uint32_t finalSize
Definition: ufs_device.hh:479
UFSHostDevice::intNum
const int intNum
Definition: ufs_device.hh:1004
UFSHostDevice::UTPUPIUHeader::dWord0
uint32_t dWord0
Definition: ufs_device.hh:257
UFSHostDevice::UFSSCSIDevice::UFSSCSIDevice
UFSSCSIDevice(const UFSHostDeviceParams *p, uint32_t lun_id, const Callback &transfer_cb, const Callback &read_cb)
Constructor and destructor.
Definition: ufs_device.cc:75
UFSHostDevice::UFSSCSIDevice::readFlash
void readFlash(uint8_t *readaddr, uint64_t offset, uint32_t size)
Disk access functions.
Definition: ufs_device.cc:688
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:797
Packet::getAddr
Addr getAddr() const
Definition: packet.hh:754
UFSHostDevice::UFSHCDSGEntry
struct UFSHCDSGEntry - UFSHCI PRD Entry baseAddr: Lower 32bit physical address DW-0 upperAddr: Upper ...
Definition: ufs_device.hh:301
UFSHostDevice::regUICCommand
@ regUICCommand
Definition: ufs_device.hh:1208
UFSHostDevice::SCSIResumeInfo::finalAddress
Addr finalAddress
Definition: ufs_device.hh:478
UFSHostDevice::SCSIResumeInfo::done
uint32_t done
Definition: ufs_device.hh:481
UFSHostDevice::pendingDoorbells
uint8_t pendingDoorbells
Definition: ufs_device.hh:1030
UFSHostDevice::UFSSCSIDevice::SSDWriteStart
void SSDWriteStart()
SSD write start.
Definition: ufs_device.cc:2029
UFSHostDevice::UFSSCSIDevice::memWriteCallback
Callback memWriteCallback
Definition: ufs_device.hh:735
UFSHostDevice::regUTPTaskREQListRunStop
@ regUTPTaskREQListRunStop
Definition: ufs_device.hh:1207
UFSHostDevice::HCIMem::TRUTRLCLR
uint32_t TRUTRLCLR
Definition: ufs_device.hh:222
SectorSize
#define SectorSize
Definition: disk_image.hh:44
UFSHostDevice::UFSHostDeviceStats::transactionLatency
Stats::Histogram transactionLatency
Histogram of latencies.
Definition: ufs_device.hh:527
UFSHostDevice::writeToDiskBurst::SCSIDiskOffset
uint64_t SCSIDiskOffset
Definition: ufs_device.hh:490
ClockedObject::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: clocked_object.cc:56
UFSHostDevice::HCIMem::ORInterruptStatus
uint32_t ORInterruptStatus
Operation and runtime registers.
Definition: ufs_device.hh:200
UFSHostDevice::HCIMem::ORHostControllerStatus
uint32_t ORHostControllerStatus
Definition: ufs_device.hh:202
UFSHostDevice::transferStartInfo
std::deque< struct transferStart > transferStartInfo
Definition: ufs_device.hh:1101
UFSHostDevice::UFSSCSIDevice::SSDReadStart
void SSDReadStart(uint32_t total_read)
Start the transactions to (and from) the disk The host will queue all the transactions.
Definition: ufs_device.cc:2178
UFSHostDevice::UFSDevice
std::vector< UFSSCSIDevice * > UFSDevice
logic units connected to the UFS Host device Note again that the "device" as such is represented by o...
Definition: ufs_device.hh:1065
UFSHostDevice::regUTPTaskREQListBaseH
@ regUTPTaskREQListBaseH
Definition: ufs_device.hh:1204
UFSHostDevice::UFSSCSIDevice::signalDone
Callback signalDone
Callbacks between Host and Device.
Definition: ufs_device.hh:728
MemCmd::ReadReq
@ ReadReq
Definition: packet.hh:82
UFSHostDevice::HCIMem::ORUECPA
uint32_t ORUECPA
Definition: ufs_device.hh:204
UFSHostDevice::HCIMem::ORUECDME
uint32_t ORUECDME
Definition: ufs_device.hh:208
Tick
uint64_t Tick
Tick count type.
Definition: types.hh:63
UFSHostDevice::UTPTransferREQCOMPL
static const unsigned int UTPTransferREQCOMPL
Bits of interest within UFS data packages.
Definition: ufs_device.hh:1173
UFSHostDevice::HCIMem::CMDUCMDARG2
uint32_t CMDUCMDARG2
Definition: ufs_device.hh:239
UFSHostDevice::UFSHCIMem
HCIMem UFSHCIMem
Host controller memory.
Definition: ufs_device.hh:1012
UFSHostDevice::regUTPTaskREQDoorbell
@ regUTPTaskREQDoorbell
Definition: ufs_device.hh:1205
UFSHostDevice::HCIMem::ORUECT
uint32_t ORUECT
Definition: ufs_device.hh:207
UFSHostDevice::UFSSCSIDevice::SSDReadDone
void SSDReadDone()
SSD Read done; Determines if the final callback of the transaction should be made at the end of a rea...
Definition: ufs_device.cc:2199
UFSHostDevice::readCallback
void readCallback()
Read callback Call back function for the logic units to indicate the completion of a read action.
Definition: ufs_device.cc:2240
UFSHostDevice::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize; needed to restore from checkpoints.
Definition: ufs_device.cc:2307
UFSHostDevice::pioSize
const Addr pioSize
Definition: ufs_device.hh:1002
UFSHostDevice::UICCommandCOMPL
static const unsigned int UICCommandCOMPL
Definition: ufs_device.hh:1175
UFSHostDevice::HCIMem::ORHostControllerEnable
uint32_t ORHostControllerEnable
Definition: ufs_device.hh:203
UFSHostDevice::UFSHostDeviceStats::totalReadSSD
Stats::Scalar totalReadSSD
Amount of data read/written.
Definition: ufs_device.hh:505
UFSHostDevice::drain
DrainState drain() override
Drain; needed to enable checkpoints.
Definition: ufs_device.cc:2324
Packet::getSize
unsigned getSize() const
Definition: packet.hh:764
X86ISA::count
count
Definition: misc.hh:703
UFSHostDevice::writeToDiskBurst::LUN
uint32_t LUN
Definition: ufs_device.hh:492
UFSHostDevice::SSDWriteinfo
std::deque< struct transferInfo > SSDWriteinfo
Information from DMA transaction to disk.
Definition: ufs_device.hh:1111
UFSHostDevice::UFSHostDeviceStats::maxDoorbell
Stats::Scalar maxDoorbell
Definition: ufs_device.hh:523
UFSHostDevice::transferEventQueue
std::deque< EventFunctionWrapper > transferEventQueue
Definition: ufs_device.hh:1168
UFSHostDevice::regUICErrorCodeDME
@ regUICErrorCodeDME
Definition: ufs_device.hh:1196
UFSHostDevice::writeDevice
void writeDevice(Event *additional_action, bool toDisk, Addr start, int size, uint8_t *destination, uint64_t SCSIDiskOffset, uint32_t lun_id)
DMA transfer functions These allow the host to push/pull the data to the memory The provided event in...
Definition: ufs_device.cc:1872
UFSHostDevice::idlePhaseStart
Tick idlePhaseStart
Definition: ufs_device.hh:1058
UFSHostDevice::SCSIStart
void SCSIStart()
Transfer SCSI function.
Definition: ufs_device.cc:1469
UFSHostDevice::UFSSCSIDevice::~UFSSCSIDevice
~UFSSCSIDevice()
Definition: ufs_device.cc:143
UFSHostDevice::writePendingNum
int writePendingNum
Definition: ufs_device.hh:1018
Stats::none
const FlagsType none
Nothing extra to print.
Definition: info.hh:43
UFSHostDevice::readGarbage
void readGarbage()
Read garbage A read from disk data structure can vary in size and is therefor allocated on creation.
Definition: ufs_device.cc:2278
UFSHostDevice::HCIMem::TRUTRLBA
uint32_t TRUTRLBA
Transfer control registers.
Definition: ufs_device.hh:219
UFSHostDevice::UTPUPIUHeader::dWord2
uint32_t dWord2
Definition: ufs_device.hh:259
UFSHostDevice::SCSIResumeInfo::RequestIn
struct UTPTransferReqDesc * RequestIn
Definition: ufs_device.hh:476
UFSHostDevice::writeDoneEvent
std::deque< EventFunctionWrapper > writeDoneEvent
Definition: ufs_device.hh:1138
UFSHostDevice::taskStart::address
Addr address
Definition: ufs_device.hh:466
UFSHostDevice::regControllerEnable
@ regControllerEnable
Definition: ufs_device.hh:1191
UFSHostDevice::readDoneEvent
std::deque< EventFunctionWrapper > readDoneEvent
Transfer flow events Basically these events form two queues, one from memory to UFS device (DMA) and ...
Definition: ufs_device.hh:1137
UFSHostDevice::SCSIReply::message
struct UPIUMessage message
Definition: ufs_device.hh:382
EventFunctionWrapper
Definition: eventq.hh:1101
UFSHostDevice::taskHandler
void taskHandler(struct UTPUPIUTaskReq *request_in, uint32_t req_pos, Addr finaladdress, uint32_t finalsize)
Task handler function.
Definition: ufs_device.cc:1390
UFSHostDevice::HCIMem::HCCAP
uint32_t HCCAP
Specify the host capabilities.
Definition: ufs_device.hh:192
Stats::DataWrap::flags
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
Definition: statistics.hh:331
DrainState::Drained
@ Drained
Buffers drained, ready for serialization/handover.
UFSHostDevice::regUICErrorCodePHYAdapterLayer
@ regUICErrorCodePHYAdapterLayer
Definition: ufs_device.hh:1192
DmaDevice::dmaPort
DmaPort dmaPort
Definition: dma_device.hh:168
UFSHostDevice::SCSIReply::expectMore
uint8_t expectMore
Definition: ufs_device.hh:384
UFSHostDevice::writeToDiskBurst::size
uint32_t size
Definition: ufs_device.hh:491
MemCmd::WriteReq
@ WriteReq
Definition: packet.hh:85
UFSHostDevice::HCIMem::TMUTMRLDBR
uint32_t TMUTMRLDBR
Definition: ufs_device.hh:230
DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:71
UFSHostDevice::UFSHostDeviceStats::averageSCSIQueue
Stats::Average averageSCSIQueue
Average Queue lengths.
Definition: ufs_device.hh:517
UFSHostDevice::UTPUPIURSP
struct UTPUPIURSP - Response UPIU structure header: UPIU header DW-0 to DW-2 residualTransferCount: R...
Definition: ufs_device.hh:270
UFSHostDevice::UFSSCSIDevice::SSDWriteDone
void SSDWriteDone()
SSD Write Done; This is the callback function for the memory model.
Definition: ufs_device.cc:2048
cp
Definition: cprintf.cc:40
UFSHostDevice::countInt
uint32_t countInt
interrupt verification This keeps track of the number of interrupts generated.
Definition: ufs_device.hh:1039
UFSHostDevice::UTPUPIUTaskReq
struct UTPUPIUTaskReq - Task request UPIU structure header - UPIU header structure DW0 to DW-2 inputP...
Definition: ufs_device.hh:286
UFSHostDevice::UFSHostDeviceStats::idleTimes
Stats::Histogram idleTimes
Definition: ufs_device.hh:528
UFSHostDevice::transferStart::done
uint32_t done
Definition: ufs_device.hh:456
UFSHostDevice::serialize
void serialize(CheckpointOut &cp) const override
Serialize; needed to make checkpoints.
Definition: ufs_device.cc:2290
UFSHostDevice::SCSIReply::LUN
uint8_t LUN
Definition: ufs_device.hh:381
UFSHostDevice::HCIMem::TMUTMRLBAU
uint32_t TMUTMRLBAU
Definition: ufs_device.hh:229
UFSHostDevice::UFSHostDeviceStats::averageReadSSDQueue
Stats::Average averageReadSSDQueue
Definition: ufs_device.hh:518
UFSHostDevice::LUNInfo::product0
uint32_t product0
Definition: ufs_device.hh:399
Stats::ScalarBase::value
Counter value() const
Return the current value of this stat as its base type.
Definition: statistics.hh:698
UFSHostDevice::UFSHostDeviceStats::averageWriteSSDQueue
Stats::Average averageWriteSSDQueue
Definition: ufs_device.hh:519
UFSHostDevice::UFSSCSIDevice::deviceReadCallback
Callback deviceReadCallback
Definition: ufs_device.hh:729
UFSHostDevice::UFSHostDeviceStats::currentSCSIQueue
Stats::Scalar currentSCSIQueue
Queue lengths.
Definition: ufs_device.hh:500
Event
Definition: eventq.hh:246
UFSHostDevice::writeDone
void writeDone()
Write done After a DMA write with data intended for the disk, this function is called.
Definition: ufs_device.cc:1983
UFSHostDevice::UTPTransferReqDesc::responseUPIULength
uint16_t responseUPIULength
Definition: ufs_device.hh:362
UFSHostDevice::taskStart
void taskStart()
Task Start function.
Definition: ufs_device.cc:1342
UFSHostDevice::requestHandler
void requestHandler()
Handler functions.
Definition: ufs_device.cc:1223
UFSHostDevice::request_out_datain
struct SCSIReply request_out_datain
SCSI reply structure, used for direct answering.
Definition: ufs_device.hh:1072
UFSHostDevice::checkDrain
void checkDrain()
Checkdrain; needed to enable checkpoints.
Definition: ufs_device.cc:2340
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
UFSHostDevice::UFSSCSIDevice::readCallback
void readCallback()
Functions to indicate that the action to the SSD has completed.
Definition: ufs_device.cc:2220
simSeconds
Stats::Formula simSeconds
Definition: stat_control.cc:61
UFSHostDevice::HCIMem::CMDUCMDARG3
uint32_t CMDUCMDARG3
Definition: ufs_device.hh:240
UFSHostDevice::UTPTransferReqDesc::commandDescBaseAddrHi
uint32_t commandDescBaseAddrHi
Definition: ufs_device.hh:359
UFSHostDevice::UFSSCSIDevice::lunID
const uint32_t lunID
Definition: ufs_device.hh:703
UFSHostDevice::UFSSCSIDevice::memReadCallback
Callback memReadCallback
Callbacks between Device and Memory.
Definition: ufs_device.hh:734
UFSHostDevice::regUICErrorCodeDataLinkLayer
@ regUICErrorCodeDataLinkLayer
Definition: ufs_device.hh:1193
UFSHostDevice::UFSSCSIDevice::recoveryPage
static const unsigned int recoveryPage[3]
Definition: ufs_device.hh:752
UFSHostDevice::LUNInfo::product1
uint32_t product1
Definition: ufs_device.hh:400
UFSHostDevice::UFSSCSIDevice::diskSize
const uint64_t diskSize
Definition: ufs_device.hh:694
UFSHostDevice::SCSIReply
SCSI reply structure.
Definition: ufs_device.hh:374
UFSHostDevice::HCIMem::TRUTRLRSR
uint32_t TRUTRLRSR
Definition: ufs_device.hh:223
UFSHostDevice::activeDoorbells
uint8_t activeDoorbells
Statistics helper variables Active doorbells indicates how many doorbells are in teh process of being...
Definition: ufs_device.hh:1029
UFSHostDevice::SCSIReply::status
uint8_t status
Definition: ufs_device.hh:379
UFSHostDevice::UPIUMessage::header
struct UTPUPIUHeader header
Definition: ufs_device.hh:325
UFSHostDevice::HCIMem::ORInterruptEnable
uint32_t ORInterruptEnable
Definition: ufs_device.hh:201
UFSHostDevice::dmaWriteInfo
std::deque< struct writeToDiskBurst > dmaWriteInfo
Information to get a DMA transaction.
Definition: ufs_device.hh:1106
UFSHostDevice
UFS command flow state machine digraph CommandFlow{ node [fontsize=10]; IDLE -> transferHandler [ lab...
Definition: ufs_device.hh:169
UFSHostDevice::lunAvail
const uint32_t lunAvail
Definition: ufs_device.hh:1006
RangeSize
AddrRange RangeSize(Addr start, Addr size)
Definition: addr_range.hh:638
UFSHostDevice::UFSHostDeviceStats::averageWriteSSDBW
Stats::Formula averageWriteSSDBW
Definition: ufs_device.hh:514
UFSHostDevice::UTPTransferReqDesc::PRDTableOffset
uint16_t PRDTableOffset
Definition: ufs_device.hh:367
UFSHostDevice::UFSSCSIDevice::statusCheck
void statusCheck(uint8_t status, uint8_t *sensecodelist)
Status of SCSI.
Definition: ufs_device.cc:671
UFSHostDevice::regUTPTransferREQListRunStop
@ regUTPTransferREQListRunStop
Definition: ufs_device.hh:1202
UFSHostDevice::UTPTransferReqDesc::RequestDescHeader::dWord0
uint32_t dWord0
Definition: ufs_device.hh:351
Drainable::signalDrainDone
void signalDrainDone() const
Signal that an object is drained.
Definition: drain.hh:301
UFSHostDevice::transferTrack
uint32_t transferTrack
Track the transfer This is allows the driver to "group" certain transfers together by using a tag in ...
Definition: ufs_device.hh:1049
UFSHostDevice::UFSHostDeviceStats::totalReadUFSTransactions
Stats::Scalar totalReadUFSTransactions
Definition: ufs_device.hh:509
UFSHostDevice::HCIMem::TMUTMRLRSR
uint32_t TMUTMRLRSR
Definition: ufs_device.hh:232
SERIALIZE_ARRAY
#define SERIALIZE_ARRAY(member, size)
Definition: serialize.hh:832
UFSHostDevice::taskEventQueue
std::deque< EventFunctionWrapper > taskEventQueue
Multiple tasks transfers can be scheduled at once for the device, the only thing we know for sure abo...
Definition: ufs_device.hh:1167
UFSHostDevice::UFSHostDeviceStats::averageReadSSDBW
Stats::Formula averageReadSSDBW
Average bandwidth for reads and writes.
Definition: ufs_device.hh:513
UFSHostDevice::regInterruptEnable
@ regInterruptEnable
Definition: ufs_device.hh:1189
UFSHostDevice::SCSIReply::reset
void reset()
Definition: ufs_device.hh:375
UFSHostDevice::getAddrRanges
AddrRangeList getAddrRanges() const override
Address range functions.
Definition: ufs_device.cc:908
UFSHostDevice::taskInfo
std::deque< struct taskStart > taskInfo
When a task/transfer is started it needs information about the task/transfer it is about to perform.
Definition: ufs_device.hh:1100
UFSHostDevice::transferStart::address
Addr address
Definition: ufs_device.hh:454
UFSHostDevice::regUICCommandArg1
@ regUICCommandArg1
Definition: ufs_device.hh:1209
UFSHostDevice::transferStart
Transfer start information.
Definition: ufs_device.hh:451
UFSHostDevice::taskStart::done
bool done
Definition: ufs_device.hh:468
UFSHostDevice::taskStart::mask
uint32_t mask
Definition: ufs_device.hh:465
UFSHostDevice::taskStart::size
uint32_t size
Definition: ufs_device.hh:467
UFSHostDevice::readDone
void readDone()
Read done Started at the end of a transaction after the last read action.
Definition: ufs_device.cc:1783
UFSHostDevice::finalUTP
void finalUTP()
final UTP, sends the last acknowledge data structure to the system; prepares the clean up functions.
Definition: ufs_device.cc:1737
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
betoh
T betoh(T value)
Definition: byteswap.hh:143
UFSHostDevice::regUTPTaskREQListBaseL
@ regUTPTaskREQListBaseL
Definition: ufs_device.hh:1203
UFSHostDevice::regUTPTransferREQDoorbell
@ regUTPTransferREQDoorbell
Definition: ufs_device.hh:1200
Packet::makeResponse
void makeResponse()
Take a request packet and modify it in place to be suitable for returning as a response to that reque...
Definition: packet.hh:1004
UFSHostDevice::transactionStart
Tick transactionStart[32]
Helper for latency stats These variables keep track of the latency for every doorbell.
Definition: ufs_device.hh:1057
Stats::DataWrap::name
Derived & name(const std::string &name)
Set the name and marks this stat to print at the end of simulation.
Definition: statistics.hh:274
UFSHostDevice::UFSHCDSGEntry::size
uint32_t size
Definition: ufs_device.hh:305
UFSHostDevice::HCIMem::HCversion
uint32_t HCversion
Definition: ufs_device.hh:193
UFSHostDevice::UFSSCSIDevice::lunInfo
struct LUNInfo lunInfo
Logic unit info; needed for SCSI Info messages and LU identification.
Definition: ufs_device.hh:702
UFSHostDevice::UFSHostDeviceStats::currentReadSSDQueue
Stats::Scalar currentReadSSDQueue
Definition: ufs_device.hh:501
name
const std::string & name()
Definition: trace.cc:50
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:790
UFSHostDevice::pioDelay
const Tick pioDelay
Definition: ufs_device.hh:1003
UFSHostDevice::UFSSCSIDevice::controlPage
static const unsigned int controlPage[3]
These pages are SCSI specific.
Definition: ufs_device.hh:751
DmaPort::dmaAction
RequestPtr dmaAction(Packet::Command cmd, Addr addr, int size, Event *event, uint8_t *data, Tick delay, Request::Flags flag=0)
Definition: dma_device.cc:197
UFSHostDevice::transferInfo::offset
uint64_t offset
Definition: ufs_device.hh:428
UFSHostDevice::UTPTransferReqDesc::PRDTableLength
uint16_t PRDTableLength
Definition: ufs_device.hh:366
UFSHostDevice::UTPEvent
EventFunctionWrapper UTPEvent
Wait for the moment where we can send the last frame.
Definition: ufs_device.hh:1155
UFSHostDevice::manageWriteTransfer
void manageWriteTransfer(uint8_t LUN, uint64_t offset, uint32_t sg_table_length, struct UFSHCDSGEntry *sglist)
Disk transfer management functions these set up the queues, and initiated them, leading to the data t...
Definition: ufs_device.cc:1924
UFSHostDevice::readPendingNum
int readPendingNum
Track number of DMA transactions in progress.
Definition: ufs_device.hh:1017
Stats::nozero
const FlagsType nozero
Don't print if this is zero.
Definition: info.hh:57
UFSHostDevice::UFSHostDeviceStats::curDoorbell
Stats::Formula curDoorbell
Number of doorbells rung.
Definition: ufs_device.hh:522
UFSHostDevice::transferInfo::size
uint32_t size
Definition: ufs_device.hh:427
BaseGic::sendInt
virtual void sendInt(uint32_t num)=0
Post an interrupt from a device that is connected to the GIC.
UFSHostDevice::regUICErrorCodeNetworkLayer
@ regUICErrorCodeNetworkLayer
Definition: ufs_device.hh:1194
UFSHostDevice::LUNInfo::product3
uint32_t product3
Definition: ufs_device.hh:402
UFSHostDevice::UFSSCSIDevice::lunAvail
const uint32_t lunAvail
Definition: ufs_device.hh:693
UFSHostDevice::regControllerPRODID
@ regControllerPRODID
Definition: ufs_device.hh:1187
UFSHostDevice::UFSSCSIDevice::flashDevice
AbstractNVM * flashDevice
Definition: ufs_device.hh:687
UFSHostDevice::regUICCommandArg2
@ regUICCommandArg2
Definition: ufs_device.hh:1210
UFSHostDevice::pioAddr
const Addr pioAddr
Host controller information.
Definition: ufs_device.hh:1001
Drainable::drainState
DrainState drainState() const
Return the current drain state of an object.
Definition: drain.hh:320
UFSHostDevice::LUNInfo::vendor1
uint32_t vendor1
Definition: ufs_device.hh:398
SimObject::name
virtual const std::string name() const
Definition: sim_object.hh:133
BaseGic::clearInt
virtual void clearInt(uint32_t num)=0
Clear an interrupt from a device that is connected to the GIC.
AbstractNVM::initializeMemory
virtual void initializeMemory(uint64_t disk_size, uint32_t sector_size)=0
Initialize Memory.
UFSHostDevice::HCIMem::CMDUCMDARG1
uint32_t CMDUCMDARG1
Definition: ufs_device.hh:238
UFSHostDevice::UFSHCDSGEntry::upperAddr
uint32_t upperAddr
Definition: ufs_device.hh:303
UFSHostDevice::HCIMem::HCHCDDID
uint32_t HCHCDDID
Definition: ufs_device.hh:194
UFSHostDevice::regUTPTransferREQListBaseL
@ regUTPTransferREQListBaseL
Definition: ufs_device.hh:1198
UFSHostDevice::transferStart::lun_id
uint32_t lun_id
Definition: ufs_device.hh:457
UFSHostDevice::taskCommandTrack
uint32_t taskCommandTrack
Definition: ufs_device.hh:1050
UFSHostDevice::SCSIReply::senseSize
uint8_t senseSize
Definition: ufs_device.hh:383
UFSHostDevice::generateInterrupt
void generateInterrupt()
set interrupt and sort out the doorbell register.
Definition: ufs_device.cc:1811
UFSHostDevice::UTPTransferReqDesc::commandDescBaseAddrLo
uint32_t commandDescBaseAddrLo
Definition: ufs_device.hh:358
UFSHostDevice::SCSIResumeInfo::reqPos
int reqPos
Definition: ufs_device.hh:477
DmaDevice
Definition: dma_device.hh:165
Packet::getLE
T getLE() const
Get the data in the packet byte swapped from little endian to host endian.
Definition: packet_access.hh:75
inform
#define inform(...)
Definition: logging.hh:240
UFSHostDevice::UTPUPIUTaskReq::header
struct UTPUPIUHeader header
Definition: ufs_device.hh:287
UFSHostDevice::transferHandler
void transferHandler(struct UTPTransferReqDesc *request_in, int req_pos, Addr finaladdress, uint32_t finalsize, uint32_t done)
Transfer handler function.
Definition: ufs_device.cc:1426
UFSHostDevice::HCIMem::ORUECN
uint32_t ORUECN
Definition: ufs_device.hh:206
UFSHostDevice::regControllerStatus
@ regControllerStatus
Definition: ufs_device.hh:1190
UFSHostDevice::UTPTransferReqDesc::header
struct UFSHostDevice::UTPTransferReqDesc::RequestDescHeader header
UFSHostDevice::taskStart
Task start information.
Definition: ufs_device.hh:463
UNSERIALIZE_ARRAY
#define UNSERIALIZE_ARRAY(member, size)
Definition: serialize.hh:840
UFSHostDevice::regStats
void regStats() override
register statistics
Definition: ufs_device.cc:767
Stats::pdf
const FlagsType pdf
Print the percent of the total that this entry represents.
Definition: info.hh:51
UFSHostDevice::transferInfo::lunID
uint32_t lunID
Definition: ufs_device.hh:430
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:257
UFSHostDevice::HCIMem::HCHCPMID
uint32_t HCHCPMID
Definition: ufs_device.hh:195
UFSHostDevice::HCIMem::CMDUICCMDR
uint32_t CMDUICCMDR
Command registers.
Definition: ufs_device.hh:237
UFSHostDevice::regUTPTransferREQListClear
@ regUTPTransferREQListClear
Definition: ufs_device.hh:1201
UFSHostDevice::clearInterrupt
void clearInterrupt()
Interrupt control functions.
Definition: ufs_device.cc:1834
UFSHostDevice::stats
struct UFSHostDeviceStats stats
RequestHandler stats.
Definition: ufs_device.hh:1126
UFSHostDevice::UFSSCSIDevice::cachingPage
static const unsigned int cachingPage[5]
Definition: ufs_device.hh:753
UFSHostDevice::read
Tick read(PacketPtr pkt) override
register access functions
Definition: ufs_device.cc:921
ClockedObject::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: clocked_object.cc:61
UFSHostDevice::UFSHostDeviceStats::totalReadDiskTransactions
Stats::Scalar totalReadDiskTransactions
Definition: ufs_device.hh:507
UFSHostDevice::write
Tick write(PacketPtr pkt) override
UFSHCD write function.
Definition: ufs_device.cc:1059
UFSHostDevice::transferInfo::filePointer
uint32_t filePointer
Definition: ufs_device.hh:429
UFSHostDevice::UFSHostDeviceStats::totalWrittenSSD
Stats::Scalar totalWrittenSSD
Definition: ufs_device.hh:506
Stats::DistBase::sample
void sample(const U &v, int n=1)
Add a value to the distribtion n times.
Definition: statistics.hh:1924
UFSHostDevice::UPIUMessage::dataCount
uint32_t dataCount
Definition: ufs_device.hh:327
UFSHostDevice::HCIMem::TRUTRLBAU
uint32_t TRUTRLBAU
Definition: ufs_device.hh:220
UFSHostDevice::HCIMem::ORUECDL
uint32_t ORUECDL
Definition: ufs_device.hh:205
Packet::setLE
void setLE(T v)
Set the value in the data pointer to v as little endian.
Definition: packet_access.hh:105
UFSHostDevice::HCIMem::TMUTMRLCLR
uint32_t TMUTMRLCLR
Definition: ufs_device.hh:231
UFSHostDevice::SCSIResumeInfo::destination
std::vector< uint8_t > destination
Definition: ufs_device.hh:480
UFSHostDevice::SCSIReply::offset
uint64_t offset
Definition: ufs_device.hh:385
CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:63
UFSHostDevice::UPIUMessage::dataMsg
std::vector< uint32_t > dataMsg
Definition: ufs_device.hh:328
UFSHostDevice::transferDone
void transferDone(Addr responseStartAddr, uint32_t req_pos, struct UTPUPIURSP request_out, uint32_t size, Addr address, uint8_t *destination, bool finished, uint32_t lun_id)
transfer done, the beginning of the final stage of the transfer.
Definition: ufs_device.cc:1698
UFSHostDevice::LUNInfo::productRevision
uint32_t productRevision
Definition: ufs_device.hh:403
UFSHostDevice::garbage
std::deque< struct UTPTransferReqDesc * > garbage
garbage queue, ensure clearing of the allocated memory
Definition: ufs_device.hh:1121
Stats
Definition: statistics.cc:61
UFSHostDevice::regUTPTransferREQListBaseH
@ regUTPTransferREQListBaseH
Definition: ufs_device.hh:1199
UFSHostDevice::LUNInfo::product2
uint32_t product2
Definition: ufs_device.hh:401
UFSHostDevice::UICCommandReady
static const unsigned int UICCommandReady
Definition: ufs_device.hh:1176
UFSHostDevice::UFSHostDeviceStats::averageDoorbell
Stats::Average averageDoorbell
Definition: ufs_device.hh:524
findLsbSet
int findLsbSet(uint64_t val)
Returns the bit position of the LSB that is set in the input.
Definition: bitfield.hh:253
UFSHostDevice::SCSIReply::senseCode
uint8_t senseCode[19]
Definition: ufs_device.hh:386
UFSHostDevice::HCIMem::TMUTMRLBA
uint32_t TMUTMRLBA
Task control registers.
Definition: ufs_device.hh:228
UFSHostDevice::readGarbageEventQueue
std::deque< EventFunctionWrapper > readGarbageEventQueue
Event after a read to clean up the UTP data structures.
Definition: ufs_device.hh:1160
UFSHostDevice::UTPTransferReqDesc::RequestDescHeader::dWord2
uint32_t dWord2
Definition: ufs_device.hh:353
Stats::Histogram::init
Histogram & init(size_type size)
Set the parameters of this histogram.
Definition: statistics.hh:2669
UFSHostDevice::regInterruptStatus
@ regInterruptStatus
Definition: ufs_device.hh:1188
UFSHostDevice::LUNSignal
void LUNSignal()
LU callback function to indicate that the action has completed.
Definition: ufs_device.cc:1666
UFSHostDevice::transferStart::mask
uint32_t mask
Definition: ufs_device.hh:453
UFSHostDevice::SCSIResume
void SCSIResume(uint32_t lun_id)
Starts the scsi handling function in the apropriate Logic unit, prepares the right data transfer sche...
Definition: ufs_device.cc:1514
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
std::list< AddrRange >
UFSHostDevice::UFSHostDeviceStats::totalWriteDiskTransactions
Stats::Scalar totalWriteDiskTransactions
Definition: ufs_device.hh:508
UFSHostDevice::UFSHostDevice
UFSHostDevice(const UFSHostDeviceParams *p)
Constructor for the UFS Host device.
Definition: ufs_device.cc:715
UFSHostDevice::UFSSCSIDevice::Callback
std::function< void()> Callback
Definition: ufs_device.hh:539
CheckpointIn
Definition: serialize.hh:67
X86ISA::destination
destination
Definition: intmessage.hh:43
UFSHostDevice::SCSIInfo
struct SCSIResumeInfo SCSIInfo
SCSI resume info information structure for SCSI resume.
Definition: ufs_device.hh:1080
Stats::DataWrap::desc
Derived & desc(const std::string &_desc)
Set the description and marks this stat to print at the end of simulation.
Definition: statistics.hh:307
ufs_device.hh
UFSHostDevice::regUFSVersion
@ regUFSVersion
Definition: ufs_device.hh:1185
UFSHostDevice::UTPTransferReqDesc
struct UTPTransferReqDesc - UTRD structure header: UTRD header DW-0 to DW-3 commandDescBaseAddrLo: UC...
Definition: ufs_device.hh:341
UFSHostDevice::regUTPTransferREQINTAGGControl
@ regUTPTransferREQINTAGGControl
Definition: ufs_device.hh:1197
UFSHostDevice::SCSIResumeEvent
EventFunctionWrapper SCSIResumeEvent
The events that control the functionality.
Definition: ufs_device.hh:1150
UFSHostDevice::regControllerDEVID
@ regControllerDEVID
Definition: ufs_device.hh:1186
UFSHostDevice::HCIMem::ORUTRIACR
uint32_t ORUTRIACR
Definition: ufs_device.hh:209
UFSHostDevice::regUICErrorCodeTransportLayer
@ regUICErrorCodeTransportLayer
Definition: ufs_device.hh:1195
UFSHostDevice::LUNInfo::dWord0
uint32_t dWord0
Definition: ufs_device.hh:395
UFSHostDevice::UTPUPIUHeader::dWord1
uint32_t dWord1
Definition: ufs_device.hh:258
UFSHostDevice::UTPTaskREQCOMPL
static const unsigned int UTPTaskREQCOMPL
Definition: ufs_device.hh:1174
UFSHostDevice::manageReadTransfer
void manageReadTransfer(uint32_t size, uint32_t LUN, uint64_t offset, uint32_t sg_table_length, struct UFSHCDSGEntry *sglist)
Manage read transfer.
Definition: ufs_device.cc:2113
UFSHostDevice::UFSHostDeviceStats::currentWriteSSDQueue
Stats::Scalar currentWriteSSDQueue
Definition: ufs_device.hh:502
DrainState::Draining
@ Draining
Draining buffers pending serialization/handover.
UFSHostDevice::regUICCommandArg3
@ regUICCommandArg3
Definition: ufs_device.hh:1211
ArmISA::mask
Bitfield< 28, 24 > mask
Definition: miscregs_types.hh:711
UFSHostDevice::UFSSCSIDevice::writeFlash
void writeFlash(uint8_t *writeaddr, uint64_t offset, uint32_t size)
Write flash.
Definition: ufs_device.cc:702
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171
UFSHostDevice::writeToDiskBurst::start
Addr start
Definition: ufs_device.hh:489
UFSHostDevice::SCSIReply::msgSize
uint32_t msgSize
Definition: ufs_device.hh:380
UFSHostDevice::transferEnd
std::deque< struct transferStart > transferEnd
To finish the transaction one needs information about the original message.
Definition: ufs_device.hh:1089
UFSHostDevice::UFSSlots
const uint8_t UFSSlots
Definition: ufs_device.hh:1007
curTick
Tick curTick()
The current simulated tick.
Definition: core.hh:45
ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:153
SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:92
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