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cortex_a76.hh
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27 
28 #ifndef __ARCH_ARM_FASTMODEL_CORTEXA76_CORETEX_A76_HH__
29 #define __ARCH_ARM_FASTMODEL_CORTEXA76_CORETEX_A76_HH__
30 
34 #include "params/FastModelCortexA76.hh"
35 #include "params/FastModelCortexA76Cluster.hh"
36 #include "scx/scx.h"
37 #include "sim/port.hh"
39 
40 class BaseCPU;
41 
42 namespace FastModel
43 {
44 
45 // The fast model exports a class called scx_evs_CortexA76x1 which represents
46 // the subsystem described in LISA+. This class specializes it to export gem5
47 // ports and interface with its peer gem5 CPU. The gem5 CPU inherits from the
48 // gem5 BaseCPU class and implements its API, while this class actually does
49 // the work.
50 class CortexA76Cluster;
51 
52 class CortexA76 : public Iris::CPU<CortexA76TC>
53 {
54  protected:
56 
58  int num = 0;
59 
60  public:
61  PARAMS(FastModelCortexA76);
62  CortexA76(const Params &p) :
63  Base(p, scx::scx_get_iris_connection_interface())
64  {}
65 
66  void initState() override;
67 
68  template <class T>
69  void set_evs_param(const std::string &n, T val);
70 
71  void setCluster(CortexA76Cluster *_cluster, int _num);
72 
73  Port &getPort(const std::string &if_name,
74  PortID idx=InvalidPortID) override;
75 };
76 
78 {
79  private:
82 
83  public:
84  PARAMS(FastModelCortexA76Cluster);
85  template <class T>
86  void
87  set_evs_param(const std::string &n, T val)
88  {
89  scx::scx_set_parameter(evs->name() + std::string(".") + n, val);
90  }
91 
92  CortexA76 *getCore(int num) const { return cores.at(num); }
93  sc_core::sc_module *getEvs() const { return evs; }
94 
95  CortexA76Cluster(const Params &p);
96 
97  Port &getPort(const std::string &if_name,
98  PortID idx=InvalidPortID) override;
99 };
100 
101 template <class T>
102 inline void
103 CortexA76::set_evs_param(const std::string &n, T val)
104 {
105  for (auto &path: params().thread_paths)
106  cluster->set_evs_param(path + "." + n, val);
107 }
108 
109 } // namespace FastModel
110 
111 #endif // __ARCH_ARM_FASTMODEL_CORTEXA76_CORETEX_A76_HH__
SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:162
FastModel::CortexA76
Definition: cortex_a76.hh:52
sc_core::sc_module
Definition: sc_module.hh:97
InvalidPortID
const PortID InvalidPortID
Definition: types.hh:244
FastModel::CortexA76Cluster::PARAMS
PARAMS(FastModelCortexA76Cluster)
PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:243
thread_context.hh
std::vector
STL vector class.
Definition: stl.hh:37
FastModel::CortexA76::setCluster
void setCluster(CortexA76Cluster *_cluster, int _num)
Definition: cortex_a76.cc:49
cpu.hh
FastModel::CortexA76::cluster
CortexA76Cluster * cluster
Definition: cortex_a76.hh:57
ArmISA::n
Bitfield< 31 > n
Definition: miscregs_types.hh:450
FastModel::CortexA76::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: cortex_a76.cc:40
ClockedObject::Params
ClockedObjectParams Params
Parameters of ClockedObject.
Definition: clocked_object.hh:237
Port
Ports are used to interface objects to each other.
Definition: port.hh:56
FastModel::CortexA76Cluster::getCore
CortexA76 * getCore(int num) const
Definition: cortex_a76.hh:92
FastModel::CortexA76::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: cortex_a76.cc:95
X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
FastModel::CortexA76::set_evs_param
void set_evs_param(const std::string &n, T val)
Definition: cortex_a76.hh:103
port.hh
sc_module.hh
amba_ports.hh
BaseCPU
Definition: base.hh:104
FastModel::CortexA76::num
int num
Definition: cortex_a76.hh:58
FastModel::CortexA76Cluster::cores
std::vector< CortexA76 * > cores
Definition: cortex_a76.hh:80
FastModel
Definition: amba_from_tlm_bridge.cc:32
FastModel::CortexA76Cluster::set_evs_param
void set_evs_param(const std::string &n, T val)
Definition: cortex_a76.hh:87
FastModel::CortexA76Cluster
Definition: cortex_a76.hh:77
sc_core::sc_object::name
const char * name() const
Definition: sc_object.cc:44
FastModel::CortexA76Cluster::getEvs
sc_core::sc_module * getEvs() const
Definition: cortex_a76.hh:93
FastModel::CortexA76Cluster::CortexA76Cluster
CortexA76Cluster(const Params &p)
Definition: cortex_a76.cc:103
FastModel::CortexA76::PARAMS
PARAMS(FastModelCortexA76)
SimObject::params
const Params & params() const
Definition: sim_object.hh:168
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
FastModel::CortexA76Cluster::evs
sc_core::sc_module * evs
Definition: cortex_a76.hh:81
FastModel::CortexA76Cluster::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: cortex_a76.cc:190
FastModel::CortexA76::Base
Iris::CPU< CortexA76TC > Base
Definition: cortex_a76.hh:55
Serializable::path
static std::stack< std::string > path
Definition: serialize.hh:321
Iris::CPU
Definition: cpu.hh:112
FastModel::CortexA76::CortexA76
CortexA76(const Params &p)
Definition: cortex_a76.hh:62
SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:141

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