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decoder.cc
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28 
29 #include "arch/x86/decoder.hh"
30 
31 #include "arch/x86/regs/misc.hh"
32 #include "base/logging.hh"
33 #include "base/trace.hh"
34 #include "base/types.hh"
35 #include "debug/Decode.hh"
36 #include "debug/Decoder.hh"
37 
38 namespace X86ISA
39 {
40 
42 
45 {
46  origPC = basePC + offset;
47  DPRINTF(Decoder, "Setting origPC to %#x\n", origPC);
49  chunkIdx = 0;
50 
51  emi.rex = 0;
52  emi.legacy = 0;
53  emi.vex = 0;
54 
55  emi.opcode.type = BadOpcode;
56  emi.opcode.op = 0;
57 
59  emi.immediate = 0;
60  emi.displacement = 0;
61  emi.dispSize = 0;
62 
63  emi.modRM = 0;
64  emi.sib = 0;
65 
66  if (instBytes->si) {
67  return FromCacheState;
68  } else {
69  instBytes->chunks.clear();
70  return PrefixState;
71  }
72 }
73 
74 void
76 {
77  // This function drives the decoder state machine.
78 
79  // Some sanity checks. You shouldn't try to process more bytes if
80  // there aren't any, and you shouldn't overwrite an already decoded
81  // ExtMachInst.
82  assert(!outOfBytes);
83  assert(!instDone);
84 
85  if (state == ResetState)
86  state = doResetState();
87  if (state == FromCacheState) {
89  } else {
90  instBytes->chunks.push_back(fetchChunk);
91  }
92 
93  // While there's still something to do...
94  while (!instDone && !outOfBytes) {
95  uint8_t nextByte = getNextByte();
96  switch (state) {
97  case PrefixState:
98  state = doPrefixState(nextByte);
99  break;
100  case Vex2Of2State:
101  state = doVex2Of2State(nextByte);
102  break;
103  case Vex2Of3State:
104  state = doVex2Of3State(nextByte);
105  break;
106  case Vex3Of3State:
107  state = doVex3Of3State(nextByte);
108  break;
109  case VexOpcodeState:
110  state = doVexOpcodeState(nextByte);
111  break;
112  case OneByteOpcodeState:
113  state = doOneByteOpcodeState(nextByte);
114  break;
115  case TwoByteOpcodeState:
116  state = doTwoByteOpcodeState(nextByte);
117  break;
119  state = doThreeByte0F38OpcodeState(nextByte);
120  break;
122  state = doThreeByte0F3AOpcodeState(nextByte);
123  break;
124  case ModRMState:
125  state = doModRMState(nextByte);
126  break;
127  case SIBState:
128  state = doSIBState(nextByte);
129  break;
130  case DisplacementState:
132  break;
133  case ImmediateState:
135  break;
136  case ErrorState:
137  panic("Went to the error state in the decoder.\n");
138  default:
139  panic("Unrecognized state! %d\n", state);
140  }
141  }
142 }
143 
146 {
147  DPRINTF(Decoder, "Looking at cache state.\n");
148  if ((fetchChunk & instBytes->masks[chunkIdx]) !=
150  DPRINTF(Decoder, "Decode cache miss.\n");
151  // The chached chunks didn't match what was fetched. Fall back to the
152  // predecoder.
154  instBytes->chunks.resize(chunkIdx + 1);
155  instBytes->si = NULL;
156  chunkIdx = 0;
158  offset = origPC % sizeof(MachInst);
159  basePC = origPC - offset;
160  return PrefixState;
161  } else if (chunkIdx == instBytes->chunks.size() - 1) {
162  // We matched the cache, so use its value.
163  instDone = true;
165  if (offset == sizeof(MachInst))
166  outOfBytes = true;
167  return ResetState;
168  } else {
169  // We matched so far, but need to check more chunks.
170  chunkIdx++;
171  outOfBytes = true;
172  return FromCacheState;
173  }
174 }
175 
176 // Either get a prefix and record it in the ExtMachInst, or send the
177 // state machine on to get the opcode(s).
179 Decoder::doPrefixState(uint8_t nextByte)
180 {
181  uint8_t prefix = Prefixes[nextByte];
182  State nextState = PrefixState;
183  // REX prefixes are only recognized in 64 bit mode.
184  if (prefix == RexPrefix && emi.mode.submode != SixtyFourBitMode)
185  prefix = 0;
186  if (prefix)
187  consumeByte();
188  switch(prefix) {
189  // Operand size override prefixes
190  case OperandSizeOverride:
191  DPRINTF(Decoder, "Found operand size override prefix.\n");
192  emi.legacy.op = true;
193  break;
194  case AddressSizeOverride:
195  DPRINTF(Decoder, "Found address size override prefix.\n");
196  emi.legacy.addr = true;
197  break;
198  // Segment override prefixes
199  case CSOverride:
200  case DSOverride:
201  case ESOverride:
202  case FSOverride:
203  case GSOverride:
204  case SSOverride:
205  DPRINTF(Decoder, "Found segment override.\n");
206  emi.legacy.seg = prefix;
207  break;
208  case Lock:
209  DPRINTF(Decoder, "Found lock prefix.\n");
210  emi.legacy.lock = true;
211  break;
212  case Rep:
213  DPRINTF(Decoder, "Found rep prefix.\n");
214  emi.legacy.rep = true;
215  break;
216  case Repne:
217  DPRINTF(Decoder, "Found repne prefix.\n");
218  emi.legacy.repne = true;
219  break;
220  case RexPrefix:
221  DPRINTF(Decoder, "Found Rex prefix %#x.\n", nextByte);
222  emi.rex = nextByte;
223  break;
224  case Vex2Prefix:
225  DPRINTF(Decoder, "Found VEX two-byte prefix %#x.\n", nextByte);
226  emi.vex.present = 1;
227  nextState = Vex2Of2State;
228  break;
229  case Vex3Prefix:
230  DPRINTF(Decoder, "Found VEX three-byte prefix %#x.\n", nextByte);
231  emi.vex.present = 1;
232  nextState = Vex2Of3State;
233  break;
234  case 0:
235  nextState = OneByteOpcodeState;
236  break;
237 
238  default:
239  panic("Unrecognized prefix %#x\n", nextByte);
240  }
241  return nextState;
242 }
243 
245 Decoder::doVex2Of2State(uint8_t nextByte)
246 {
247  consumeByte();
248  Vex2Of2 vex = nextByte;
249 
250  emi.rex.r = !vex.r;
251 
252  emi.vex.l = vex.l;
253  emi.vex.v = ~vex.v;
254 
255  switch (vex.p) {
256  case 0:
257  break;
258  case 1:
259  emi.legacy.op = 1;
260  break;
261  case 2:
262  emi.legacy.rep = 1;
263  break;
264  case 3:
265  emi.legacy.repne = 1;
266  break;
267  }
268 
269  emi.opcode.type = TwoByteOpcode;
270 
271  return VexOpcodeState;
272 }
273 
275 Decoder::doVex2Of3State(uint8_t nextByte)
276 {
277  if (emi.mode.submode != SixtyFourBitMode && bits(nextByte, 7, 6) == 0x3) {
278  // This was actually an LDS instruction. Reroute to that path.
279  emi.vex.present = 0;
280  emi.opcode.type = OneByteOpcode;
281  emi.opcode.op = 0xC4;
283  nextByte >= 0xA0 && nextByte <= 0xA3);
284  }
285 
286  consumeByte();
287  Vex2Of3 vex = nextByte;
288 
289  emi.rex.r = !vex.r;
290  emi.rex.x = !vex.x;
291  emi.rex.b = !vex.b;
292 
293  switch (vex.m) {
294  case 1:
295  emi.opcode.type = TwoByteOpcode;
296  break;
297  case 2:
298  emi.opcode.type = ThreeByte0F38Opcode;
299  break;
300  case 3:
301  emi.opcode.type = ThreeByte0F3AOpcode;
302  break;
303  default:
304  // These encodings are reserved. Pretend this was an undefined
305  // instruction so the main decoder will behave correctly, and stop
306  // trying to interpret bytes.
307  emi.opcode.type = TwoByteOpcode;
308  emi.opcode.op = 0x0B;
309  instDone = true;
310  return ResetState;
311  }
312  return Vex3Of3State;
313 }
314 
316 Decoder::doVex3Of3State(uint8_t nextByte)
317 {
318  if (emi.mode.submode != SixtyFourBitMode && bits(nextByte, 7, 6) == 0x3) {
319  // This was actually an LES instruction. Reroute to that path.
320  emi.vex.present = 0;
321  emi.opcode.type = OneByteOpcode;
322  emi.opcode.op = 0xC5;
324  nextByte >= 0xA0 && nextByte <= 0xA3);
325  }
326 
327  consumeByte();
328  Vex3Of3 vex = nextByte;
329 
330  emi.rex.w = vex.w;
331 
332  emi.vex.l = vex.l;
333  emi.vex.v = ~vex.v;
334 
335  switch (vex.p) {
336  case 0:
337  break;
338  case 1:
339  emi.legacy.op = 1;
340  break;
341  case 2:
342  emi.legacy.rep = 1;
343  break;
344  case 3:
345  emi.legacy.repne = 1;
346  break;
347  }
348 
349  return VexOpcodeState;
350 }
351 
353 Decoder::doVexOpcodeState(uint8_t nextByte)
354 {
355  DPRINTF(Decoder, "Found VEX opcode %#x.\n", nextByte);
356 
357  emi.opcode.op = nextByte;
358  consumeByte();
359 
360  switch (emi.opcode.type) {
361  case TwoByteOpcode:
363  case ThreeByte0F38Opcode:
366  case ThreeByte0F3AOpcode:
369  default:
370  panic("Unrecognized opcode type %d.\n", emi.opcode.type);
371  }
372 }
373 
374 // Load the first opcode byte. Determine if there are more opcode bytes, and
375 // if not, what immediate and/or ModRM is needed.
378 {
379  State nextState = ErrorState;
380  consumeByte();
381 
382  if (nextByte == 0x0f) {
383  DPRINTF(Decoder, "Found opcode escape byte %#x.\n", nextByte);
384  nextState = TwoByteOpcodeState;
385  } else {
386  DPRINTF(Decoder, "Found one byte opcode %#x.\n", nextByte);
387  emi.opcode.type = OneByteOpcode;
388  emi.opcode.op = nextByte;
389 
391  nextByte >= 0xA0 && nextByte <= 0xA3);
392  }
393  return nextState;
394 }
395 
396 // Load the second opcode byte. Determine if there are more opcode bytes, and
397 // if not, what immediate and/or ModRM is needed.
400 {
401  State nextState = ErrorState;
402  consumeByte();
403  if (nextByte == 0x38) {
404  nextState = ThreeByte0F38OpcodeState;
405  DPRINTF(Decoder, "Found opcode escape byte %#x.\n", nextByte);
406  } else if (nextByte == 0x3a) {
407  nextState = ThreeByte0F3AOpcodeState;
408  DPRINTF(Decoder, "Found opcode escape byte %#x.\n", nextByte);
409  } else {
410  DPRINTF(Decoder, "Found two byte opcode %#x.\n", nextByte);
411  emi.opcode.type = TwoByteOpcode;
412  emi.opcode.op = nextByte;
413 
415  }
416  return nextState;
417 }
418 
419 // Load the third opcode byte and determine what immediate and/or ModRM is
420 // needed.
423 {
424  consumeByte();
425 
426  DPRINTF(Decoder, "Found three byte 0F38 opcode %#x.\n", nextByte);
427  emi.opcode.type = ThreeByte0F38Opcode;
428  emi.opcode.op = nextByte;
429 
431 }
432 
433 // Load the third opcode byte and determine what immediate and/or ModRM is
434 // needed.
437 {
438  consumeByte();
439 
440  DPRINTF(Decoder, "Found three byte 0F3A opcode %#x.\n", nextByte);
441  emi.opcode.type = ThreeByte0F3AOpcode;
442  emi.opcode.op = nextByte;
443 
445 }
446 
447 // Generic opcode processing which determines the immediate size, and whether
448 // or not there's a modrm byte.
450 Decoder::processOpcode(ByteTable &immTable, ByteTable &modrmTable,
451  bool addrSizedImm)
452 {
453  State nextState = ErrorState;
454  const uint8_t opcode = emi.opcode.op;
455 
456  // Figure out the effective operand size. This can be overriden to
457  // a fixed value at the decoder level.
458  int logOpSize;
459  if (emi.rex.w)
460  logOpSize = 3; // 64 bit operand size
461  else if (emi.legacy.op)
462  logOpSize = altOp;
463  else
464  logOpSize = defOp;
465 
466  // Set the actual op size.
467  emi.opSize = 1 << logOpSize;
468 
469  // Figure out the effective address size. This can be overriden to
470  // a fixed value at the decoder level.
471  int logAddrSize;
472  if (emi.legacy.addr)
473  logAddrSize = altAddr;
474  else
475  logAddrSize = defAddr;
476 
477  // Set the actual address size.
478  emi.addrSize = 1 << logAddrSize;
479 
480  // Figure out the effective stack width. This can be overriden to
481  // a fixed value at the decoder level.
482  emi.stackSize = 1 << stack;
483 
484  // Figure out how big of an immediate we'll retreive based
485  // on the opcode.
486  int immType = immTable[opcode];
487  if (addrSizedImm)
488  immediateSize = SizeTypeToSize[logAddrSize - 1][immType];
489  else
490  immediateSize = SizeTypeToSize[logOpSize - 1][immType];
491 
492  // Determine what to expect next.
493  if (modrmTable[opcode]) {
494  nextState = ModRMState;
495  } else {
496  if (immediateSize) {
497  nextState = ImmediateState;
498  } else {
499  instDone = true;
500  nextState = ResetState;
501  }
502  }
503  return nextState;
504 }
505 
506 // Get the ModRM byte and determine what displacement, if any, there is.
507 // Also determine whether or not to get the SIB byte, displacement, or
508 // immediate next.
510 Decoder::doModRMState(uint8_t nextByte)
511 {
512  State nextState = ErrorState;
513  ModRM modRM = nextByte;
514  DPRINTF(Decoder, "Found modrm byte %#x.\n", nextByte);
515  if (defOp == 1) {
516  // Figure out 16 bit displacement size.
517  if ((modRM.mod == 0 && modRM.rm == 6) || modRM.mod == 2)
518  displacementSize = 2;
519  else if (modRM.mod == 1)
520  displacementSize = 1;
521  else
522  displacementSize = 0;
523  } else {
524  // Figure out 32/64 bit displacement size.
525  if ((modRM.mod == 0 && modRM.rm == 5) || modRM.mod == 2)
526  displacementSize = 4;
527  else if (modRM.mod == 1)
528  displacementSize = 1;
529  else
530  displacementSize = 0;
531  }
532 
533  // The "test" instruction in group 3 needs an immediate, even though
534  // the other instructions with the same actual opcode don't.
535  if (emi.opcode.type == OneByteOpcode && (modRM.reg & 0x6) == 0) {
536  if (emi.opcode.op == 0xF6)
537  immediateSize = 1;
538  else if (emi.opcode.op == 0xF7)
539  immediateSize = (emi.opSize == 8) ? 4 : emi.opSize;
540  }
541 
542  // If there's an SIB, get that next.
543  // There is no SIB in 16 bit mode.
544  if (modRM.rm == 4 && modRM.mod != 3) {
545  // && in 32/64 bit mode)
546  nextState = SIBState;
547  } else if (displacementSize) {
548  nextState = DisplacementState;
549  } else if (immediateSize) {
550  nextState = ImmediateState;
551  } else {
552  instDone = true;
553  nextState = ResetState;
554  }
555  // The ModRM byte is consumed no matter what.
556  consumeByte();
557  emi.modRM = modRM;
558  return nextState;
559 }
560 
561 // Get the SIB byte. We don't do anything with it at this point, other
562 // than storing it in the ExtMachInst. Determine if we need to get a
563 // displacement or immediate next.
565 Decoder::doSIBState(uint8_t nextByte)
566 {
567  State nextState = ErrorState;
568  emi.sib = nextByte;
569  DPRINTF(Decoder, "Found SIB byte %#x.\n", nextByte);
570  consumeByte();
571  if (emi.modRM.mod == 0 && emi.sib.base == 5)
572  displacementSize = 4;
573  if (displacementSize) {
574  nextState = DisplacementState;
575  } else if (immediateSize) {
576  nextState = ImmediateState;
577  } else {
578  instDone = true;
579  nextState = ResetState;
580  }
581  return nextState;
582 }
583 
584 // Gather up the displacement, or at least as much of it as we can get.
587 {
588  State nextState = ErrorState;
589 
593 
594  DPRINTF(Decoder, "Collecting %d byte displacement, got %d bytes.\n",
596 
598  // Reset this for other immediates.
599  immediateCollected = 0;
600  // Sign extend the displacement.
601  switch(displacementSize)
602  {
603  case 1:
604  emi.displacement = sext<8>(emi.displacement);
605  break;
606  case 2:
607  emi.displacement = sext<16>(emi.displacement);
608  break;
609  case 4:
610  emi.displacement = sext<32>(emi.displacement);
611  break;
612  default:
613  panic("Undefined displacement size!\n");
614  }
615  DPRINTF(Decoder, "Collected displacement %#x.\n",
616  emi.displacement);
617  if (immediateSize) {
618  nextState = ImmediateState;
619  } else {
620  instDone = true;
621  nextState = ResetState;
622  }
623 
625  }
626  else
627  nextState = DisplacementState;
628  return nextState;
629 }
630 
631 // Gather up the immediate, or at least as much of it as we can get.
634 {
635  State nextState = ErrorState;
636 
638 
639  DPRINTF(Decoder, "Collecting %d byte immediate, got %d bytes.\n",
641 
643  // Reset this for other immediates.
644  immediateCollected = 0;
645 
646  //XXX Warning! The following is an observed pattern and might
647  // not always be true!
648 
649  // Instructions which use 64 bit operands but 32 bit immediates
650  // need to have the immediate sign extended to 64 bits.
651  // Instructions which use true 64 bit immediates won't be
652  // affected, and instructions that use true 32 bit immediates
653  // won't notice.
654  switch(immediateSize) {
655  case 4:
656  emi.immediate = sext<32>(emi.immediate);
657  break;
658  case 1:
659  emi.immediate = sext<8>(emi.immediate);
660  }
661 
662  DPRINTF(Decoder, "Collected immediate %#x.\n",
663  emi.immediate);
664  instDone = true;
665  nextState = ResetState;
666  } else {
667  nextState = ImmediateState;
668  }
669  return nextState;
670 }
671 
674 
677 {
679 
680  auto iter = instMap->find(mach_inst);
681  if (iter != instMap->end()) {
682  si = iter->second;
683  } else {
684  si = decodeInst(mach_inst);
685  (*instMap)[mach_inst] = si;
686  }
687 
688  DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
689  si->getName(), mach_inst);
690  return si;
691 }
692 
695 {
696  if (!instDone)
697  return NULL;
698  instDone = false;
699  updateNPC(nextPC);
700 
702  if (si)
703  return si;
704 
705  // We didn't match in the AddrMap, but we still populated an entry. Fix
706  // up its byte masks.
707  const int chunkSize = sizeof(MachInst);
708 
710 
711  Addr firstBasePC = basePC - (instBytes->chunks.size() - 1) * chunkSize;
712  Addr firstOffset = origPC - firstBasePC;
713  Addr totalSize = instBytes->lastOffset - firstOffset +
714  (instBytes->chunks.size() - 1) * chunkSize;
715  int start = firstOffset;
716  instBytes->masks.clear();
717 
718  while (totalSize) {
719  int end = start + totalSize;
720  end = (chunkSize < end) ? chunkSize : end;
721  int size = end - start;
722  int idx = instBytes->masks.size();
723 
724  MachInst maskVal = mask(size * 8) << (start * 8);
725  assert(maskVal);
726 
727  instBytes->masks.push_back(maskVal);
728  instBytes->chunks[idx] &= instBytes->masks[idx];
729  totalSize -= size;
730  start = 0;
731  }
732 
733  si = decode(emi, origPC);
734  return si;
735 }
736 
739 {
740  return microcodeRom.fetchMicroop(micropc, curMacroop);
741 }
742 
743 }
X86ISA::Decoder::UsesModRMThreeByte0F38
static ByteTable UsesModRMThreeByte0F38
Definition: decoder.hh:62
X86ISA::Rep
@ Rep
Definition: types.hh:67
X86ISA::ExtMachInst::mode
OperatingMode mode
Definition: types.hh:232
X86ISA::Decoder::updateNPC
void updateNPC(X86ISA::PCState &nextPC)
Definition: decoder.hh:317
X86ISA::Decoder::PrefixState
@ PrefixState
Definition: decoder.hh:187
X86ISA::Decoder::InstBytes::chunks
std::vector< MachInst > chunks
Definition: decoder.hh:77
X86ISA::Decoder::SIBState
@ SIBState
Definition: decoder.hh:197
X86ISA::Decoder::SizeTypeToSize
static const uint8_t SizeTypeToSize[3][10]
Definition: decoder.hh:56
X86ISA::Decoder::outOfBytes
bool outOfBytes
Definition: decoder.hh:173
X86ISA::si
Bitfield< 15, 3 > si
Definition: misc.hh:860
X86ISA::DSOverride
@ DSOverride
Definition: types.hh:60
X86ISA::ExtMachInst::op
Opcode op
Definition: types.hh:213
X86ISA::Decoder::defAddr
uint8_t defAddr
Definition: decoder.hh:105
X86ISA::Decoder::getImmediate
void getImmediate(int &collected, uint64_t &current, int size)
Definition: decoder.hh:115
X86ISA::Decoder::UsesModRMThreeByte0F3A
static ByteTable UsesModRMThreeByte0F3A
Definition: decoder.hh:63
X86ISA::Decoder::ThreeByte0F3AOpcodeState
@ ThreeByte0F3AOpcodeState
Definition: decoder.hh:195
X86ISA::Decoder::doVex2Of3State
State doVex2Of3State(uint8_t)
Definition: decoder.cc:275
X86ISA::Decoder::doPrefixState
State doPrefixState(uint8_t)
Definition: decoder.cc:179
X86ISA::Decoder::DisplacementState
@ DisplacementState
Definition: decoder.hh:198
X86ISAInst::MicrocodeRom::fetchMicroop
StaticInstPtr fetchMicroop(MicroPC microPC, StaticInstPtr curMacroop)
Definition: microcode_rom.hh:60
X86ISA::ESOverride
@ ESOverride
Definition: types.hh:57
X86ISA::Decoder::process
void process()
Definition: decoder.cc:75
X86ISA::Decoder::decodeInst
StaticInstPtr decodeInst(ExtMachInst mach_inst)
X86ISA::Decoder::basePC
Addr basePC
Definition: decoder.hh:92
X86ISA::Decoder::altOp
uint8_t altOp
Definition: decoder.hh:102
X86ISA::Decoder::doVex3Of3State
State doVex3Of3State(uint8_t)
Definition: decoder.cc:316
X86ISA::Decoder::doTwoByteOpcodeState
State doTwoByteOpcodeState(uint8_t)
Definition: decoder.cc:399
X86ISA::MachInst
uint64_t MachInst
Definition: types.hh:53
X86ISA::Vex2Prefix
@ Vex2Prefix
Definition: types.hh:69
X86ISA::ExtMachInst::immediate
uint64_t immediate
Definition: types.hh:219
X86ISA::Decoder::immediateSize
int immediateSize
Definition: decoder.hh:179
X86ISA::Decoder::ResetState
@ ResetState
Definition: decoder.hh:185
X86ISA::Decoder::UsesModRMTwoByte
static ByteTable UsesModRMTwoByte
Definition: decoder.hh:61
X86ISA::Decoder::VexOpcodeState
@ VexOpcodeState
Definition: decoder.hh:191
X86ISA::Decoder::Vex2Of3State
@ Vex2Of3State
Definition: decoder.hh:189
decoder.hh
X86ISA::Decoder::doSIBState
State doSIBState(uint8_t)
Definition: decoder.cc:565
X86ISA::SSOverride
@ SSOverride
Definition: types.hh:59
X86ISA::ExtMachInst::displacement
uint64_t displacement
Definition: types.hh:220
X86ISA::Decoder::ImmediateTypeThreeByte0F3A
static ByteTable ImmediateTypeThreeByte0F3A
Definition: decoder.hh:68
DecodeCache::AddrMap::lookup
Value & lookup(Addr addr)
Definition: decode_cache.hh:127
X86ISA::AddressSizeOverride
@ AddressSizeOverride
Definition: types.hh:65
X86ISA::Decoder::InstBytes::lastOffset
int lastOffset
Definition: decoder.hh:79
X86ISA::FSOverride
@ FSOverride
Definition: types.hh:61
X86ISA::Decoder::Vex3Of3State
@ Vex3Of3State
Definition: decoder.hh:190
X86ISA::Decoder::ImmediateTypeTwoByte
static ByteTable ImmediateTypeTwoByte
Definition: decoder.hh:66
X86ISA::GSOverride
@ GSOverride
Definition: types.hh:62
X86ISA::Decoder::stack
uint8_t stack
Definition: decoder.hh:106
X86ISA::ExtMachInst::opSize
uint8_t opSize
Definition: types.hh:223
X86ISA::Decoder::state
State state
Definition: decoder.hh:204
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:237
X86ISA::OperandSizeOverride
@ OperandSizeOverride
Definition: types.hh:64
X86ISA::ExtMachInst::opcode
struct X86ISA::ExtMachInst::@20 opcode
X86ISA::Decoder::immediateCollected
int immediateCollected
Definition: decoder.hh:182
X86ISA::ExtMachInst::addrSize
uint8_t addrSize
Definition: types.hh:225
X86ISA::Decoder::processOpcode
State processOpcode(ByteTable &immTable, ByteTable &modrmTable, bool addrSizedImm=false)
Definition: decoder.cc:450
X86ISA::Decoder::doModRMState
State doModRMState(uint8_t)
Definition: decoder.cc:510
X86ISA::PCState
Definition: types.hh:286
X86ISA::Decoder::defOp
uint8_t defOp
Definition: decoder.hh:103
X86ISA::Repne
@ Repne
Definition: types.hh:68
X86ISA::Decoder::UsesModRMOneByte
static ByteTable UsesModRMOneByte
Definition: decoder.hh:60
X86ISA::Decoder::doVexOpcodeState
State doVexOpcodeState(uint8_t)
Definition: decoder.cc:353
X86ISA::Decoder::getNextByte
uint8_t getNextByte()
Definition: decoder.hh:109
X86ISA::ExtMachInst
Definition: types.hh:199
X86ISAInst::MicrocodeRom
Definition: microcode_rom.hh:39
X86ISA::Decoder::decodePages
DecodePages * decodePages
Definition: decoder.hh:235
X86ISA::Decoder::fetchRomMicroop
StaticInstPtr fetchRomMicroop(MicroPC micropc, StaticInstPtr curMacroop) override
Definition: decoder.cc:738
X86ISA::Decoder::ModRMState
@ ModRMState
Definition: decoder.hh:196
X86ISA::Decoder::instDone
bool instDone
Definition: decoder.hh:175
X86ISA::Decoder::instBytes
InstBytes * instBytes
Definition: decoder.hh:89
X86ISA
This is exposed globally, independent of the ISA.
Definition: acpi.hh:55
X86ISA::Decoder::origPC
Addr origPC
Definition: decoder.hh:94
X86ISA::Decoder::instCacheMap
static InstCacheMap instCacheMap
Definition: decoder.hh:242
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:148
X86ISA::Decoder::TwoByteOpcodeState
@ TwoByteOpcodeState
Definition: decoder.hh:193
X86ISA::ExtMachInst::modRM
ModRM modRM
Definition: types.hh:216
X86ISA::Vex3Prefix
@ Vex3Prefix
Definition: types.hh:70
X86ISA::Decoder::chunkIdx
int chunkIdx
Definition: decoder.hh:90
X86ISA::Decoder::ErrorState
@ ErrorState
Definition: decoder.hh:201
ArmISA::opcode
Bitfield< 24, 21 > opcode
Definition: types.hh:101
X86ISA::Decoder::InstBytes
Definition: decoder.hh:74
X86ISA::Decoder::ImmediateTypeOneByte
static ByteTable ImmediateTypeOneByte
Definition: decoder.hh:65
X86ISA::Decoder::doThreeByte0F38OpcodeState
State doThreeByte0F38OpcodeState(uint8_t)
Definition: decoder.cc:422
X86ISA::Decoder::dummy
static InstBytes dummy
Definition: decoder.hh:85
X86ISA::Prefixes
Prefixes
Definition: types.hh:55
X86ISA::Decoder::ThreeByte0F38OpcodeState
@ ThreeByte0F38OpcodeState
Definition: decoder.hh:194
X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:80
X86ISA::Lock
@ Lock
Definition: types.hh:66
X86ISA::CSOverride
@ CSOverride
Definition: types.hh:58
X86ISA::Decoder::ImmediateTypeThreeByte0F38
static ByteTable ImmediateTypeThreeByte0F38
Definition: decoder.hh:67
X86ISA::Decoder::doImmediateState
State doImmediateState()
Definition: decoder.cc:633
X86ISA::ExtMachInst::stackSize
uint8_t stackSize
Definition: types.hh:227
X86ISA::Decoder::ImmediateState
@ ImmediateState
Definition: decoder.hh:199
X86ISA::Decoder::fetchChunk
MachInst fetchChunk
Definition: decoder.hh:88
X86ISA::Decoder::doResetState
State doResetState()
Definition: decoder.cc:44
types.hh
X86ISA::Decoder::doVex2Of2State
State doVex2Of2State(uint8_t)
Definition: decoder.cc:245
X86ISA::ExtMachInst::type
OpcodeType type
Definition: types.hh:211
X86ISA::Decoder::decode
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition: decoder.cc:676
X86ISA::Decoder::InstBytes::masks
std::vector< MachInst > masks
Definition: decoder.hh:78
X86ISA::Decoder::InstCacheMap
std::unordered_map< CacheKey, DecodeCache::InstMap< ExtMachInst > * > InstCacheMap
Definition: decoder.hh:241
X86ISA::ExtMachInst::rex
Rex rex
Definition: types.hh:205
X86ISA::Decoder::InstBytes::si
StaticInstPtr si
Definition: decoder.hh:76
X86ISA::Decoder::instMap
DecodeCache::InstMap< ExtMachInst > * instMap
Definition: decoder.hh:239
logging.hh
X86ISA::ExtMachInst::sib
Sib sib
Definition: types.hh:217
X86ISA::ExtMachInst::vex
VexInfo vex
Definition: types.hh:206
X86ISA::ExtMachInst::dispSize
uint8_t dispSize
Definition: types.hh:229
X86ISA::Decoder::doOneByteOpcodeState
State doOneByteOpcodeState(uint8_t)
Definition: decoder.cc:377
bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:73
X86ISA::mask
mask
Definition: misc.hh:796
X86ISA::Decoder::FromCacheState
@ FromCacheState
Definition: decoder.hh:186
X86ISA::Decoder::doDisplacementState
State doDisplacementState()
Definition: decoder.cc:586
X86ISA::Decoder::consumeByte
void consumeByte()
Definition: decoder.hh:157
X86ISA::Decoder::doFromCacheState
State doFromCacheState()
Definition: decoder.cc:145
X86ISA::ExtMachInst::legacy
LegacyPrefixVector legacy
Definition: types.hh:204
RefCountingPtr< StaticInst >
X86ISA::Decoder::offset
int offset
Definition: decoder.hh:96
X86ISA::Decoder::doThreeByte0F3AOpcodeState
State doThreeByte0F3AOpcodeState(uint8_t)
Definition: decoder.cc:436
trace.hh
X86ISA::SixtyFourBitMode
@ SixtyFourBitMode
Definition: types.hh:191
X86ISA::Decoder::microcodeRom
static X86ISAInst::MicrocodeRom microcodeRom
Definition: decoder.hh:71
X86ISA::Decoder::OneByteOpcodeState
@ OneByteOpcodeState
Definition: decoder.hh:192
X86ISA::RexPrefix
@ RexPrefix
Definition: types.hh:63
MicroPC
uint16_t MicroPC
Definition: types.hh:150
X86ISA::Decoder::displacementSize
int displacementSize
Definition: decoder.hh:177
X86ISA::Decoder::altAddr
uint8_t altAddr
Definition: decoder.hh:104
X86ISA::Decoder::Vex2Of2State
@ Vex2Of2State
Definition: decoder.hh:188
X86ISA::Decoder
Definition: decoder.hh:52
misc.hh
X86ISA::Decoder::emi
ExtMachInst emi
Definition: decoder.hh:98
X86ISA::Decoder::State
State
Definition: decoder.hh:184
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171

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