gem5  v21.1.0.2
PerfectCacheMemory.hh
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40 
41 #ifndef __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__
42 #define __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__
43 
44 #include <unordered_map>
45 
46 #include "base/compiler.hh"
48 #include "mem/ruby/protocol/AccessPermission.hh"
49 
50 namespace gem5
51 {
52 
53 namespace ruby
54 {
55 
56 template<class ENTRY>
58 {
59  PerfectCacheLineState() { m_permission = AccessPermission_NUM; }
60  AccessPermission m_permission;
61  ENTRY m_entry;
62 };
63 
64 template<class ENTRY>
65 inline std::ostream&
66 operator<<(std::ostream& out, const PerfectCacheLineState<ENTRY>& obj)
67 {
68  return out;
69 }
70 
71 template<class ENTRY>
73 {
74  public:
76 
77  // tests to see if an address is present in the cache
78  bool isTagPresent(Addr address) const;
79 
80  // Returns true if there is:
81  // a) a tag match on this address or there is
82  // b) an Invalid line in the same cache "way"
83  bool cacheAvail(Addr address) const;
84 
85  // find an Invalid entry and sets the tag appropriate for the address
86  void allocate(Addr address);
87 
88  void deallocate(Addr address);
89 
90  // Returns with the physical address of the conflicting cache line
91  Addr cacheProbe(Addr newAddress) const;
92 
93  // looks an address up in the cache
94  ENTRY* lookup(Addr address);
95  const ENTRY* lookup(Addr address) const;
96 
97  // Get/Set permission of cache block
98  AccessPermission getPermission(Addr address) const;
99  void changePermission(Addr address, AccessPermission new_perm);
100 
101  // Print cache contents
102  void print(std::ostream& out) const;
103 
104  private:
105  // Private copy constructor and assignment operator
108 
109  // Data Members (m_prefix)
110  std::unordered_map<Addr, PerfectCacheLineState<ENTRY> > m_map;
111 };
112 
113 template<class ENTRY>
114 inline std::ostream&
115 operator<<(std::ostream& out, const PerfectCacheMemory<ENTRY>& obj)
116 {
117  obj.print(out);
118  out << std::flush;
119  return out;
120 }
121 
122 template<class ENTRY>
123 inline
125 {
126 }
127 
128 // tests to see if an address is present in the cache
129 template<class ENTRY>
130 inline bool
132 {
133  return m_map.count(makeLineAddress(address)) > 0;
134 }
135 
136 template<class ENTRY>
137 inline bool
139 {
140  return true;
141 }
142 
143 // find an Invalid or already allocated entry and sets the tag
144 // appropriate for the address
145 template<class ENTRY>
146 inline void
148 {
149  PerfectCacheLineState<ENTRY> line_state;
150  line_state.m_permission = AccessPermission_Invalid;
151  line_state.m_entry = ENTRY();
152  m_map[makeLineAddress(address)] = line_state;
153 }
154 
155 // deallocate entry
156 template<class ENTRY>
157 inline void
159 {
160  GEM5_VAR_USED auto num_erased = m_map.erase(makeLineAddress(address));
161  assert(num_erased == 1);
162 }
163 
164 // Returns with the physical address of the conflicting cache line
165 template<class ENTRY>
166 inline Addr
168 {
169  panic("cacheProbe called in perfect cache");
170  return newAddress;
171 }
172 
173 // looks an address up in the cache
174 template<class ENTRY>
175 inline ENTRY*
177 {
178  return &m_map[makeLineAddress(address)].m_entry;
179 }
180 
181 // looks an address up in the cache
182 template<class ENTRY>
183 inline const ENTRY*
185 {
186  return &m_map[makeLineAddress(address)].m_entry;
187 }
188 
189 template<class ENTRY>
190 inline AccessPermission
192 {
193  return m_map[makeLineAddress(address)].m_permission;
194 }
195 
196 template<class ENTRY>
197 inline void
199  AccessPermission new_perm)
200 {
201  Addr line_address = makeLineAddress(address);
202  PerfectCacheLineState<ENTRY>& line_state = m_map[line_address];
203  line_state.m_permission = new_perm;
204 }
205 
206 template<class ENTRY>
207 inline void
208 PerfectCacheMemory<ENTRY>::print(std::ostream& out) const
209 {
210 }
211 
212 } // namespace ruby
213 } // namespace gem5
214 
215 #endif // __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__
gem5::ruby::PerfectCacheMemory
Definition: PerfectCacheMemory.hh:72
gem5::ruby::PerfectCacheLineState::m_entry
ENTRY m_entry
Definition: PerfectCacheMemory.hh:61
gem5::ruby::PerfectCacheMemory::isTagPresent
bool isTagPresent(Addr address) const
Definition: PerfectCacheMemory.hh:131
gem5::ruby::operator<<
std::ostream & operator<<(std::ostream &os, const BoolVec &myvector)
Definition: BoolVec.cc:49
gem5::ruby::PerfectCacheMemory::deallocate
void deallocate(Addr address)
Definition: PerfectCacheMemory.hh:158
gem5::ruby::PerfectCacheMemory::m_map
std::unordered_map< Addr, PerfectCacheLineState< ENTRY > > m_map
Definition: PerfectCacheMemory.hh:110
gem5::ruby::makeLineAddress
Addr makeLineAddress(Addr addr)
Definition: Address.cc:60
gem5::ruby::PerfectCacheLineState::m_permission
AccessPermission m_permission
Definition: PerfectCacheMemory.hh:60
gem5::ruby::PerfectCacheMemory::lookup
ENTRY * lookup(Addr address)
Definition: PerfectCacheMemory.hh:176
gem5::ruby::PerfectCacheMemory::print
void print(std::ostream &out) const
Definition: PerfectCacheMemory.hh:208
gem5::ruby::PerfectCacheLineState::PerfectCacheLineState
PerfectCacheLineState()
Definition: PerfectCacheMemory.hh:59
gem5::ruby::PerfectCacheMemory::cacheAvail
bool cacheAvail(Addr address) const
Definition: PerfectCacheMemory.hh:138
compiler.hh
gem5::ruby::PerfectCacheMemory::operator=
PerfectCacheMemory & operator=(const PerfectCacheMemory &obj)
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ruby::PerfectCacheLineState
Definition: PerfectCacheMemory.hh:57
gem5::ruby::PerfectCacheMemory::cacheProbe
Addr cacheProbe(Addr newAddress) const
Definition: PerfectCacheMemory.hh:167
Address.hh
gem5::ruby::PerfectCacheMemory::allocate
void allocate(Addr address)
Definition: PerfectCacheMemory.hh:147
gem5::ruby::PerfectCacheMemory::changePermission
void changePermission(Addr address, AccessPermission new_perm)
Definition: PerfectCacheMemory.hh:198
gem5::ruby::PerfectCacheMemory::getPermission
AccessPermission getPermission(Addr address) const
Definition: PerfectCacheMemory.hh:191
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::ruby::PerfectCacheMemory::PerfectCacheMemory
PerfectCacheMemory()
Definition: PerfectCacheMemory.hh:124

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