gem5  v22.1.0.0
PerfectSwitch.hh
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1 /*
2  * Copyright (c) 2021 ARM Limited
3  * All rights reserved.
4  *
5  * The license below extends only to copyright in the software and shall
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13  *
14  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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40 
41 /*
42  * Perfect switch, of course it is perfect and no latency or what so
43  * ever. Every cycle it is woke up and perform all the necessary
44  * routings that must be done. Note, this switch also has number of
45  * input ports/output ports and has a routing table as well.
46  */
47 
48 #ifndef __MEM_RUBY_NETWORK_SIMPLE_PERFECTSWITCH_HH__
49 #define __MEM_RUBY_NETWORK_SIMPLE_PERFECTSWITCH_HH__
50 
51 #include <iostream>
52 #include <string>
53 #include <vector>
54 
57 
58 namespace gem5
59 {
60 
61 namespace ruby
62 {
63 
64 class MessageBuffer;
65 class NetDest;
66 class SimpleNetwork;
67 class Switch;
68 
69 class PerfectSwitch : public Consumer
70 {
71  public:
72  PerfectSwitch(SwitchID sid, Switch *, uint32_t);
74 
75  std::string name()
76  { return csprintf("PerfectSwitch-%i", m_switch_id); }
77 
78  void init(SimpleNetwork *);
79  void addInPort(const std::vector<MessageBuffer*>& in);
81  const NetDest& routing_table_entry,
82  const PortDirection &dst_inport,
83  Tick routing_latency,
84  int link_weight);
85 
86  int getInLinks() const { return m_in.size(); }
87  int getOutLinks() const { return m_out.size(); }
88 
89  void wakeup();
90  void storeEventInfo(int info);
91 
92  void clearStats();
93  void collateStats();
94  void print(std::ostream& out) const;
95 
96  private:
97  // Private copy constructor and assignment operator
100 
101  void operateVnet(int vnet);
102  void operateMessageBuffer(MessageBuffer *b, int vnet);
103 
105  Switch * const m_switch;
106 
107  // Vector of queues associated to each port.
109 
110  // Each output port also has a latency for routing to that port
111  struct OutputPort
112  {
115  };
117 
118  // input ports ordered by priority; indexed by vnet first
120  // input ports grouped by priority; indexed by vnet,prio_lv
122 
123  void updatePriorityGroups(int vnet, MessageBuffer* buf);
124 
127 
130 
131  MessageBuffer* inBuffer(int in_port, int vnet) const;
132 };
133 
134 inline std::ostream&
135 operator<<(std::ostream& out, const PerfectSwitch& obj)
136 {
137  obj.print(out);
138  out << std::flush;
139  return out;
140 }
141 
142 } // namespace ruby
143 } // namespace gem5
144 
145 #endif // __MEM_RUBY_NETWORK_SIMPLE_PERFECTSWITCH_HH__
PerfectSwitch & operator=(const PerfectSwitch &obj)
void init(SimpleNetwork *)
void addOutPort(const std::vector< MessageBuffer * > &out, const NetDest &routing_table_entry, const PortDirection &dst_inport, Tick routing_latency, int link_weight)
std::vector< std::vector< MessageBuffer * > > m_in_prio
std::vector< std::vector< MessageBuffer * > > m_in
void storeEventInfo(int info)
std::vector< int > m_pending_message_count
std::vector< OutputPort > m_out
std::vector< std::vector< std::vector< MessageBuffer * > > > m_in_prio_groups
SimpleNetwork * m_network_ptr
PerfectSwitch(SwitchID sid, Switch *, uint32_t)
void print(std::ostream &out) const
MessageBuffer * inBuffer(int in_port, int vnet) const
PerfectSwitch(const PerfectSwitch &obj)
void updatePriorityGroups(int vnet, MessageBuffer *buf)
void addInPort(const std::vector< MessageBuffer * > &in)
void operateMessageBuffer(MessageBuffer *b, int vnet)
STL vector class.
Definition: stl.hh:37
Bitfield< 7 > b
Definition: misc_types.hh:388
unsigned int SwitchID
Definition: TypeDefines.hh:43
std::string PortDirection
Definition: TypeDefines.hh:44
std::ostream & operator<<(std::ostream &os, const BoolVec &myvector)
Definition: BoolVec.cc:49
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint64_t Tick
Tick count type.
Definition: types.hh:58
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
std::vector< MessageBuffer * > buffers

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