gem5 v24.0.0.0
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PerfectSwitch.hh
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1/*
2 * Copyright (c) 2021 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 */
40
41/*
42 * Perfect switch, of course it is perfect and no latency or what so
43 * ever. Every cycle it is woke up and perform all the necessary
44 * routings that must be done. Note, this switch also has number of
45 * input ports/output ports and has a routing table as well.
46 */
47
48#ifndef __MEM_RUBY_NETWORK_SIMPLE_PERFECTSWITCH_HH__
49#define __MEM_RUBY_NETWORK_SIMPLE_PERFECTSWITCH_HH__
50
51#include <iostream>
52#include <string>
53#include <vector>
54
57
58namespace gem5
59{
60
61namespace ruby
62{
63
64class MessageBuffer;
65class NetDest;
66class SimpleNetwork;
67class Switch;
68
69class PerfectSwitch : public Consumer
70{
71 public:
72 PerfectSwitch(SwitchID sid, Switch *, uint32_t);
74
75 std::string name()
76 { return csprintf("PerfectSwitch-%i", m_switch_id); }
77
78 void init(SimpleNetwork *);
81 const NetDest& routing_table_entry,
82 const PortDirection &dst_inport,
83 Tick routing_latency,
84 int link_weight);
85
86 int getInLinks() const { return m_in.size(); }
87 int getOutLinks() const { return m_out.size(); }
88
89 void wakeup();
90 void storeEventInfo(int info);
91
92 void clearStats();
93 void collateStats();
94 void print(std::ostream& out) const;
95
96 private:
97 // Private copy constructor and assignment operator
100
101 void operateVnet(int vnet);
102 void operateMessageBuffer(MessageBuffer *b, int vnet);
103
106
107 // Vector of queues associated to each port.
109
110 // Each output port also has a latency for routing to that port
117
118 // input ports ordered by priority; indexed by vnet first
120 // input ports grouped by priority; indexed by vnet,prio_lv
122
123 void updatePriorityGroups(int vnet, MessageBuffer* buf);
124
127
130
131 MessageBuffer* inBuffer(int in_port, int vnet) const;
132};
133
134inline std::ostream&
135operator<<(std::ostream& out, const PerfectSwitch& obj)
136{
137 obj.print(out);
138 out << std::flush;
139 return out;
140}
141
142} // namespace ruby
143} // namespace gem5
144
145#endif // __MEM_RUBY_NETWORK_SIMPLE_PERFECTSWITCH_HH__
void addOutPort(const std::vector< MessageBuffer * > &out, const NetDest &routing_table_entry, const PortDirection &dst_inport, Tick routing_latency, int link_weight)
std::vector< std::vector< MessageBuffer * > > m_in_prio
std::vector< std::vector< MessageBuffer * > > m_in
std::vector< int > m_pending_message_count
std::vector< OutputPort > m_out
PerfectSwitch & operator=(const PerfectSwitch &obj)
std::vector< std::vector< std::vector< MessageBuffer * > > > m_in_prio_groups
SimpleNetwork * m_network_ptr
PerfectSwitch(SwitchID sid, Switch *, uint32_t)
void print(std::ostream &out) const
MessageBuffer * inBuffer(int in_port, int vnet) const
PerfectSwitch(const PerfectSwitch &obj)
void updatePriorityGroups(int vnet, MessageBuffer *buf)
void addInPort(const std::vector< MessageBuffer * > &in)
void operateMessageBuffer(MessageBuffer *b, int vnet)
STL vector class.
Definition stl.hh:37
Bitfield< 7 > b
unsigned int SwitchID
std::string PortDirection
std::ostream & operator<<(std::ostream &os, const BoolVec &myvector)
Definition BoolVec.cc:49
const FlagsType init
This Stat is Initialized.
Definition info.hh:55
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint64_t Tick
Tick count type.
Definition types.hh:58
std::string csprintf(const char *format, const Args &...args)
Definition cprintf.hh:161
std::vector< MessageBuffer * > buffers

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