gem5  v21.1.0.2
PerfectSwitch.hh
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1 /*
2  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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28 
29 /*
30  * Perfect switch, of course it is perfect and no latency or what so
31  * ever. Every cycle it is woke up and perform all the necessary
32  * routings that must be done. Note, this switch also has number of
33  * input ports/output ports and has a routing table as well.
34  */
35 
36 #ifndef __MEM_RUBY_NETWORK_SIMPLE_PERFECTSWITCH_HH__
37 #define __MEM_RUBY_NETWORK_SIMPLE_PERFECTSWITCH_HH__
38 
39 #include <iostream>
40 #include <string>
41 #include <vector>
42 
45 
46 namespace gem5
47 {
48 
49 namespace ruby
50 {
51 
52 class MessageBuffer;
53 class NetDest;
54 class SimpleNetwork;
55 class Switch;
56 
57 struct LinkOrder
58 {
59  int m_link;
60  int m_value;
61 };
62 
63 bool operator<(const LinkOrder& l1, const LinkOrder& l2);
64 
65 class PerfectSwitch : public Consumer
66 {
67  public:
68  PerfectSwitch(SwitchID sid, Switch *, uint32_t);
70 
71  std::string name()
72  { return csprintf("PerfectSwitch-%i", m_switch_id); }
73 
74  void init(SimpleNetwork *);
75  void addInPort(const std::vector<MessageBuffer*>& in);
77  const NetDest& routing_table_entry);
78 
79  int getInLinks() const { return m_in.size(); }
80  int getOutLinks() const { return m_out.size(); }
81 
82  void wakeup();
83  void storeEventInfo(int info);
84 
85  void clearStats();
86  void collateStats();
87  void print(std::ostream& out) const;
88 
89  private:
90  // Private copy constructor and assignment operator
91  PerfectSwitch(const PerfectSwitch& obj);
93 
94  void operateVnet(int vnet);
95  void operateMessageBuffer(MessageBuffer *b, int incoming, int vnet);
96 
98  Switch * const m_switch;
99 
100  // vector of queues from the components
103 
106 
110 
113 };
114 
115 inline std::ostream&
116 operator<<(std::ostream& out, const PerfectSwitch& obj)
117 {
118  obj.print(out);
119  out << std::flush;
120  return out;
121 }
122 
123 } // namespace ruby
124 } // namespace gem5
125 
126 #endif // __MEM_RUBY_NETWORK_SIMPLE_PERFECTSWITCH_HH__
gem5::ruby::PerfectSwitch::m_out
std::vector< std::vector< MessageBuffer * > > m_out
Definition: PerfectSwitch.hh:102
gem5::ruby::PerfectSwitch::m_round_robin_start
int m_round_robin_start
Definition: PerfectSwitch.hh:108
gem5::ruby::PerfectSwitch::m_switch
Switch *const m_switch
Definition: PerfectSwitch.hh:98
gem5::ruby::PerfectSwitch::operateMessageBuffer
void operateMessageBuffer(MessageBuffer *b, int incoming, int vnet)
Definition: PerfectSwitch.cc:144
gem5::ruby::PerfectSwitch::name
std::string name()
Definition: PerfectSwitch.hh:71
gem5::ruby::PerfectSwitch::clearStats
void clearStats()
Definition: PerfectSwitch.cc:321
gem5::ruby::operator<<
std::ostream & operator<<(std::ostream &os, const BoolVec &myvector)
Definition: BoolVec.cc:49
gem5::ruby::PerfectSwitch::m_wakeups_wo_switch
int m_wakeups_wo_switch
Definition: PerfectSwitch.hh:109
gem5::ruby::SimpleNetwork
Definition: SimpleNetwork.hh:61
std::vector
STL vector class.
Definition: stl.hh:37
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::ruby::Consumer
Definition: Consumer.hh:61
gem5::ruby::PerfectSwitch
Definition: PerfectSwitch.hh:65
gem5::ruby::PerfectSwitch::m_routing_table
std::vector< NetDest > m_routing_table
Definition: PerfectSwitch.hh:104
gem5::ruby::PerfectSwitch::collateStats
void collateStats()
Definition: PerfectSwitch.cc:325
gem5::ruby::Switch
Definition: Switch.hh:77
gem5::ruby::LinkOrder::m_link
int m_link
Definition: PerfectSwitch.hh:59
gem5::ruby::PerfectSwitch::addInPort
void addInPort(const std::vector< MessageBuffer * > &in)
Definition: PerfectSwitch.cc:76
gem5::ArmISA::b
Bitfield< 7 > b
Definition: misc_types.hh:381
gem5::ruby::PerfectSwitch::init
void init(SimpleNetwork *)
Definition: PerfectSwitch.cc:66
gem5::ruby::PerfectSwitch::m_in
std::vector< std::vector< MessageBuffer * > > m_in
Definition: PerfectSwitch.hh:101
TypeDefines.hh
gem5::ruby::PerfectSwitch::m_switch_id
const SwitchID m_switch_id
Definition: PerfectSwitch.hh:97
gem5::ruby::PerfectSwitch::m_pending_message_count
std::vector< int > m_pending_message_count
Definition: PerfectSwitch.hh:112
gem5::ruby::PerfectSwitch::getInLinks
int getInLinks() const
Definition: PerfectSwitch.hh:79
gem5::ruby::PerfectSwitch::getOutLinks
int getOutLinks() const
Definition: PerfectSwitch.hh:80
gem5::ruby::SwitchID
unsigned int SwitchID
Definition: TypeDefines.hh:41
gem5::ruby::operator<
bool operator<(const LinkOrder &l1, const LinkOrder &l2)
Definition: PerfectSwitch.cc:52
gem5::ruby::PerfectSwitch::m_network_ptr
SimpleNetwork * m_network_ptr
Definition: PerfectSwitch.hh:111
gem5::ruby::NetDest
Definition: NetDest.hh:45
gem5::ruby::PerfectSwitch::m_virtual_networks
uint32_t m_virtual_networks
Definition: PerfectSwitch.hh:107
gem5::ruby::LinkOrder
Definition: PerfectSwitch.hh:57
gem5::ruby::PerfectSwitch::~PerfectSwitch
~PerfectSwitch()
Definition: PerfectSwitch.cc:105
gem5::ruby::PerfectSwitch::print
void print(std::ostream &out) const
Definition: PerfectSwitch.cc:331
Consumer.hh
gem5::ruby::PerfectSwitch::operateVnet
void operateVnet(int vnet)
Definition: PerfectSwitch.cc:110
gem5::ruby::PerfectSwitch::operator=
PerfectSwitch & operator=(const PerfectSwitch &obj)
gem5::ruby::PerfectSwitch::PerfectSwitch
PerfectSwitch(SwitchID sid, Switch *, uint32_t)
Definition: PerfectSwitch.cc:57
gem5::ruby::PerfectSwitch::wakeup
void wakeup()
Definition: PerfectSwitch.cc:290
gem5::ruby::LinkOrder::m_value
int m_value
Definition: PerfectSwitch.hh:60
gem5::X86ISA::l1
Bitfield< 2 > l1
Definition: misc.hh:664
gem5::ruby::PerfectSwitch::storeEventInfo
void storeEventInfo(int info)
Definition: PerfectSwitch.cc:315
gem5::ruby::MessageBuffer
Definition: MessageBuffer.hh:74
gem5::ruby::PerfectSwitch::m_link_order
std::vector< LinkOrder > m_link_order
Definition: PerfectSwitch.hh:105
gem5::ruby::PerfectSwitch::addOutPort
void addOutPort(const std::vector< MessageBuffer * > &out, const NetDest &routing_table_entry)
Definition: PerfectSwitch.cc:91
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::X86ISA::l2
Bitfield< 4 > l2
Definition: misc.hh:666

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