RubyTester.hh

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/*
 * Copyright (c) 2013 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
 * Copyright (c) 2009 Advanced Micro Devices, Inc.
 * All rights reserved.
 *
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 * modification, are permitted provided that the following conditions are
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#ifndef __CPU_RUBYTEST_RUBYTESTER_HH__
#define __CPU_RUBYTEST_RUBYTESTER_HH__
 
#include <iostream>
#include <string>
#include <vector>
 
#include "cpu/testers/rubytest/CheckTable.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
#include "mem/ruby/common/SubBlock.hh"
#include "mem/ruby/common/TypeDefines.hh"
#include "params/RubyTester.hh"
#include "sim/clocked_object.hh"
 
namespace gem5
{
 
class RubyTester : public ClockedObject
{
  public:
    class CpuPort : public RequestPort
    {
      private:
        RubyTester *tester;
        // index for m_last_progress_vector and hitCallback
        PortID globalIdx;
 
      public:
        //
        // Currently, each instatiation of the RubyTester::CpuPort supports
        // only instruction or data requests, not both.  However, for those
        // RubyPorts that support both types of requests, separate InstOnly
        // and DataOnly CpuPorts will map to that RubyPort
 
        CpuPort(const std::string &_name, RubyTester *_tester, PortID _id,
                PortID _index)
            : RequestPort(_name, _tester, _id), tester(_tester),
              globalIdx(_index)
        {}
 
      protected:
        virtual bool recvTimingResp(PacketPtr pkt);
        virtual void recvReqRetry()
        { panic("%s does not expect a retry\n", name()); }
    };
 
    struct SenderState : public Packet::SenderState
    {
        ruby::SubBlock subBlock;
 
        SenderState(Addr addr, int size) : subBlock(addr, size) {}
 
    };
 
    typedef RubyTesterParams Params;
    RubyTester(const Params &p);
    ~RubyTester();
 
    Port &getPort(const std::string &if_name,
                  PortID idx=InvalidPortID) override;
 
    bool isInstOnlyCpuPort(int idx);
    bool isInstDataCpuPort(int idx);
 
    RequestPort* getReadableCpuPort(int idx);
    RequestPort* getWritableCpuPort(int idx);
 
    void init() override;
 
    void wakeup();
 
    void incrementCheckCompletions() { m_checks_completed++; }
 
    void printStats(std::ostream& out) const {}
    void clearStats() {}
    void printConfig(std::ostream& out) const {}
 
    void print(std::ostream& out) const;
    bool getCheckFlush() { return m_check_flush; }
 
    RequestorID requestorId() { return _requestorId; }
  protected:
    EventFunctionWrapper checkStartEvent;
 
    RequestorID _requestorId;
 
  private:
    void hitCallback(ruby::NodeID proc, ruby::SubBlock* data);
 
    void checkForDeadlock();
 
    // Private copy constructor and assignment operator
    RubyTester(const RubyTester& obj);
    RubyTester& operator=(const RubyTester& obj);
 
    CheckTable* m_checkTable_ptr;
    std::vector<Cycles> m_last_progress_vector;
 
    int m_num_cpus;
    uint64_t m_checks_completed;
    std::vector<RequestPort*> writePorts;
    std::vector<RequestPort*> readPorts;
    uint64_t m_checks_to_complete;
    int m_deadlock_threshold;
    int m_num_writers;
    int m_num_readers;
    int m_wakeup_frequency;
    bool m_check_flush;
    int m_num_inst_only_ports;
    int m_num_inst_data_ports;
};
 
inline std::ostream&
operator<<(std::ostream& out, const RubyTester& obj)
{
    obj.print(out);
    out << std::flush;
    return out;
}
 
} // namespace gem5
 
#endif // __CPU_RUBYTEST_RUBYTESTER_HH__