gem5  v21.1.0.2
RubyTester.cc
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41 
43 
44 #include "base/logging.hh"
45 #include "base/trace.hh"
47 #include "debug/RubyTest.hh"
49 #include "sim/sim_exit.hh"
50 #include "sim/system.hh"
51 
52 namespace gem5
53 {
54 
56  : ClockedObject(p),
57  checkStartEvent([this]{ wakeup(); }, "RubyTester tick",
58  false, Event::CPU_Tick_Pri),
59  _requestorId(p.system->getRequestorId(this)),
60  m_checkTable_ptr(nullptr),
61  m_num_cpus(p.num_cpus),
62  m_checks_to_complete(p.checks_to_complete),
63  m_deadlock_threshold(p.deadlock_threshold),
64  m_num_writers(0),
65  m_num_readers(0),
66  m_wakeup_frequency(p.wakeup_frequency),
67  m_check_flush(p.check_flush),
68  m_num_inst_only_ports(p.port_cpuInstPort_connection_count),
69  m_num_inst_data_ports(p.port_cpuInstDataPort_connection_count)
70 {
71  m_checks_completed = 0;
72 
73  //
74  // Create the requested inst and data ports and place them on the
75  // appropriate read and write port lists. The reason for the subtle
76  // difference between inst and data ports vs. read and write ports is
77  // from the tester's perspective, it only needs to know whether a port
78  // supports reads (checks) or writes (actions). Meanwhile, the protocol
79  // controllers have data ports (support read and writes) or inst ports
80  // (support only reads).
81  // Note: the inst ports are the lowest elements of the readPort vector,
82  // then the data ports are added to the readPort vector
83  //
84  int idx = 0;
85  for (int i = 0; i < p.port_cpuInstPort_connection_count; ++i) {
86  readPorts.push_back(new CpuPort(csprintf("%s-instPort%d", name(), i),
87  this, i, idx));
88  idx++;
89  }
90  for (int i = 0; i < p.port_cpuInstDataPort_connection_count; ++i) {
91  CpuPort *port = new CpuPort(csprintf("%s-instDataPort%d", name(), i),
92  this, i, idx);
93  readPorts.push_back(port);
94  writePorts.push_back(port);
95  idx++;
96  }
97  for (int i = 0; i < p.port_cpuDataPort_connection_count; ++i) {
98  CpuPort *port = new CpuPort(csprintf("%s-dataPort%d", name(), i),
99  this, i, idx);
100  readPorts.push_back(port);
101  writePorts.push_back(port);
102  idx++;
103  }
104 
105  // add the check start event to the event queue
106  schedule(checkStartEvent, 1);
107 }
108 
110 {
111  delete m_checkTable_ptr;
112  // Only delete the readPorts since the writePorts are just a subset
113  for (int i = 0; i < readPorts.size(); i++)
114  delete readPorts[i];
115 }
116 
117 void
119 {
120  assert(writePorts.size() > 0 && readPorts.size() > 0);
121 
123  for (int i = 0; i < m_last_progress_vector.size(); i++) {
125  }
126 
127  m_num_writers = writePorts.size();
128  m_num_readers = readPorts.size();
129  assert(m_num_readers == m_num_cpus);
130 
132 }
133 
134 Port &
135 RubyTester::getPort(const std::string &if_name, PortID idx)
136 {
137  if (if_name != "cpuInstPort" && if_name != "cpuInstDataPort" &&
138  if_name != "cpuDataPort") {
139  // pass it along to our super class
140  return ClockedObject::getPort(if_name, idx);
141  } else {
142  if (if_name == "cpuInstPort") {
143  if (idx > m_num_inst_only_ports) {
144  panic("RubyTester::getPort: unknown inst port %d\n",
145  idx);
146  }
147  //
148  // inst ports map to the lowest readPort elements
149  //
150  return *readPorts[idx];
151  } else if (if_name == "cpuInstDataPort") {
152  if (idx > m_num_inst_data_ports) {
153  panic("RubyTester::getPort: unknown inst+data port %d\n",
154  idx);
155  }
156  int read_idx = idx + m_num_inst_only_ports;
157  //
158  // inst+data ports map to the next readPort elements
159  //
160  return *readPorts[read_idx];
161  } else {
162  assert(if_name == "cpuDataPort");
163  //
164  // data only ports map to the final readPort elements
165  //
166  if (idx > (static_cast<int>(readPorts.size()) -
168  panic("RubyTester::getPort: unknown data port %d\n",
169  idx);
170  }
171  int read_idx = idx + m_num_inst_only_ports + m_num_inst_data_ports;
172  return *readPorts[read_idx];
173  }
174  // Note: currently the Ruby Tester does not support write only ports
175  // but that could easily be added here
176  }
177 }
178 
179 bool
181 {
182  // retrieve the subblock and call hitCallback
183  RubyTester::SenderState* senderState =
184  safe_cast<RubyTester::SenderState*>(pkt->senderState);
185  ruby::SubBlock& subblock = senderState->subBlock;
186 
187  tester->hitCallback(globalIdx, &subblock);
188 
189  // Now that the tester has completed, delete the senderState
190  // (includes sublock) and the packet, then return
191  delete pkt->senderState;
192  delete pkt;
193  return true;
194 }
195 
196 bool
198 {
199  return idx < m_num_inst_only_ports;
200 }
201 
202 bool
204 {
205  return ((idx >= m_num_inst_only_ports) &&
207 }
208 
211 {
212  assert(idx >= 0 && idx < readPorts.size());
213 
214  return readPorts[idx];
215 }
216 
219 {
220  assert(idx >= 0 && idx < writePorts.size());
221 
222  return writePorts[idx];
223 }
224 
225 void
227 {
228  // Mark that we made progress
230 
231  DPRINTF(RubyTest, "completed request for proc: %d", proc);
232  DPRINTFR(RubyTest, " addr: 0x%x, size: %d, data: ",
233  data->getAddress(), data->getSize());
234  for (int byte = 0; byte < data->getSize(); byte++) {
235  DPRINTFR(RubyTest, "%d ", data->getByte(byte));
236  }
237  DPRINTFR(RubyTest, "\n");
238 
239  // This tells us our store has 'completed' or for a load gives us
240  // back the data to make the check
241  Check* check_ptr = m_checkTable_ptr->getCheck(data->getAddress());
242  assert(check_ptr != NULL);
243  check_ptr->performCallback(proc, data, curCycle());
244 }
245 
246 void
248 {
250  // Try to perform an action or check
251  Check* check_ptr = m_checkTable_ptr->getRandomCheck();
252  assert(check_ptr != NULL);
253  check_ptr->initiate();
254 
256 
258  } else {
259  exitSimLoop("Ruby Tester completed");
260  }
261 }
262 
263 void
265 {
266  int size = m_last_progress_vector.size();
267  Cycles current_time = curCycle();
268  for (int processor = 0; processor < size; processor++) {
269  if ((current_time - m_last_progress_vector[processor]) >
271  panic("Deadlock detected: current_time: %d last_progress_time: %d "
272  "difference: %d processor: %d\n",
273  current_time, m_last_progress_vector[processor],
274  current_time - m_last_progress_vector[processor], processor);
275  }
276  }
277 }
278 
279 void
280 RubyTester::print(std::ostream& out) const
281 {
282  out << "[RubyTester]" << std::endl;
283 }
284 
285 } // namespace gem5
gem5::RubyTester::getWritableCpuPort
RequestPort * getWritableCpuPort(int idx)
Definition: RubyTester.cc:218
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::RubyTester::CpuPort::globalIdx
PortID globalIdx
Definition: RubyTester.hh:68
gem5::RubyTester::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: RubyTester.cc:118
gem5::SimObject::getPort
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Definition: sim_object.cc:126
gem5::RubyTester::hitCallback
void hitCallback(ruby::NodeID proc, ruby::SubBlock *data)
Definition: RubyTester.cc:226
gem5::RubyTester::m_last_progress_vector
std::vector< Cycles > m_last_progress_vector
Definition: RubyTester.hh:139
gem5::RubyTester::m_deadlock_threshold
int m_deadlock_threshold
Definition: RubyTester.hh:146
system.hh
gem5::CheckTable::getRandomCheck
Check * getRandomCheck()
Definition: CheckTable.cc:114
DPRINTFR
#define DPRINTFR(x,...)
Definition: trace.hh:200
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::Clocked::curCycle
Cycles curCycle() const
Determine the current cycle, corresponding to a tick aligned to a clock edge.
Definition: clocked_object.hh:195
gem5::RubyTester::getReadableCpuPort
RequestPort * getReadableCpuPort(int idx)
Definition: RubyTester.cc:210
gem5::RubyTester::m_num_inst_only_ports
int m_num_inst_only_ports
Definition: RubyTester.hh:151
gem5::Check
Definition: Check.hh:51
gem5::RubyTester::print
void print(std::ostream &out) const
Definition: RubyTester.cc:280
gem5::ruby::SubBlock
Definition: SubBlock.hh:44
gem5::EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1019
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::RubyTester::isInstDataCpuPort
bool isInstDataCpuPort(int idx)
Definition: RubyTester.cc:203
gem5::RubyTester::m_wakeup_frequency
int m_wakeup_frequency
Definition: RubyTester.hh:149
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
sim_exit.hh
gem5::exitSimLoop
void exitSimLoop(const std::string &message, int exit_code, Tick when, Tick repeat, bool serialize)
Schedule an event to exit the simulation loop (returning to Python) at the end of the current cycle (...
Definition: sim_events.cc:88
gem5::RubyTester::m_checks_to_complete
uint64_t m_checks_to_complete
Definition: RubyTester.hh:145
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::RubyTester::SenderState
Definition: RubyTester.hh:89
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::RubyTester::m_num_inst_data_ports
int m_num_inst_data_ports
Definition: RubyTester.hh:152
Check.hh
gem5::RubyTester::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: RubyTester.cc:135
gem5::CheckTable
Definition: CheckTable.hh:45
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::RubyTester::RubyTester
RubyTester(const Params &p)
Definition: RubyTester.cc:55
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::RubyTester::isInstOnlyCpuPort
bool isInstOnlyCpuPort(int idx)
Definition: RubyTester.cc:197
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::RubyTester::CpuPort::tester
RubyTester * tester
Definition: RubyTester.hh:66
RubyTester.hh
gem5::RubyTester::CpuPort::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Definition: RubyTester.cc:180
gem5::Check::initiate
void initiate()
Definition: Check.cc:59
gem5::RubyTester::checkForDeadlock
void checkForDeadlock()
Definition: RubyTester.cc:264
gem5::RubyTester::Params
RubyTesterParams Params
Definition: RubyTester.hh:97
gem5::Packet::senderState
SenderState * senderState
This packet's sender state.
Definition: packet.hh:534
name
const std::string & name()
Definition: trace.cc:49
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::RubyTester::wakeup
void wakeup()
Definition: RubyTester.cc:247
gem5::RubyTester::writePorts
std::vector< RequestPort * > writePorts
Definition: RubyTester.hh:143
gem5::RubyTester::m_checkTable_ptr
CheckTable * m_checkTable_ptr
Definition: RubyTester.hh:138
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
logging.hh
gem5::RubyTester::checkStartEvent
EventFunctionWrapper checkStartEvent
Definition: RubyTester.hh:125
gem5::RubyTester::m_num_readers
int m_num_readers
Definition: RubyTester.hh:148
gem5::ruby::NodeID
unsigned int NodeID
Definition: TypeDefines.hh:40
trace.hh
gem5::RubyTester::readPorts
std::vector< RequestPort * > readPorts
Definition: RubyTester.hh:144
gem5::EventBase::CPU_Tick_Pri
static const Priority CPU_Tick_Pri
CPU ticks must come after other associated CPU events (such as writebacks).
Definition: eventq.hh:204
gem5::RubyTester::m_num_cpus
int m_num_cpus
Definition: RubyTester.hh:141
gem5::Check::performCallback
void performCallback(ruby::NodeID proc, ruby::SubBlock *data, Cycles curTime)
Definition: Check.cc:287
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::RubyTester::m_checks_completed
uint64_t m_checks_completed
Definition: RubyTester.hh:142
gem5::RubyTester::SenderState::subBlock
ruby::SubBlock subBlock
Definition: RubyTester.hh:91
gem5::CheckTable::getCheck
Check * getCheck(Addr address)
Definition: CheckTable.cc:121
SubBlock.hh
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::RubyTester::m_num_writers
int m_num_writers
Definition: RubyTester.hh:147
gem5::RubyTester::~RubyTester
~RubyTester()
Definition: RubyTester.cc:109

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