47#include "debug/RubyTest.hh"
57 checkStartEvent([this]{
wakeup(); },
"RubyTester tick",
59 _requestorId(
p.system->getRequestorId(
this)),
60 m_checkTable_ptr(
nullptr),
61 m_num_cpus(
p.num_cpus),
62 m_checks_to_complete(
p.checks_to_complete),
63 m_deadlock_threshold(
p.deadlock_threshold),
66 m_wakeup_frequency(
p.wakeup_frequency),
67 m_check_flush(
p.check_flush),
68 m_num_inst_only_ports(
p.port_cpuInstPort_connection_count),
69 m_num_inst_data_ports(
p.port_cpuInstDataPort_connection_count)
71 m_checks_completed = 0;
85 for (
int i = 0;
i <
p.port_cpuInstPort_connection_count; ++
i) {
86 readPorts.push_back(
new CpuPort(
csprintf(
"%s-instPort%d",
name(),
i),
90 for (
int i = 0;
i <
p.port_cpuInstDataPort_connection_count; ++
i) {
91 CpuPort *port =
new CpuPort(
csprintf(
"%s-instDataPort%d",
name(),
i),
93 readPorts.push_back(port);
94 writePorts.push_back(port);
97 for (
int i = 0;
i <
p.port_cpuDataPort_connection_count; ++
i) {
98 CpuPort *port =
new CpuPort(
csprintf(
"%s-dataPort%d",
name(),
i),
100 readPorts.push_back(port);
101 writePorts.push_back(port);
106 schedule(checkStartEvent, 1);
137 if (if_name !=
"cpuInstPort" && if_name !=
"cpuInstDataPort" &&
138 if_name !=
"cpuDataPort") {
142 if (if_name ==
"cpuInstPort") {
144 panic(
"RubyTester::getPort: unknown inst port %d\n",
151 }
else if (if_name ==
"cpuInstDataPort") {
153 panic(
"RubyTester::getPort: unknown inst+data port %d\n",
162 assert(if_name ==
"cpuDataPort");
166 if (idx > (
static_cast<int>(
readPorts.size()) -
168 panic(
"RubyTester::getPort: unknown data port %d\n",
212 assert(idx >= 0 && idx <
readPorts.size());
231 DPRINTF(RubyTest,
"completed request for proc: %d", proc);
232 DPRINTFR(RubyTest,
" addr: 0x%x, size: %d, data: ",
233 data->getAddress(),
data->getSize());
234 for (
int byte = 0;
byte <
data->getSize();
byte++) {
242 assert(check_ptr != NULL);
252 assert(check_ptr != NULL);
268 for (
int processor = 0; processor < size; processor++) {
271 panic(
"Deadlock detected: current_time: %d last_progress_time: %d "
272 "difference: %d processor: %d\n",
282 out <<
"[RubyTester]" << std::endl;
Check * getCheck(Addr address)
void performCallback(ruby::NodeID proc, ruby::SubBlock *data, Cycles curTime)
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Cycles curCycle() const
Determine the current cycle, corresponding to a tick aligned to a clock edge.
Cycles is a wrapper class for representing cycle counts, i.e.
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
SenderState * senderState
This packet's sender state.
Ports are used to interface objects to each other.
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
virtual bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
EventFunctionWrapper checkStartEvent
std::vector< RequestPort * > readPorts
bool isInstOnlyCpuPort(int idx)
RequestPort * getWritableCpuPort(int idx)
void hitCallback(ruby::NodeID proc, ruby::SubBlock *data)
int m_num_inst_only_ports
RubyTester(const Params &p)
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
bool isInstDataCpuPort(int idx)
std::vector< RequestPort * > writePorts
RequestPort * getReadableCpuPort(int idx)
uint64_t m_checks_to_complete
int m_num_inst_data_ports
CheckTable * m_checkTable_ptr
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
uint64_t m_checks_completed
std::vector< Cycles > m_last_progress_vector
void print(std::ostream &out) const
void schedule(Event &event, Tick when)
static const Priority CPU_Tick_Pri
CPU ticks must come after other associated CPU events (such as writebacks).
#define panic(...)
This implements a cprintf based panic() function.
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
T safe_cast(U &&ref_or_ptr)
Tick curTick()
The universal simulation clock.
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
void exitSimLoop(const std::string &message, int exit_code, Tick when, Tick repeat, bool serialize)
Schedule an event to exit the simulation loop (returning to Python) at the end of the current cycle (...
std::string csprintf(const char *format, const Args &...args)
const std::string & name()