gem5  v21.1.0.2
apic.hh
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28 
29 #ifndef __ARCH_X86_APICREGS_HH__
30 #define __ARCH_X86_APICREGS_HH__
31 
32 #include "base/bitunion.hh"
33 
34 namespace gem5
35 {
36 
37 namespace X86ISA
38 {
40  {
50 
52 
54 
56 
69 
71 
73  };
74 
75  static inline ApicRegIndex
77  {
79  }
80 
81  static inline ApicRegIndex
83  {
85  }
86 
87  static inline ApicRegIndex
89  {
91  }
92 
93  BitUnion32(InterruptCommandRegLow)
94  Bitfield<7, 0> vector;
95  Bitfield<10, 8> deliveryMode;
96  Bitfield<11> destMode;
97  Bitfield<12> deliveryStatus;
98  Bitfield<14> level;
99  Bitfield<15> trigger;
100  Bitfield<19, 18> destShorthand;
101  EndBitUnion(InterruptCommandRegLow)
102 
103  BitUnion32(InterruptCommandRegHigh)
104  Bitfield<31, 24> destination;
105  EndBitUnion(InterruptCommandRegHigh)
106 
107 } // namespace X86ISA
108 } // namespace gem5
109 
110 #endif
gem5::X86ISA::level
Bitfield< 20 > level
Definition: intmessage.hh:51
gem5::X86ISA::APIC_INTERRUPT_COMMAND_LOW
@ APIC_INTERRUPT_COMMAND_LOW
Definition: apic.hh:58
gem5::X86ISA::APIC_LOGICAL_DESTINATION
@ APIC_LOGICAL_DESTINATION
Definition: apic.hh:47
gem5::X86ISA::APIC_LVT_LINT1
@ APIC_LVT_LINT1
Definition: apic.hh:64
gem5::X86ISA::APIC_INTERRUPT_COMMAND_HIGH
@ APIC_INTERRUPT_COMMAND_HIGH
Definition: apic.hh:59
gem5::X86ISA::vector
Bitfield< 15, 8 > vector
Definition: intmessage.hh:48
gem5::X86ISA::ApicRegIndex
ApicRegIndex
Definition: apic.hh:39
gem5::X86ISA::APIC_LVT_LINT0
@ APIC_LVT_LINT0
Definition: apic.hh:63
gem5::X86ISA::APIC_ERROR_STATUS
@ APIC_ERROR_STATUS
Definition: apic.hh:57
gem5::X86ISA::APIC_CURRENT_COUNT
@ APIC_CURRENT_COUNT
Definition: apic.hh:67
gem5::X86ISA::APIC_SPURIOUS_INTERRUPT_VECTOR
@ APIC_SPURIOUS_INTERRUPT_VECTOR
Definition: apic.hh:49
gem5::X86ISA::APIC_TRIGGER_MODE
static ApicRegIndex APIC_TRIGGER_MODE(int index)
Definition: apic.hh:82
gem5::X86ISA::APIC_DIVIDE_CONFIGURATION
@ APIC_DIVIDE_CONFIGURATION
Definition: apic.hh:68
gem5::X86ISA::APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
@ APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
Definition: apic.hh:62
gem5::X86ISA::destination
destination
Definition: intmessage.hh:47
gem5::X86ISA::APIC_ARBITRATION_PRIORITY
@ APIC_ARBITRATION_PRIORITY
Definition: apic.hh:44
gem5::X86ISA::APIC_TRIGGER_MODE_BASE
@ APIC_TRIGGER_MODE_BASE
Definition: apic.hh:53
gem5::X86ISA::APIC_LVT_THERMAL_SENSOR
@ APIC_LVT_THERMAL_SENSOR
Definition: apic.hh:61
gem5::X86ISA::destShorthand
Bitfield< 19, 18 > destShorthand
Definition: apic.hh:100
gem5::X86ISA::APIC_INTERNAL_STATE
@ APIC_INTERNAL_STATE
Definition: apic.hh:70
gem5::X86ISA::APIC_LVT_TIMER
@ APIC_LVT_TIMER
Definition: apic.hh:60
bitunion.hh
gem5::X86ISA::APIC_EOI
@ APIC_EOI
Definition: apic.hh:46
gem5::X86ISA::APIC_INTERRUPT_REQUEST_BASE
@ APIC_INTERRUPT_REQUEST_BASE
Definition: apic.hh:55
gem5::X86ISA::APIC_INTERRUPT_REQUEST
static ApicRegIndex APIC_INTERRUPT_REQUEST(int index)
Definition: apic.hh:88
gem5::X86ISA::destMode
Bitfield< 19 > destMode
Definition: intmessage.hh:50
gem5::X86ISA::BitUnion32
BitUnion32(TriggerIntMessage) Bitfield< 7
gem5::X86ISA::APIC_TASK_PRIORITY
@ APIC_TASK_PRIORITY
Definition: apic.hh:43
gem5::X86ISA::APIC_PROCESSOR_PRIORITY
@ APIC_PROCESSOR_PRIORITY
Definition: apic.hh:45
gem5::X86ISA::APIC_INITIAL_COUNT
@ APIC_INITIAL_COUNT
Definition: apic.hh:66
gem5::X86ISA::index
Bitfield< 5, 3 > index
Definition: types.hh:98
gem5::X86ISA::APIC_VERSION
@ APIC_VERSION
Definition: apic.hh:42
gem5::X86ISA::APIC_IN_SERVICE_BASE
@ APIC_IN_SERVICE_BASE
Definition: apic.hh:51
gem5::X86ISA::APIC_IN_SERVICE
static ApicRegIndex APIC_IN_SERVICE(int index)
Definition: apic.hh:76
gem5::X86ISA::deliveryStatus
Bitfield< 12 > deliveryStatus
Definition: apic.hh:97
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::X86ISA::APIC_LVT_ERROR
@ APIC_LVT_ERROR
Definition: apic.hh:65
gem5::X86ISA::APIC_ID
@ APIC_ID
Definition: apic.hh:41
gem5::X86ISA::deliveryMode
Bitfield< 18, 16 > deliveryMode
Definition: intmessage.hh:49
gem5::X86ISA::EndBitUnion
EndBitUnion(TriggerIntMessage) GEM5_DEPRECATED_NAMESPACE(DeliveryMode
gem5::X86ISA::trigger
Bitfield< 21 > trigger
Definition: intmessage.hh:52
gem5::X86ISA::APIC_DESTINATION_FORMAT
@ APIC_DESTINATION_FORMAT
Definition: apic.hh:48
gem5::X86ISA::NUM_APIC_REGS
@ NUM_APIC_REGS
Definition: apic.hh:72

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