gem5 v24.0.0.0
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Go to the source code of this file.
Namespaces | |
namespace | gem5 |
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved. | |
namespace | gem5::PowerISA |
Enumerations | |
enum | gem5::PowerISA::MiscRegIndex { gem5::PowerISA::NUM_MISCREGS = 0 } |
Functions | |
constexpr RegClass | gem5::PowerISA::miscRegClass (MiscRegClass, MiscRegClassName, NUM_MISCREGS, debug::MiscRegs) |
gem5::PowerISA::BitUnion32 (Cr) SubBitUnion(cr0 | |
gem5::PowerISA::EndSubBitUnion (cr0) Bitfield< 27 | |
gem5::PowerISA::EndBitUnion (Cr) BitUnion32(Xer) Bitfield< 31 > so | |
gem5::PowerISA::EndBitUnion (Xer) BitUnion32(Fpscr) Bitfield< 31 > fx | |
gem5::PowerISA::SubBitUnion (fprf, 16, 12) Bitfield< 16 > c | |
gem5::PowerISA::SubBitUnion (fpcc, 15, 12) Bitfield< 15 > fl | |
gem5::PowerISA::EndSubBitUnion (fpcc) EndSubBitUnion(fprf) Bitfield< 10 > vxsqrt | |
gem5::PowerISA::EndBitUnion (Fpscr) BitUnion64(Msr) Bitfield< 63 > sf | |