gem5  v21.1.0.2
mem.hh
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1 /*
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29 
30 #ifndef __ARCH_RISCV_INST_MEM_HH__
31 #define __ARCH_RISCV_INST_MEM_HH__
32 
33 #include <string>
34 
36 #include "cpu/exec_context.hh"
37 #include "cpu/static_inst.hh"
38 
39 namespace gem5
40 {
41 
42 namespace RiscvISA
43 {
44 
45 class MemInst : public RiscvStaticInst
46 {
47  protected:
48  int64_t offset;
50 
51  MemInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
52  : RiscvStaticInst(mnem, _machInst, __opClass), offset(0)
53  {}
54 };
55 
56 class Load : public MemInst
57 {
58  protected:
59  using MemInst::MemInst;
60 
61  std::string generateDisassembly(
62  Addr pc, const loader::SymbolTable *symtab) const override;
63 };
64 
65 class Store : public MemInst
66 {
67  protected:
68  using MemInst::MemInst;
69 
70  std::string generateDisassembly(
71  Addr pc, const loader::SymbolTable *symtab) const override;
72 };
73 
74 } // namespace RiscvISA
75 } // namespace gem5
76 
77 #endif // __ARCH_RISCV_INST_MEM_HH__
gem5::RiscvISA::Store::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem.cc:56
gem5::RiscvISA::RiscvStaticInst
Base class for all RISC-V static instructions.
Definition: static_inst.hh:49
gem5::RiscvISA::Load::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem.cc:47
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::RiscvISA::MemInst::memAccessFlags
Request::Flags memAccessFlags
Definition: mem.hh:49
gem5::Flags< FlagsType >
gem5::RiscvISA::MemInst
Definition: mem.hh:45
gem5::RiscvISA::Load
Definition: mem.hh:56
gem5::RiscvISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
static_inst.hh
gem5::RiscvISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:54
static_inst.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::RiscvISA::Store
Definition: mem.hh:65
gem5::RiscvISA::MemInst::MemInst
MemInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: mem.hh:51
exec_context.hh
gem5::RiscvISA::MemInst::offset
int64_t offset
Definition: mem.hh:48
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40

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