gem5  v21.1.0.2
mem.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2015 RISC-V Foundation
3  * Copyright (c) 2017 The University of Virginia
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions are
8  * met: redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer;
10  * redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution;
13  * neither the name of the copyright holders nor the names of its
14  * contributors may be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28  */
29 
30 #include "arch/riscv/insts/mem.hh"
31 
32 #include <sstream>
33 #include <string>
34 
37 #include "arch/riscv/utility.hh"
38 #include "cpu/static_inst.hh"
39 
40 namespace gem5
41 {
42 
43 namespace RiscvISA
44 {
45 
46 std::string
48 {
49  std::stringstream ss;
50  ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", " <<
51  offset << '(' << registerName(srcRegIdx(0)) << ')';
52  return ss.str();
53 }
54 
55 std::string
57 {
58  std::stringstream ss;
59  ss << mnemonic << ' ' << registerName(srcRegIdx(1)) << ", " <<
60  offset << '(' << registerName(srcRegIdx(0)) << ')';
61  return ss.str();
62 }
63 
64 } // namespace RiscvISA
65 } // namespace gem5
gem5::RiscvISA::Store::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem.cc:56
mem.hh
gem5::RiscvISA::Load::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem.cc:47
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::StaticInst::destRegIdx
const RegId & destRegIdx(int i) const
Return logical index (architectural reg num) of i'th destination reg.
Definition: static_inst.hh:237
gem5::RiscvISA::registerName
std::string registerName(RegId reg)
Definition: utility.hh:106
gem5::RiscvISA::ss
Bitfield< 11, 8 > ss
Definition: pra_constants.hh:257
gem5::StaticInst::srcRegIdx
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
Definition: static_inst.hh:247
gem5::RiscvISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
static_inst.hh
static_inst.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::RiscvISA::MemInst::offset
int64_t offset
Definition: mem.hh:48
utility.hh
bitfields.hh
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:281
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40

Generated on Tue Sep 21 2021 12:24:34 for gem5 by doxygen 1.8.17