base_gic.hh File Reference

Base class for ARM GIC implementations. More...

#include <memory>
#include <unordered_map>
#include <vector>
#include "arch/arm/system.hh"
#include "dev/intpin.hh"
#include "dev/io_device.hh"
#include "enums/ArmInterruptType.hh"

Go to the source code of this file.

Classes
class	gem5::BaseGic
class	gem5::ArmInterruptPinGen
	This SimObject is instantiated in the python world and serves as an ArmInterruptPin generator. More...
class	gem5::ArmSPIGen
	Shared Peripheral Interrupt Generator It is capable of generating one interrupt only: it maintains a pointer to it and returns it every time it is asked for it (via the get metod) More...
class	gem5::ArmPPIGen
	Private Peripheral Interrupt Generator Since PPIs are banked in the GIC, this class is capable of generating more than one interrupt (one per ContextID). More...
class	gem5::ArmSigInterruptPinGen
class	gem5::ArmInterruptPin
	Generic representation of an Arm interrupt pin. More...
class	gem5::ArmSPI
class	gem5::ArmPPI
class	gem5::ArmSigInterruptPin

Namespaces
	gem5
	Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.

Detailed Description

Base class for ARM GIC implementations.

Definition in file base_gic.hh.