gem5  v22.1.0.0
system.hh
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40 
41 #ifndef __ARCH_ARM_SYSTEM_HH__
42 #define __ARCH_ARM_SYSTEM_HH__
43 
44 #include <memory>
45 #include <string>
46 #include <unordered_map>
47 #include <vector>
48 
49 #include "arch/arm/page_size.hh"
50 #include "arch/arm/types.hh"
51 #include "kern/linux/events.hh"
52 #include "params/ArmSystem.hh"
53 #include "sim/full_system.hh"
54 #include "sim/sim_object.hh"
55 #include "sim/system.hh"
56 #include "enums/ArmExtension.hh"
57 
58 
59 namespace gem5
60 {
61 
62 class GenericTimer;
63 class BaseGic;
64 class FVPBasePwrCtrl;
65 class ThreadContext;
66 
67 struct ArmReleaseParams;
68 
69 class ArmRelease : public SimObject
70 {
71  public:
73  ArmRelease(const Params &p);
74 
75  bool
76  has(ArmExtension ext) const
77  {
78  if (auto it = _extensions.find(ext); it != _extensions.end()) {
79  return it->second;
80  } else {
81  return false;
82  }
83  }
84 
85  protected:
89  std::unordered_map<ArmExtension, bool> _extensions;
90 };
91 
92 class ArmSystem : public System
93 {
94  protected:
100 
105 
110 
116 
121  const uint8_t _physAddrRange64;
122 
126  const bool _haveLargeAsid64;
127 
129  const unsigned _sveVL;
130 
135 
141 
142  public:
143  static constexpr Addr PageBytes = ArmISA::PageBytes;
144  static constexpr Addr PageShift = ArmISA::PageShift;
145 
147 
148  ArmSystem(const Params &p);
149 
151  bool multiProc;
152 
153  const ArmRelease* releaseFS() const { return release; }
154 
155  bool has(ArmExtension ext) const { return release->has(ext); }
156 
158  void
160  {
161  _genericTimer = generic_timer;
162  }
163 
165  void setGIC(BaseGic *gic) { _gic = gic; }
166 
169  {
170  _pwrCtrl = pwr_ctrl;
171  }
172 
175 
177  BaseGic *getGIC() const { return _gic; }
178 
181 
184  bool highestELIs64() const { return _highestELIs64; }
185 
188  highestEL() const
189  {
190  if (has(ArmExtension::SECURITY))
191  return ArmISA::EL3;
192  if (has(ArmExtension::VIRTUALIZATION))
193  return ArmISA::EL2;
194  return ArmISA::EL1;
195  }
196 
199  Addr resetAddr() const { return _resetAddr; }
201 
203  bool haveLargeAsid64() const { return _haveLargeAsid64; }
204 
206  unsigned sveVL() const { return _sveVL; }
207 
210  uint8_t physAddrRange64() const { return _physAddrRange64; }
211 
213  uint8_t
215  {
216  if (_highestELIs64)
217  return _physAddrRange64;
218  if (has(ArmExtension::LPAE))
219  return 40;
220  return 32;
221  }
222 
224  Addr physAddrMask() const { return mask(physAddrRange()); }
225 
227  bool haveSemihosting() const { return semihosting != nullptr; }
228 
233  static ArmSystem*
235  {
236  assert(FullSystem);
237  return static_cast<ArmSystem *>(tc->getSystemPtr());
238  }
239 
240  static bool has(ArmExtension ext, ThreadContext *tc);
241 
242  static bool highestELIs64(ThreadContext *tc);
243 
248 
250  static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el);
251 
255  static Addr resetAddr(ThreadContext *tc);
256 
260  static uint8_t physAddrRange(ThreadContext *tc);
261 
265  static Addr physAddrMask(ThreadContext *tc);
266 
269  static bool haveLargeAsid64(ThreadContext *tc);
270 
272  static bool haveSemihosting(ThreadContext *tc);
273 
275  static bool callSemihosting64(ThreadContext *tc, bool gem5_ops=false);
276 
278  static bool callSemihosting32(ThreadContext *tc, bool gem5_ops=false);
279 
281  static bool callSemihosting(ThreadContext *tc, bool gem5_ops=false);
282 
284  static void callSetStandByWfi(ThreadContext *tc);
285 
287  static void callClearStandByWfi(ThreadContext *tc);
288 
294  static bool callSetWakeRequest(ThreadContext *tc);
295 
297  static void callClearWakeRequest(ThreadContext *tc);
298 };
299 
300 } // namespace gem5
301 
302 #endif
bool has(ArmExtension ext) const
Definition: system.hh:76
ArmRelease(const Params &p)
Definition: system.cc:61
std::unordered_map< ArmExtension, bool > _extensions
List of implemented extensions.
Definition: system.hh:89
PARAMS(ArmRelease)
Semihosting for AArch32 and AArch64.
Definition: semihosting.hh:77
const bool _haveLargeAsid64
True if ASID is 16 bits in AArch64 (ARMv8)
Definition: system.hh:126
static ArmSystem * getArmSystem(ThreadContext *tc)
Returns a valid ArmSystem pointer if using ARM ISA, it fails otherwise.
Definition: system.hh:234
static constexpr Addr PageShift
Definition: system.hh:144
void setGenericTimer(GenericTimer *generic_timer)
Sets the pointer to the Generic Timer.
Definition: system.hh:159
FVPBasePwrCtrl * _pwrCtrl
Pointer to the Power Controller (if any)
Definition: system.hh:104
BaseGic * _gic
Definition: system.hh:99
uint8_t physAddrRange64() const
Returns the supported physical address range in bits if the highest implemented exception level is 64...
Definition: system.hh:210
Addr physAddrMask() const
Returns the physical address mask.
Definition: system.hh:224
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:184
static constexpr Addr PageBytes
Definition: system.hh:143
BaseGic * getGIC() const
Get a pointer to the system's GIC.
Definition: system.hh:177
ArmISA::ExceptionLevel highestEL() const
Returns the highest implemented exception level.
Definition: system.hh:188
static bool callSemihosting32(ThreadContext *tc, bool gem5_ops=false)
Make a Semihosting call from aarch32.
Definition: system.cc:184
bool haveSemihosting() const
Is Arm Semihosting support enabled?
Definition: system.hh:227
const uint8_t _physAddrRange64
Supported physical address range in bits if the highest implemented exception level is 64 bits (ARMv8...
Definition: system.hh:121
static void callClearStandByWfi(ThreadContext *tc)
Make a call to notify the power controller of STANDBYWFI deassertion.
Definition: system.cc:206
static void callSetStandByWfi(ThreadContext *tc)
Make a call to notify the power controller of STANDBYWFI assertion.
Definition: system.cc:199
ArmSemihosting *const semihosting
True if the Semihosting interface is enabled.
Definition: system.hh:134
Addr _resetAddr
Reset address (ARMv8)
Definition: system.hh:109
static bool callSemihosting(ThreadContext *tc, bool gem5_ops=false)
Make a Semihosting call from either aarch64 or aarch32.
Definition: system.cc:190
uint8_t physAddrRange() const
Returns the supported physical address range in bits.
Definition: system.hh:214
static bool callSetWakeRequest(ThreadContext *tc)
Notify the power controller of WAKEREQUEST assertion.
Definition: system.cc:213
void setResetAddr(Addr addr)
Definition: system.hh:200
PARAMS(ArmSystem)
void setPowerController(FVPBasePwrCtrl *pwr_ctrl)
Sets the pointer to the Power Controller.
Definition: system.hh:168
bool has(ArmExtension ext) const
Definition: system.hh:155
bool haveLargeAsid64() const
Returns true if ASID is 16 bits in AArch64 (ARMv8)
Definition: system.hh:203
Addr resetAddr() const
Returns the reset address if the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:199
static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el)
Return true if the system implements a specific exception level.
Definition: system.cc:131
const unsigned _sveVL
SVE vector length at reset, in quadwords.
Definition: system.hh:129
FVPBasePwrCtrl * getPowerController() const
Get a pointer to the system's power controller.
Definition: system.hh:180
void setGIC(BaseGic *gic)
Sets the pointer to the GIC.
Definition: system.hh:165
static void callClearWakeRequest(ThreadContext *tc)
Notify the power controller of WAKEREQUEST deassertion.
Definition: system.cc:222
bool multiProc
true if this a multiprocessor system
Definition: system.hh:151
GenericTimer * getGenericTimer() const
Get a pointer to the system's generic timer model.
Definition: system.hh:174
GenericTimer * _genericTimer
Pointer to the Generic Timer wrapper.
Definition: system.hh:98
unsigned sveVL() const
Returns the SVE vector length at reset, in quadwords.
Definition: system.hh:206
ArmSystem(const Params &p)
Definition: system.cc:72
bool _highestELIs64
True if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:115
static bool callSemihosting64(ThreadContext *tc, bool gem5_ops=false)
Make a Semihosting call from aarch64.
Definition: system.cc:178
const ArmRelease * release
Arm Release object: contains a list of implemented features.
Definition: system.hh:140
const ArmRelease * releaseFS() const
Definition: system.hh:153
Abstract superclass for simulation objects.
Definition: sim_object.hh:148
SimObjectParams Params
Definition: sim_object.hh:170
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual System * getSystemPtr()=0
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
Bitfield< 27, 24 > gic
Definition: misc_types.hh:175
const Addr PageShift
Definition: page_size.hh:52
Bitfield< 3, 2 > el
Definition: misc_types.hh:73
const Addr PageBytes
Definition: page_size.hh:53
Bitfield< 12 > ext
Definition: misc_types.hh:434
Bitfield< 54 > p
Definition: pagetable.hh:70
Bitfield< 3 > addr
Definition: types.hh:84
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220

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