gem5  v22.0.0.2
system.hh
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40 
41 #ifndef __ARCH_ARM_SYSTEM_HH__
42 #define __ARCH_ARM_SYSTEM_HH__
43 
44 #include <memory>
45 #include <string>
46 #include <unordered_map>
47 #include <vector>
48 
49 #include "arch/arm/page_size.hh"
50 #include "kern/linux/events.hh"
51 #include "params/ArmSystem.hh"
52 #include "sim/full_system.hh"
53 #include "sim/sim_object.hh"
54 #include "sim/system.hh"
55 #include "enums/ArmExtension.hh"
56 
57 
58 namespace gem5
59 {
60 
61 class GenericTimer;
62 class BaseGic;
63 class FVPBasePwrCtrl;
64 class ThreadContext;
65 
66 struct ArmReleaseParams;
67 
68 class ArmRelease : public SimObject
69 {
70  public:
72  ArmRelease(const Params &p);
73 
74  bool
75  has(ArmExtension ext) const
76  {
77  if (auto it = _extensions.find(ext); it != _extensions.end()) {
78  return it->second;
79  } else {
80  return false;
81  }
82  }
83 
84  protected:
88  std::unordered_map<ArmExtension, bool> _extensions;
89 };
90 
91 class ArmSystem : public System
92 {
93  protected:
99 
104 
109 
115 
120  const uint8_t _physAddrRange64;
121 
125  const bool _haveLargeAsid64;
126 
128  const unsigned _sveVL;
129 
134 
140 
141  public:
142  static constexpr Addr PageBytes = ArmISA::PageBytes;
143  static constexpr Addr PageShift = ArmISA::PageShift;
144 
145  PARAMS(ArmSystem);
146 
147  ArmSystem(const Params &p);
148 
150  bool multiProc;
151 
152  const ArmRelease* releaseFS() const { return release; }
153 
154  bool has(ArmExtension ext) const { return release->has(ext); }
155 
157  void
159  {
160  _genericTimer = generic_timer;
161  }
162 
164  void setGIC(BaseGic *gic) { _gic = gic; }
165 
168  {
169  _pwrCtrl = pwr_ctrl;
170  }
171 
174 
176  BaseGic *getGIC() const { return _gic; }
177 
180 
183  bool highestELIs64() const { return _highestELIs64; }
184 
187  highestEL() const
188  {
189  if (has(ArmExtension::SECURITY))
190  return ArmISA::EL3;
191  if (has(ArmExtension::VIRTUALIZATION))
192  return ArmISA::EL2;
193  return ArmISA::EL1;
194  }
195 
198  Addr resetAddr() const { return _resetAddr; }
200 
202  bool haveLargeAsid64() const { return _haveLargeAsid64; }
203 
205  unsigned sveVL() const { return _sveVL; }
206 
209  uint8_t physAddrRange64() const { return _physAddrRange64; }
210 
212  uint8_t
214  {
215  if (_highestELIs64)
216  return _physAddrRange64;
217  if (has(ArmExtension::LPAE))
218  return 40;
219  return 32;
220  }
221 
223  Addr physAddrMask() const { return mask(physAddrRange()); }
224 
226  bool haveSemihosting() const { return semihosting != nullptr; }
227 
232  static ArmSystem*
234  {
235  assert(FullSystem);
236  return static_cast<ArmSystem *>(tc->getSystemPtr());
237  }
238 
239  static bool has(ArmExtension ext, ThreadContext *tc);
240 
241  static bool highestELIs64(ThreadContext *tc);
242 
247 
249  static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el);
250 
254  static Addr resetAddr(ThreadContext *tc);
255 
259  static uint8_t physAddrRange(ThreadContext *tc);
260 
264  static Addr physAddrMask(ThreadContext *tc);
265 
268  static bool haveLargeAsid64(ThreadContext *tc);
269 
271  static bool haveSemihosting(ThreadContext *tc);
272 
274  static bool callSemihosting64(ThreadContext *tc, bool gem5_ops=false);
275 
277  static bool callSemihosting32(ThreadContext *tc, bool gem5_ops=false);
278 
280  static bool callSemihosting(ThreadContext *tc, bool gem5_ops=false);
281 
283  static void callSetStandByWfi(ThreadContext *tc);
284 
286  static void callClearStandByWfi(ThreadContext *tc);
287 
293  static bool callSetWakeRequest(ThreadContext *tc);
294 
296  static void callClearWakeRequest(ThreadContext *tc);
297 };
298 
299 } // namespace gem5
300 
301 #endif
gem5::ArmSystem::setGenericTimer
void setGenericTimer(GenericTimer *generic_timer)
Sets the pointer to the Generic Timer.
Definition: system.hh:158
gem5::ArmSystem::physAddrRange
uint8_t physAddrRange() const
Returns the supported physical address range in bits.
Definition: system.hh:213
events.hh
gem5::ThreadContext::getSystemPtr
virtual System * getSystemPtr()=0
gem5::ArmISA::PageShift
const Addr PageShift
Definition: page_size.hh:52
gem5::ArmSystem::_genericTimer
GenericTimer * _genericTimer
Pointer to the Generic Timer wrapper.
Definition: system.hh:97
gem5::ArmSystem::_gic
BaseGic * _gic
Definition: system.hh:98
gem5::ArmSystem::ArmSystem
ArmSystem(const Params &p)
Definition: system.cc:72
system.hh
gem5::ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:183
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:73
gem5::ArmSystem::callSemihosting64
static bool callSemihosting64(ThreadContext *tc, bool gem5_ops=false)
Make a Semihosting call from aarch64.
Definition: system.cc:178
gem5::ArmSystem::callClearWakeRequest
static void callClearWakeRequest(ThreadContext *tc)
Notify the power controller of WAKEREQUEST deassertion.
Definition: system.cc:222
gem5::ArmSystem::haveLargeAsid64
bool haveLargeAsid64() const
Returns true if ASID is 16 bits in AArch64 (ARMv8)
Definition: system.hh:202
gem5::ArmSystem::getPowerController
FVPBasePwrCtrl * getPowerController() const
Get a pointer to the system's power controller.
Definition: system.hh:179
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:274
gem5::ArmSystem::callSemihosting
static bool callSemihosting(ThreadContext *tc, bool gem5_ops=false)
Make a Semihosting call from either aarch64 or aarch32.
Definition: system.cc:190
gem5::ArmSystem::getGIC
BaseGic * getGIC() const
Get a pointer to the system's GIC.
Definition: system.hh:176
gem5::mask
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
gem5::ArmSystem::getArmSystem
static ArmSystem * getArmSystem(ThreadContext *tc)
Returns a valid ArmSystem pointer if using ARM ISA, it fails otherwise.
Definition: system.hh:233
gem5::ArmSystem::_resetAddr
Addr _resetAddr
Reset address (ARMv8)
Definition: system.hh:108
gem5::ArmISA::gic
Bitfield< 27, 24 > gic
Definition: misc_types.hh:175
gem5::SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:170
gem5::ArmRelease::has
bool has(ArmExtension ext) const
Definition: system.hh:75
gem5::ArmRelease::ArmRelease
ArmRelease(const Params &p)
Definition: system.cc:61
gem5::ArmSystem::multiProc
bool multiProc
true if this a multiprocessor system
Definition: system.hh:150
gem5::ArmSystem::PARAMS
PARAMS(ArmSystem)
gem5::System
Definition: system.hh:75
gem5::ArmSystem::highestEL
ArmISA::ExceptionLevel highestEL() const
Returns the highest implemented exception level.
Definition: system.hh:187
gem5::BaseGic
Definition: base_gic.hh:72
gem5::ArmRelease::PARAMS
PARAMS(ArmRelease)
gem5::ArmSystem::_pwrCtrl
FVPBasePwrCtrl * _pwrCtrl
Pointer to the Power Controller (if any)
Definition: system.hh:103
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::ArmSystem::PageShift
static constexpr Addr PageShift
Definition: system.hh:143
sim_object.hh
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:275
gem5::ArmSystem::semihosting
ArmSemihosting *const semihosting
True if the Semihosting interface is enabled.
Definition: system.hh:133
gem5::GenericTimer
Definition: generic_timer.hh:286
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:276
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::ArmISA::ext
Bitfield< 12 > ext
Definition: misc_types.hh:428
gem5::ArmSystem::_physAddrRange64
const uint8_t _physAddrRange64
Supported physical address range in bits if the highest implemented exception level is 64 bits (ARMv8...
Definition: system.hh:120
gem5::ArmSystem::callSetWakeRequest
static bool callSetWakeRequest(ThreadContext *tc)
Notify the power controller of WAKEREQUEST assertion.
Definition: system.cc:213
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmSystem::callClearStandByWfi
static void callClearStandByWfi(ThreadContext *tc)
Make a call to notify the power controller of STANDBYWFI deassertion.
Definition: system.cc:206
gem5::ArmSystem::_highestELIs64
bool _highestELIs64
True if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:114
gem5::ArmSemihosting
Semihosting for AArch32 and AArch64.
Definition: semihosting.hh:76
full_system.hh
gem5::ArmRelease
Definition: system.hh:68
gem5::ArmSystem::physAddrMask
Addr physAddrMask() const
Returns the physical address mask.
Definition: system.hh:223
gem5::ArmSystem::setPowerController
void setPowerController(FVPBasePwrCtrl *pwr_ctrl)
Sets the pointer to the Power Controller.
Definition: system.hh:167
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::ArmSystem::has
bool has(ArmExtension ext) const
Definition: system.hh:154
gem5::ArmSystem::release
const ArmRelease * release
Arm Release object: contains a list of implemented features.
Definition: system.hh:139
gem5::ArmSystem::callSetStandByWfi
static void callSetStandByWfi(ThreadContext *tc)
Make a call to notify the power controller of STANDBYWFI assertion.
Definition: system.cc:199
gem5::ArmSystem
Definition: system.hh:91
gem5::FVPBasePwrCtrl
Definition: fvp_base_pwr_ctrl.hh:58
gem5::ArmRelease::_extensions
std::unordered_map< ArmExtension, bool > _extensions
List of implemented extensions.
Definition: system.hh:88
gem5::ArmSystem::sveVL
unsigned sveVL() const
Returns the SVE vector length at reset, in quadwords.
Definition: system.hh:205
gem5::ArmSystem::haveSemihosting
bool haveSemihosting() const
Is Arm Semihosting support enabled?
Definition: system.hh:226
gem5::ArmSystem::setGIC
void setGIC(BaseGic *gic)
Sets the pointer to the GIC.
Definition: system.hh:164
gem5::ArmISA::PageBytes
const Addr PageBytes
Definition: page_size.hh:53
gem5::ArmSystem::resetAddr
Addr resetAddr() const
Returns the reset address if the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:198
gem5::ArmSystem::releaseFS
const ArmRelease * releaseFS() const
Definition: system.hh:152
gem5::ArmSystem::getGenericTimer
GenericTimer * getGenericTimer() const
Get a pointer to the system's generic timer model.
Definition: system.hh:173
gem5::ArmSystem::PageBytes
static constexpr Addr PageBytes
Definition: system.hh:142
page_size.hh
gem5::ArmSystem::haveEL
static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el)
Return true if the system implements a specific exception level.
Definition: system.cc:131
gem5::ArmSystem::physAddrRange64
uint8_t physAddrRange64() const
Returns the supported physical address range in bits if the highest implemented exception level is 64...
Definition: system.hh:209
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ArmSystem::_haveLargeAsid64
const bool _haveLargeAsid64
True if ASID is 16 bits in AArch64 (ARMv8)
Definition: system.hh:125
gem5::ArmSystem::callSemihosting32
static bool callSemihosting32(ThreadContext *tc, bool gem5_ops=false)
Make a Semihosting call from aarch32.
Definition: system.cc:184
gem5::ArmSystem::_sveVL
const unsigned _sveVL
SVE vector length at reset, in quadwords.
Definition: system.hh:128
gem5::ArmSystem::setResetAddr
void setResetAddr(Addr addr)
Definition: system.hh:199
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:271
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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