gem5  v21.1.0.2
system.hh
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40 
41 #ifndef __ARCH_ARM_SYSTEM_HH__
42 #define __ARCH_ARM_SYSTEM_HH__
43 
44 #include <memory>
45 #include <string>
46 #include <vector>
47 
48 #include "kern/linux/events.hh"
49 #include "params/ArmSystem.hh"
50 #include "sim/full_system.hh"
51 #include "sim/sim_object.hh"
52 #include "sim/system.hh"
53 
54 namespace gem5
55 {
56 
57 class GenericTimer;
58 class BaseGic;
59 class FVPBasePwrCtrl;
60 class ThreadContext;
61 
62 class ArmSystem : public System
63 {
64  protected:
68  const bool _haveSecurity;
69 
73  const bool _haveLPAE;
74 
78  const bool _haveVirtualization;
79 
83  const bool _haveCrypto;
84 
90 
95 
100 
106 
111  const uint8_t _physAddrRange64;
112 
116  const bool _haveLargeAsid64;
117 
121  const bool _haveTME;
122 
126  const bool _haveSVE;
127 
129  const unsigned _sveVL;
130 
134  const bool _haveLSE;
135 
137  const bool _haveVHE;
138 
140  const unsigned _havePAN;
141 
143  const unsigned _haveSecEL2;
144 
149 
150  public:
151  static constexpr Addr PageBytes = ArmISA::PageBytes;
152  static constexpr Addr PageShift = ArmISA::PageShift;
153 
154  PARAMS(ArmSystem);
155 
156  ArmSystem(const Params &p);
157 
159  bool multiProc;
160 
162  bool haveSecurity() const { return _haveSecurity; }
163 
166  bool haveLPAE() const { return _haveLPAE; }
167 
171  bool haveVirtualization() const { return _haveVirtualization; }
172 
176  bool haveCrypto() const { return _haveCrypto; }
177 
179  void
181  {
182  _genericTimer = generic_timer;
183  }
184 
186  void setGIC(BaseGic *gic) { _gic = gic; }
187 
190  {
191  _pwrCtrl = pwr_ctrl;
192  }
193 
196 
198  BaseGic *getGIC() const { return _gic; }
199 
202 
205  bool highestELIs64() const { return _highestELIs64; }
206 
209  highestEL() const
210  {
211  if (_haveSecurity)
212  return ArmISA::EL3;
214  return ArmISA::EL2;
215  return ArmISA::EL1;
216  }
217 
220  Addr resetAddr() const { return _resetAddr; }
222 
224  bool haveLargeAsid64() const { return _haveLargeAsid64; }
225 
229  bool haveTME() const { return _haveTME; }
230 
232  bool haveSVE() const { return _haveSVE; }
233 
235  unsigned sveVL() const { return _sveVL; }
236 
238  bool haveLSE() const { return _haveLSE; }
239 
241  bool haveVHE() const { return _haveVHE; }
242 
244  bool havePAN() const { return _havePAN; }
245 
247  bool haveSecEL2() const { return _haveSecEL2; }
248 
251  uint8_t physAddrRange64() const { return _physAddrRange64; }
252 
254  uint8_t
256  {
257  if (_highestELIs64)
258  return _physAddrRange64;
259  if (_haveLPAE)
260  return 40;
261  return 32;
262  }
263 
265  Addr physAddrMask() const { return mask(physAddrRange()); }
266 
268  bool haveSemihosting() const { return semihosting != nullptr; }
269 
274  static ArmSystem*
276  {
277  assert(FullSystem);
278  return static_cast<ArmSystem *>(tc->getSystemPtr());
279  }
280 
284  static bool haveSecurity(ThreadContext *tc);
285 
289  static bool haveVirtualization(ThreadContext *tc);
290 
294  static bool haveLPAE(ThreadContext *tc);
295 
299  static bool highestELIs64(ThreadContext *tc);
300 
305 
307  static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el);
308 
312  static bool haveTME(ThreadContext *tc);
313 
317  static Addr resetAddr(ThreadContext *tc);
318 
322  static uint8_t physAddrRange(ThreadContext *tc);
323 
327  static Addr physAddrMask(ThreadContext *tc);
328 
331  static bool haveLargeAsid64(ThreadContext *tc);
332 
334  static bool haveSemihosting(ThreadContext *tc);
335 
337  static bool callSemihosting64(ThreadContext *tc, bool gem5_ops=false);
338 
340  static bool callSemihosting32(ThreadContext *tc, bool gem5_ops=false);
341 
343  static bool callSemihosting(ThreadContext *tc, bool gem5_ops=false);
344 
346  static void callSetStandByWfi(ThreadContext *tc);
347 
349  static void callClearStandByWfi(ThreadContext *tc);
350 
356  static bool callSetWakeRequest(ThreadContext *tc);
357 
359  static void callClearWakeRequest(ThreadContext *tc);
360 };
361 
362 } // namespace gem5
363 
364 #endif
gem5::ArmSystem::setGenericTimer
void setGenericTimer(GenericTimer *generic_timer)
Sets the pointer to the Generic Timer.
Definition: system.hh:180
gem5::ArmSystem::physAddrRange
uint8_t physAddrRange() const
Returns the supported physical address range in bits.
Definition: system.hh:255
events.hh
gem5::ThreadContext::getSystemPtr
virtual System * getSystemPtr()=0
gem5::ArmISA::PageShift
const Addr PageShift
Definition: page_size.hh:52
gem5::ArmSystem::_genericTimer
GenericTimer * _genericTimer
Pointer to the Generic Timer wrapper.
Definition: system.hh:88
gem5::ArmSystem::_gic
BaseGic * _gic
Definition: system.hh:89
gem5::ArmSystem::_havePAN
const unsigned _havePAN
True if Priviledge Access Never is implemented.
Definition: system.hh:140
gem5::ArmSystem::ArmSystem
ArmSystem(const Params &p)
Definition: system.cc:60
gem5::ArmSystem::_haveLSE
const bool _haveLSE
True if LSE is implemented (ARMv8.1)
Definition: system.hh:134
gem5::ArmSystem::haveLSE
bool haveLSE() const
Returns true if LSE is implemented (ARMv8.1)
Definition: system.hh:238
system.hh
gem5::ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:205
gem5::ArmSystem::_haveTME
const bool _haveTME
True if system implements the transactional memory extension (TME)
Definition: system.hh:121
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:72
gem5::ArmSystem::haveLPAE
bool haveLPAE() const
Returns true if this system implements the Large Physical Address Extension.
Definition: system.hh:166
gem5::ArmSystem::callSemihosting64
static bool callSemihosting64(ThreadContext *tc, bool gem5_ops=false)
Make a Semihosting call from aarch64.
Definition: system.cc:191
gem5::ArmSystem::haveVHE
bool haveVHE() const
Returns true if Virtualization Host Extensions is implemented.
Definition: system.hh:241
gem5::ArmSystem::callClearWakeRequest
static void callClearWakeRequest(ThreadContext *tc)
Notify the power controller of WAKEREQUEST deassertion.
Definition: system.cc:235
gem5::ArmSystem::haveLargeAsid64
bool haveLargeAsid64() const
Returns true if ASID is 16 bits in AArch64 (ARMv8)
Definition: system.hh:224
gem5::ArmSystem::getPowerController
FVPBasePwrCtrl * getPowerController() const
Get a pointer to the system's power controller.
Definition: system.hh:201
gem5::ArmSystem::haveCrypto
bool haveCrypto() const
Returns true if this system implements the Crypto Extension.
Definition: system.hh:176
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:267
gem5::ArmSystem::callSemihosting
static bool callSemihosting(ThreadContext *tc, bool gem5_ops=false)
Make a Semihosting call from either aarch64 or aarch32.
Definition: system.cc:203
gem5::ArmSystem::getGIC
BaseGic * getGIC() const
Get a pointer to the system's GIC.
Definition: system.hh:198
gem5::mask
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
gem5::ArmSystem::getArmSystem
static ArmSystem * getArmSystem(ThreadContext *tc)
Returns a valid ArmSystem pointer if using ARM ISA, it fails otherwise.
Definition: system.hh:275
gem5::ArmSystem::_resetAddr
Addr _resetAddr
Reset address (ARMv8)
Definition: system.hh:99
gem5::ArmSystem::_haveSVE
const bool _haveSVE
True if SVE is implemented (ARMv8)
Definition: system.hh:126
gem5::ArmISA::gic
Bitfield< 27, 24 > gic
Definition: misc_types.hh:174
gem5::SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:170
gem5::ArmSystem::multiProc
bool multiProc
true if this a multiprocessor system
Definition: system.hh:159
gem5::ArmSystem::PARAMS
PARAMS(ArmSystem)
gem5::System
Definition: system.hh:77
gem5::ArmSystem::highestEL
ArmISA::ExceptionLevel highestEL() const
Returns the highest implemented exception level.
Definition: system.hh:209
gem5::BaseGic
Definition: base_gic.hh:72
gem5::ArmSystem::_pwrCtrl
FVPBasePwrCtrl * _pwrCtrl
Pointer to the Power Controller (if any)
Definition: system.hh:94
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::ArmSystem::PageShift
static constexpr Addr PageShift
Definition: system.hh:152
sim_object.hh
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:268
gem5::ArmSystem::semihosting
ArmSemihosting *const semihosting
True if the Semihosting interface is enabled.
Definition: system.hh:148
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::GenericTimer
Definition: generic_timer.hh:288
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:269
gem5::ArmSystem::havePAN
bool havePAN() const
Returns true if Priviledge Access Never is implemented.
Definition: system.hh:244
gem5::ArmSystem::_physAddrRange64
const uint8_t _physAddrRange64
Supported physical address range in bits if the highest implemented exception level is 64 bits (ARMv8...
Definition: system.hh:111
gem5::ArmSystem::callSetWakeRequest
static bool callSetWakeRequest(ThreadContext *tc)
Notify the power controller of WAKEREQUEST assertion.
Definition: system.cc:226
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmSystem::haveSVE
bool haveSVE() const
Returns true if SVE is implemented (ARMv8)
Definition: system.hh:232
gem5::ArmSystem::_haveSecEL2
const unsigned _haveSecEL2
True if Secure EL2 is implemented.
Definition: system.hh:143
gem5::ArmSystem::callClearStandByWfi
static void callClearStandByWfi(ThreadContext *tc)
Make a call to notify the power controller of STANDBYWFI deassertion.
Definition: system.cc:219
gem5::ArmSystem::_highestELIs64
bool _highestELIs64
True if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:105
gem5::ArmSemihosting
Semihosting for AArch32 and AArch64.
Definition: semihosting.hh:76
full_system.hh
gem5::ArmSystem::physAddrMask
Addr physAddrMask() const
Returns the physical address mask.
Definition: system.hh:265
gem5::ArmSystem::setPowerController
void setPowerController(FVPBasePwrCtrl *pwr_ctrl)
Sets the pointer to the Power Controller.
Definition: system.hh:189
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:223
gem5::ArmSystem::_haveCrypto
const bool _haveCrypto
True if this system implements the Crypto Extension.
Definition: system.hh:83
gem5::ArmSystem::callSetStandByWfi
static void callSetStandByWfi(ThreadContext *tc)
Make a call to notify the power controller of STANDBYWFI assertion.
Definition: system.cc:212
gem5::ArmSystem
Definition: system.hh:62
gem5::FVPBasePwrCtrl
Definition: fvp_base_pwr_ctrl.hh:58
gem5::ArmSystem::sveVL
unsigned sveVL() const
Returns the SVE vector length at reset, in quadwords.
Definition: system.hh:235
gem5::ArmSystem::haveSemihosting
bool haveSemihosting() const
Is Arm Semihosting support enabled?
Definition: system.hh:268
gem5::ArmSystem::haveSecurity
bool haveSecurity() const
Returns true if this system implements the Security Extensions.
Definition: system.hh:162
gem5::ArmSystem::setGIC
void setGIC(BaseGic *gic)
Sets the pointer to the GIC.
Definition: system.hh:186
gem5::ArmISA::PageBytes
const Addr PageBytes
Definition: page_size.hh:53
gem5::ArmSystem::resetAddr
Addr resetAddr() const
Returns the reset address if the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:220
gem5::ArmSystem::getGenericTimer
GenericTimer * getGenericTimer() const
Get a pointer to the system's generic timer model.
Definition: system.hh:195
gem5::ArmSystem::PageBytes
static constexpr Addr PageBytes
Definition: system.hh:151
gem5::ArmSystem::haveEL
static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el)
Return true if the system implements a specific exception level.
Definition: system.cc:138
gem5::ArmSystem::physAddrRange64
uint8_t physAddrRange64() const
Returns the supported physical address range in bits if the highest implemented exception level is 64...
Definition: system.hh:251
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmSystem::_haveVHE
const bool _haveVHE
True if FEAT_VHE (Virtualization Host Extensions) is implemented.
Definition: system.hh:137
gem5::ArmSystem::haveSecEL2
bool haveSecEL2() const
Returns true if Priviledge Access Never is implemented.
Definition: system.hh:247
gem5::ArmSystem::haveTME
bool haveTME() const
Returns true if this system implements the transactional memory extension (ARMv9)
Definition: system.hh:229
gem5::ArmSystem::_haveLargeAsid64
const bool _haveLargeAsid64
True if ASID is 16 bits in AArch64 (ARMv8)
Definition: system.hh:116
gem5::ArmSystem::_haveVirtualization
const bool _haveVirtualization
True if this system implements the virtualization Extensions.
Definition: system.hh:78
gem5::ArmSystem::callSemihosting32
static bool callSemihosting32(ThreadContext *tc, bool gem5_ops=false)
Make a Semihosting call from aarch32.
Definition: system.cc:197
gem5::ArmSystem::_sveVL
const unsigned _sveVL
SVE vector length at reset, in quadwords.
Definition: system.hh:129
gem5::ArmSystem::_haveSecurity
const bool _haveSecurity
True if this system implements the Security Extensions.
Definition: system.hh:68
gem5::ArmSystem::_haveLPAE
const bool _haveLPAE
True if this system implements the Large Physical Address Extension.
Definition: system.hh:73
gem5::ArmSystem::setResetAddr
void setResetAddr(Addr addr)
Definition: system.hh:221
gem5::ArmSystem::haveVirtualization
bool haveVirtualization() const
Returns true if this system implements the virtualization Extensions.
Definition: system.hh:171
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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