gem5  v21.1.0.2
blockmem.cc
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28 
30 
31 namespace gem5
32 {
33 
34 namespace SparcISA
35 {
36 
37 std::string
39  Addr pc, const loader::SymbolTable *symtab) const
40 {
41  std::stringstream response;
42  bool load = flags[IsLoad];
43  bool save = flags[IsStore];
44 
45  printMnemonic(response, mnemonic);
46  if (save) {
47  printReg(response, srcRegIdx(0));
48  ccprintf(response, ", ");
49  }
50  ccprintf(response, "[ ");
51  printReg(response, srcRegIdx(!save ? 0 : 1));
52  ccprintf(response, " + ");
53  printReg(response, srcRegIdx(!save ? 1 : 2));
54  ccprintf(response, " ]");
55  if (load) {
56  ccprintf(response, ", ");
57  printReg(response, destRegIdx(0));
58  }
59 
60  return response.str();
61 }
62 
63 std::string
65  Addr pc, const loader::SymbolTable *symtab) const
66 {
67  std::stringstream response;
68  bool load = flags[IsLoad];
69  bool save = flags[IsStore];
70 
71  printMnemonic(response, mnemonic);
72  if (save) {
73  printReg(response, srcRegIdx(1));
74  ccprintf(response, ", ");
75  }
76  ccprintf(response, "[ ");
77  printReg(response, srcRegIdx(0));
78  if (imm >= 0)
79  ccprintf(response, " + 0x%x ]", imm);
80  else
81  ccprintf(response, " + -0x%x ]", -imm);
82  if (load) {
83  ccprintf(response, ", ");
84  printReg(response, destRegIdx(0));
85  }
86 
87  return response.str();
88 }
89 
90 } // namespace SparcISA
91 } // namespace gem5
gem5::SparcISA::BlockMemMicro::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: blockmem.cc:38
blockmem.hh
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::StaticInst::destRegIdx
const RegId & destRegIdx(int i) const
Return logical index (architectural reg num) of i'th destination reg.
Definition: static_inst.hh:237
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::StaticInst::srcRegIdx
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
Definition: static_inst.hh:247
gem5::SparcISA::BlockMemImmMicro::imm
const int32_t imm
Definition: blockmem.hh:87
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:103
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::SparcISA::SparcStaticInst::printReg
static void printReg(std::ostream &os, RegId reg)
Definition: static_inst.cc:102
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::SparcISA::SparcStaticInst::printMnemonic
static void printMnemonic(std::ostream &os, const char *mnemonic)
Definition: static_inst.cc:63
gem5::SparcISA::BlockMemImmMicro::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: blockmem.cc:64
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:281
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40

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