| _cacheLineSize | gem5::BaseCPU | protected |
| _cpuId | gem5::BaseCPU | protected |
| _dataRequestorId | gem5::BaseCPU | protected |
| _drainManager | gem5::Drainable | private |
| _drainState | gem5::Drainable | mutableprivate |
| _instRequestorId | gem5::BaseCPU | protected |
| _kvmRun | gem5::BaseKvmCPU | private |
| _name | gem5::Named | private |
| _objNameResolver | gem5::SimObject | privatestatic |
| _params | gem5::SimObject | protected |
| _pid | gem5::BaseCPU | protected |
| _regIndexList | gem5::BaseArmKvmCPU | mutableprivate |
| _socketId | gem5::BaseCPU | protected |
| _status | gem5::BaseKvmCPU | protected |
| _switchedOut | gem5::BaseCPU | protected |
| _taskId | gem5::BaseCPU | protected |
| activateContext(ThreadID thread_num) override | gem5::BaseKvmCPU | virtual |
| activeInstPeriod | gem5::BaseKvmCPU | private |
| addressMonitor | gem5::BaseCPU | private |
| addStat(statistics::Info *info) | gem5::statistics::Group | |
| addStatGroup(const char *name, Group *block) | gem5::statistics::Group | |
| alwaysSyncTC | gem5::BaseKvmCPU | protected |
| archIsDrained() const | gem5::BaseKvmCPU | inlineprotectedvirtual |
| armMonitor(ThreadID tid, Addr address) | gem5::BaseCPU | |
| BaseArmKvmCPU(const BaseArmKvmCPUParams ¶ms) | gem5::BaseArmKvmCPU | |
| BaseCPU(const Params ¶ms, bool is_checker=false) | gem5::BaseCPU | |
| BaseKvmCPU(const BaseKvmCPUParams ¶ms) | gem5::BaseKvmCPU | |
| baseStats | gem5::BaseCPU | |
| cacheLineSize() const | gem5::BaseCPU | inline |
| checkInterrupts(ThreadID tid) const | gem5::BaseCPU | inline |
| clearInterrupt(ThreadID tid, int int_num, int index) | gem5::BaseCPU | inline |
| clearInterrupts(ThreadID tid) | gem5::BaseCPU | inline |
| clockDomain | gem5::Clocked | private |
| Clocked(ClockDomain &clk_domain) | gem5::Clocked | inlineprotected |
| Clocked(Clocked &)=delete | gem5::Clocked | protected |
| clockEdge(Cycles cycles=Cycles(0)) const | gem5::Clocked | inline |
| ClockedObject(const ClockedObjectParams &p) | gem5::ClockedObject | |
| clockPeriod() const | gem5::Clocked | inline |
| clockPeriodUpdated() | gem5::Clocked | inlineprotectedvirtual |
| commitStats | gem5::BaseCPU | |
| contextToThread(ContextID cid) | gem5::BaseCPU | inline |
| CPU_STATE_ON enum value | gem5::BaseCPU | protected |
| CPU_STATE_SLEEP enum value | gem5::BaseCPU | protected |
| CPU_STATE_WAKEUP enum value | gem5::BaseCPU | protected |
| cpuId() const | gem5::BaseCPU | inline |
| cpuList | gem5::BaseCPU | privatestatic |
| CPUState enum name | gem5::BaseCPU | protected |
| ctrInsts | gem5::BaseKvmCPU | |
| curCycle() const | gem5::Clocked | inline |
| currentFunctionEnd | gem5::BaseCPU | private |
| currentFunctionStart | gem5::BaseCPU | private |
| currentSection() | gem5::Serializable | static |
| cycle | gem5::Clocked | mutableprivate |
| cyclesToTicks(Cycles c) const | gem5::Clocked | inline |
| dataPort | gem5::BaseKvmCPU | protected |
| dataRequestorId() const | gem5::BaseCPU | inline |
| deallocateContext(ThreadID thread_num) | gem5::BaseKvmCPU | |
| deschedule(Event &event) | gem5::EventManager | inline |
| deschedule(Event *event) | gem5::EventManager | inline |
| deschedulePowerGatingEvent() | gem5::BaseCPU | |
| deviceEventQueue() | gem5::BaseKvmCPU | inlineprotected |
| discardPendingSignal(int signum) const | gem5::BaseKvmCPU | private |
| dmDrain() | gem5::Drainable | private |
| dmDrainResume() | gem5::Drainable | private |
| doMMIOAccess(Addr paddr, void *data, int size, bool write) | gem5::BaseKvmCPU | protected |
| drain() override | gem5::BaseKvmCPU | virtual |
| Drainable() | gem5::Drainable | protected |
| drainResume() override | gem5::BaseKvmCPU | virtual |
| drainState() const | gem5::Drainable | inline |
| dump() const | gem5::BaseKvmCPU | virtual |
| enableFunctionTrace() | gem5::BaseCPU | private |
| enterPwrGating() | gem5::BaseCPU | protected |
| enterPwrGatingEvent | gem5::BaseCPU | protected |
| EventManager(EventManager &em) | gem5::EventManager | inline |
| EventManager(EventManager *em) | gem5::EventManager | inline |
| EventManager(EventQueue *eq) | gem5::EventManager | inline |
| eventq | gem5::EventManager | protected |
| eventQueue() const | gem5::EventManager | inline |
| executeStats | gem5::BaseCPU | |
| fetchStats | gem5::BaseCPU | |
| find(const char *name) | gem5::SimObject | static |
| findContext(ThreadContext *tc) | gem5::BaseCPU | |
| finishMMIOPending() | gem5::BaseKvmCPU | |
| fiqAsserted | gem5::BaseArmKvmCPU | protected |
| flushCoalescedMMIO() | gem5::BaseKvmCPU | private |
| flushTLBs() | gem5::BaseCPU | |
| frequency() const | gem5::Clocked | inline |
| functionEntryTick | gem5::BaseCPU | private |
| functionTraceStream | gem5::BaseCPU | private |
| functionTracingEnabled | gem5::BaseCPU | private |
| generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream) | gem5::Serializable | static |
| getAndFormatOneReg(uint64_t id) const | gem5::BaseKvmCPU | protected |
| getContext(int tn) override | gem5::BaseKvmCPU | virtual |
| getCpuAddrMonitor(ThreadID tid) | gem5::BaseCPU | inline |
| getCurrentInstCount(ThreadID tid) | gem5::BaseCPU | |
| getDataPort() override | gem5::BaseKvmCPU | inlinevirtual |
| getFPUState(struct kvm_fpu &state) const | gem5::BaseKvmCPU | protected |
| getGuestData(uint64_t offset) const | gem5::BaseKvmCPU | inlineprotected |
| getHostCycles() const | gem5::BaseKvmCPU | protectedvirtual |
| getInstPort() override | gem5::BaseKvmCPU | inlinevirtual |
| getInterruptController(ThreadID tid) | gem5::BaseCPU | inline |
| getKvmRunState() | gem5::BaseKvmCPU | inlineprotected |
| getOneReg(uint64_t id, void *addr) const | gem5::BaseKvmCPU | protected |
| getOneRegU32(uint64_t id) const | gem5::BaseKvmCPU | inlineprotected |
| getOneRegU64(uint64_t id) const | gem5::BaseKvmCPU | inlineprotected |
| getPid() const | gem5::BaseCPU | inline |
| getPort(const std::string &if_name, PortID idx=InvalidPortID) override | gem5::BaseCPU | virtual |
| getProbeManager() | gem5::SimObject | |
| getRegisters(struct kvm_regs ®s) const | gem5::BaseKvmCPU | protected |
| getRegList() const | gem5::BaseArmKvmCPU | protected |
| getRegList(kvm_reg_list ®s) const | gem5::BaseArmKvmCPU | private |
| getSimObjectResolver() | gem5::SimObject | static |
| getSpecialRegisters(struct kvm_sregs ®s) const | gem5::BaseKvmCPU | protected |
| getStatGroups() const | gem5::statistics::Group | |
| getStats() const | gem5::statistics::Group | |
| getTracer() | gem5::BaseCPU | inline |
| getVCpuID() const | gem5::BaseKvmCPU | inline |
| globalStats | gem5::BaseCPU | protectedstatic |
| Group()=delete | gem5::statistics::Group | |
| Group(const Group &)=delete | gem5::statistics::Group | |
| Group(Group *parent, const char *name=nullptr) | gem5::statistics::Group | |
| haltContext(ThreadID thread_num) override | gem5::BaseKvmCPU | virtual |
| handleKvmExit() | gem5::BaseKvmCPU | protectedvirtual |
| handleKvmExitException() | gem5::BaseKvmCPU | protectedvirtual |
| handleKvmExitFailEntry() | gem5::BaseKvmCPU | protectedvirtual |
| handleKvmExitHypercall() | gem5::BaseKvmCPU | protectedvirtual |
| handleKvmExitIO() | gem5::BaseKvmCPU | protectedvirtual |
| handleKvmExitIRQWindowOpen() | gem5::BaseKvmCPU | protectedvirtual |
| handleKvmExitUnknown() | gem5::BaseKvmCPU | protectedvirtual |
| hostFactor | gem5::BaseKvmCPU | private |
| htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause) | gem5::BaseCPU | inlinevirtual |
| hwCycles | gem5::BaseKvmCPU | private |
| hwInstructions | gem5::BaseKvmCPU | private |
| Idle enum value | gem5::BaseKvmCPU | protected |
| init() override | gem5::BaseKvmCPU | virtual |
| initState() | gem5::SimObject | virtual |
| instCnt | gem5::BaseCPU | protected |
| instCount() | gem5::BaseCPU | inline |
| instPort | gem5::BaseKvmCPU | protected |
| instRequestorId() const | gem5::BaseCPU | inline |
| interrupts | gem5::BaseCPU | protected |
| invldPid | gem5::BaseCPU | static |
| ioctl(int request, long p1) const | gem5::BaseKvmCPU | protected |
| ioctl(int request, void *p1) const | gem5::BaseKvmCPU | inlineprotected |
| ioctl(int request) const | gem5::BaseKvmCPU | inlineprotected |
| ioctlRun() override | gem5::BaseArmKvmCPU | protectedvirtual |
| irqAsserted | gem5::BaseArmKvmCPU | protected |
| kick() const | gem5::BaseKvmCPU | inline |
| kvmArmVCpuInit(const kvm_vcpu_init &init) | gem5::BaseArmKvmCPU | protected |
| kvmInterrupt(const struct kvm_interrupt &interrupt) | gem5::BaseKvmCPU | protected |
| kvmNonMaskableInterrupt() | gem5::BaseKvmCPU | protected |
| kvmRun(Tick ticks) override | gem5::BaseArmKvmCPU | protectedvirtual |
| kvmRunDrain() | gem5::BaseKvmCPU | protectedvirtual |
| kvmStateDirty | gem5::BaseKvmCPU | protected |
| loadState(CheckpointIn &cp) | gem5::SimObject | virtual |
| memInvalidate() | gem5::SimObject | inlinevirtual |
| memWriteback() | gem5::SimObject | inlinevirtual |
| mergedParent | gem5::statistics::Group | private |
| mergedStatGroups | gem5::statistics::Group | private |
| mergeStatGroup(Group *block) | gem5::statistics::Group | |
| mmioRing | gem5::BaseKvmCPU | private |
| modelResetPort | gem5::BaseCPU | protected |
| mwait(ThreadID tid, PacketPtr pkt) | gem5::BaseCPU | |
| mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu) | gem5::BaseCPU | |
| name() const | gem5::Named | inlinevirtual |
| Named(const std::string &name_) | gem5::Named | inline |
| nextCycle() const | gem5::Clocked | inline |
| notifyFork() override | gem5::BaseKvmCPU | virtual |
| numContexts() | gem5::BaseCPU | inline |
| numSimulatedCPUs() | gem5::BaseCPU | inlinestatic |
| numSimulatedInsts() | gem5::BaseCPU | inlinestatic |
| numSimulatedOps() | gem5::BaseCPU | inlinestatic |
| numThreads | gem5::BaseCPU | |
| gem5::operator=(const Group &)=delete | gem5::statistics::Group | |
| gem5::Clocked::operator=(Clocked &)=delete | gem5::Clocked | protected |
| pageSize | gem5::BaseKvmCPU | private |
| PARAMS(BaseCPU) | gem5::BaseCPU | |
| Params typedef | gem5::ClockedObject | |
| params() const | gem5::SimObject | inline |
| path | gem5::Serializable | privatestatic |
| perfControlledByTimer | gem5::BaseKvmCPU | private |
| pmuProbePoint(const char *name) | gem5::BaseCPU | protected |
| postInterrupt(ThreadID tid, int int_num, int index) | gem5::BaseCPU | |
| powerGatingOnIdle | gem5::BaseCPU | protected |
| powerState | gem5::ClockedObject | |
| ppActiveCycles | gem5::BaseCPU | protected |
| ppAllCycles | gem5::BaseCPU | protected |
| ppRetiredBranches | gem5::BaseCPU | protected |
| ppRetiredInsts | gem5::BaseCPU | protected |
| ppRetiredInstsPC | gem5::BaseCPU | protected |
| ppRetiredLoads | gem5::BaseCPU | protected |
| ppRetiredStores | gem5::BaseCPU | protected |
| ppSleeping | gem5::BaseCPU | protected |
| preDumpStats() | gem5::statistics::Group | virtual |
| prevDeviceIRQLevel | gem5::BaseArmKvmCPU | protected |
| previousCycle | gem5::BaseCPU | protected |
| previousState | gem5::BaseCPU | protected |
| probeInstCommit(const StaticInstPtr &inst, Addr pc) | gem5::BaseCPU | virtual |
| probeManager | gem5::SimObject | private |
| pwrGatingLatency | gem5::BaseCPU | protected |
| RegIndexVector typedef | gem5::BaseArmKvmCPU | protected |
| registerThreadContexts() | gem5::BaseCPU | |
| regProbeListeners() | gem5::SimObject | virtual |
| regProbePoints() override | gem5::BaseCPU | virtual |
| regStats() override | gem5::BaseCPU | virtual |
| reschedule(Event &event, Tick when, bool always=false) | gem5::EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | gem5::EventManager | inline |
| resetClock() const | gem5::Clocked | inlineprotected |
| resetStats() | gem5::statistics::Group | virtual |
| resolveStat(std::string name) const | gem5::statistics::Group | |
| restartEqThread() | gem5::BaseKvmCPU | private |
| Running enum value | gem5::BaseKvmCPU | protected |
| RunningMMIOPending enum value | gem5::BaseKvmCPU | protected |
| RunningService enum value | gem5::BaseKvmCPU | protected |
| RunningServiceCompletion enum value | gem5::BaseKvmCPU | protected |
| runTimer | gem5::BaseKvmCPU | private |
| schedule(Event &event, Tick when) | gem5::EventManager | inline |
| schedule(Event *event, Tick when) | gem5::EventManager | inline |
| scheduleInstStop(ThreadID tid, Counter insts, std::string cause) | gem5::BaseCPU | |
| scheduleInstStopAnyThread(Counter max_insts) | gem5::BaseCPU | |
| schedulePowerGatingEvent() | gem5::BaseCPU | |
| scheduleSimpointsInstStop(std::vector< Counter > inst_starts) | gem5::BaseCPU | |
| Serializable() | gem5::Serializable | |
| serialize(CheckpointOut &cp) const override | gem5::BaseCPU | virtual |
| serializeAll(const std::string &cpt_dir) | gem5::SimObject | static |
| serializeSection(CheckpointOut &cp, const char *name) const | gem5::Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | gem5::Serializable | inline |
| serializeThread(CheckpointOut &cp, ThreadID tid) const override | gem5::BaseKvmCPU | virtual |
| setCurTick(Tick newVal) | gem5::EventManager | inline |
| setFPUState(const struct kvm_fpu &state) | gem5::BaseKvmCPU | protected |
| setOneReg(uint64_t id, const void *addr) | gem5::BaseKvmCPU | protected |
| setOneReg(uint64_t id, uint64_t value) | gem5::BaseKvmCPU | inlineprotected |
| setOneReg(uint64_t id, uint32_t value) | gem5::BaseKvmCPU | inlineprotected |
| setPid(uint32_t pid) | gem5::BaseCPU | inline |
| setRegisters(const struct kvm_regs ®s) | gem5::BaseKvmCPU | protected |
| setReset(bool state) | gem5::BaseCPU | virtual |
| setSignalMask(const sigset_t *mask) | gem5::BaseKvmCPU | protected |
| setSimObjectResolver(SimObjectResolver *resolver) | gem5::SimObject | static |
| setSpecialRegisters(const struct kvm_sregs ®s) | gem5::BaseKvmCPU | protected |
| setupCounters() | gem5::BaseKvmCPU | private |
| setupInstCounter(uint64_t period=0) | gem5::BaseKvmCPU | private |
| setupInstStop() | gem5::BaseKvmCPU | private |
| setupSignalHandler() | gem5::BaseKvmCPU | private |
| signalDrainDone() const | gem5::Drainable | inlineprotected |
| SimObject(const Params &p) | gem5::SimObject | |
| SimObjectList typedef | gem5::SimObject | private |
| simObjectList | gem5::SimObject | privatestatic |
| socketId() const | gem5::BaseCPU | inline |
| startup() override | gem5::BaseArmKvmCPU | virtual |
| statGroups | gem5::statistics::Group | private |
| stats | gem5::BaseKvmCPU | |
| Status enum name | gem5::BaseKvmCPU | protected |
| stutterPC(PCStateBase &pc) const override | gem5::BaseArmKvmCPU | inlineprotectedvirtual |
| suspendContext(ThreadID thread_num) override | gem5::BaseKvmCPU | virtual |
| switchedOut() const | gem5::BaseCPU | inline |
| switchOut() override | gem5::BaseKvmCPU | virtual |
| syncKvmState() | gem5::BaseKvmCPU | protected |
| syncThreadContext() | gem5::BaseKvmCPU | protected |
| syscallRetryLatency | gem5::BaseCPU | |
| system | gem5::BaseCPU | |
| takeOverFrom(BaseCPU *cpu) override | gem5::BaseKvmCPU | virtual |
| taskId() const | gem5::BaseCPU | inline |
| taskId(uint32_t id) | gem5::BaseCPU | inline |
| tc | gem5::BaseKvmCPU | |
| thread | gem5::BaseKvmCPU | |
| threadContextDirty | gem5::BaseKvmCPU | protected |
| threadContexts | gem5::BaseCPU | protected |
| tick() | gem5::BaseKvmCPU | protected |
| tickEvent | gem5::BaseKvmCPU | private |
| ticksToCycles(Tick t) const | gem5::Clocked | inline |
| totalInsts() const override | gem5::BaseKvmCPU | virtual |
| totalOps() const override | gem5::BaseKvmCPU | virtual |
| traceFunctions(Addr pc) | gem5::BaseCPU | inline |
| traceFunctionsInternal(Addr pc) | gem5::BaseCPU | private |
| tracer | gem5::BaseCPU | protected |
| tryDrain() | gem5::BaseKvmCPU | private |
| tryGetRegList(uint64_t nelem) const | gem5::BaseArmKvmCPU | private |
| unserialize(CheckpointIn &cp) override | gem5::BaseCPU | virtual |
| unserializeSection(CheckpointIn &cp, const char *name) | gem5::Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | gem5::Serializable | inline |
| unserializeThread(CheckpointIn &cp, ThreadID tid) override | gem5::BaseKvmCPU | virtual |
| update() const | gem5::Clocked | inlineprivate |
| updateClockPeriod() | gem5::Clocked | inline |
| updateCycleCounters(CPUState state) | gem5::BaseCPU | inlineprotected |
| updateKvmState()=0 | gem5::BaseKvmCPU | protectedpure virtual |
| updateThreadContext()=0 | gem5::BaseKvmCPU | protectedpure virtual |
| usePerf | gem5::BaseKvmCPU | protected |
| vcpuFD | gem5::BaseKvmCPU | private |
| vcpuID | gem5::BaseKvmCPU | protected |
| vcpuMMapSize | gem5::BaseKvmCPU | private |
| vcpuThread | gem5::BaseKvmCPU | protected |
| verifyMemoryMode() const override | gem5::BaseKvmCPU | virtual |
| virtTimerPin | gem5::BaseArmKvmCPU | protected |
| vm | gem5::BaseKvmCPU | |
| voltage() const | gem5::Clocked | inline |
| wakeup(ThreadID tid=0) override | gem5::BaseKvmCPU | virtual |
| wakeupEventQueue(Tick when=(Tick) -1) | gem5::EventManager | inline |
| workItemBegin() | gem5::BaseCPU | inline |
| workItemEnd() | gem5::BaseCPU | inline |
| ~BaseArmKvmCPU() | gem5::BaseArmKvmCPU | virtual |
| ~BaseCPU() | gem5::BaseCPU | virtual |
| ~BaseKvmCPU() | gem5::BaseKvmCPU | virtual |
| ~Clocked() | gem5::Clocked | inlineprotectedvirtual |
| ~Drainable() | gem5::Drainable | protectedvirtual |
| ~Group() | gem5::statistics::Group | virtual |
| ~Named()=default | gem5::Named | virtual |
| ~Serializable() | gem5::Serializable | virtual |
| ~SimObject() | gem5::SimObject | virtual |