| _cacheLineSize | gem5::ComputeUnit | private |
| _drainManager | gem5::Drainable | private |
| _drainState | gem5::Drainable | mutableprivate |
| _name | gem5::Named | private |
| _numBarrierSlots | gem5::ComputeUnit | private |
| _objNameResolver | gem5::SimObject | privatestatic |
| _params | gem5::SimObject | protected |
| _requestorId | gem5::ComputeUnit | protected |
| activeWaves | gem5::ComputeUnit | |
| addStat(statistics::Info *info) | gem5::statistics::Group | |
| addStatGroup(const char *name, Group *block) | gem5::statistics::Group | |
| allAtBarrier(int bar_id) | gem5::ComputeUnit | |
| barrierSlot(int bar_id) | gem5::ComputeUnit | inlineprivate |
| cacheLineBits | gem5::ComputeUnit | private |
| cacheLineSize() const | gem5::ComputeUnit | inline |
| clockDomain | gem5::Clocked | private |
| Clocked(ClockDomain &clk_domain) | gem5::Clocked | inlineprotected |
| Clocked(Clocked &)=delete | gem5::Clocked | protected |
| clockEdge(Cycles cycles=Cycles(0)) const | gem5::Clocked | inline |
| ClockedObject(const ClockedObjectParams &p) | gem5::ClockedObject | |
| clockPeriod() const | gem5::Clocked | inline |
| clockPeriodUpdated() | gem5::Clocked | inlineprotectedvirtual |
| coalescerToVrfBusWidth | gem5::ComputeUnit | |
| ComputeUnit(const Params &p) | gem5::ComputeUnit | |
| countPages | gem5::ComputeUnit | |
| cu_id | gem5::ComputeUnit | |
| curCycle() const | gem5::Clocked | inline |
| currentSection() | gem5::Serializable | static |
| cycle | gem5::Clocked | mutableprivate |
| cyclesToTicks(Cycles c) const | gem5::Clocked | inline |
| debugSegFault | gem5::ComputeUnit | |
| decMaxBarrierCnt(int bar_id) | gem5::ComputeUnit | |
| deleteFromPipeMap(Wavefront *w) | gem5::ComputeUnit | |
| deschedule(Event &event) | gem5::EventManager | inline |
| deschedule(Event *event) | gem5::EventManager | inline |
| dispWorkgroup(HSAQueueEntry *task, int num_wfs_in_wg) | gem5::ComputeUnit | |
| dmDrain() | gem5::Drainable | private |
| dmDrainResume() | gem5::Drainable | private |
| doFlush(GPUDynInstPtr gpuDynInst) | gem5::ComputeUnit | |
| doInvalidate(RequestPtr req, int kernId) | gem5::ComputeUnit | |
| doSmReturn(GPUDynInstPtr gpuDynInst) | gem5::ComputeUnit | |
| doSQCInvalidate(RequestPtr req, int kernId) | gem5::ComputeUnit | |
| dpBypassLength() const | gem5::ComputeUnit | inline |
| dpBypassPipeLength | gem5::ComputeUnit | |
| drain() override | gem5::SimObject | inlinevirtual |
| Drainable() | gem5::Drainable | protected |
| drainResume() | gem5::Drainable | inlineprotectedvirtual |
| drainState() const | gem5::Drainable | inline |
| EventManager(EventManager &em) | gem5::EventManager | inline |
| EventManager(EventManager *em) | gem5::EventManager | inline |
| EventManager(EventQueue *eq) | gem5::EventManager | inline |
| eventq | gem5::EventManager | protected |
| eventQueue() const | gem5::EventManager | inline |
| exec() | gem5::ComputeUnit | |
| exec_policy | gem5::ComputeUnit | |
| execStage | gem5::ComputeUnit | |
| exitCallback() | gem5::ComputeUnit | |
| fetch(PacketPtr pkt, Wavefront *wavefront) | gem5::ComputeUnit | |
| fetchStage | gem5::ComputeUnit | |
| fillKernelState(Wavefront *w, HSAQueueEntry *task) | gem5::ComputeUnit | |
| find(const char *name) | gem5::SimObject | static |
| firstMemUnit() const | gem5::ComputeUnit | |
| freeBarrierIds | gem5::ComputeUnit | private |
| frequency() const | gem5::Clocked | inline |
| functionalTLB | gem5::ComputeUnit | |
| generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream) | gem5::Serializable | static |
| getAndIncSeqNum() | gem5::ComputeUnit | inline |
| getCacheLineBits() const | gem5::ComputeUnit | inline |
| getFreeBarrierId() | gem5::ComputeUnit | inlineprivate |
| getLds() const | gem5::ComputeUnit | inline |
| getPort(const std::string &if_name, PortID idx) override | gem5::ComputeUnit | inlinevirtual |
| getProbeManager() | gem5::SimObject | |
| getRefCounter(const uint32_t dispatchId, const uint32_t wgId) const | gem5::ComputeUnit | |
| getSimObjectResolver() | gem5::SimObject | static |
| getStatGroups() const | gem5::statistics::Group | |
| getStats() const | gem5::statistics::Group | |
| getTokenManager() | gem5::ComputeUnit | inline |
| glbMemToVrfBus | gem5::ComputeUnit | |
| globalMemoryPipe | gem5::ComputeUnit | |
| globalSeqNum | gem5::ComputeUnit | private |
| gmTokenPort | gem5::ComputeUnit | |
| Group()=delete | gem5::statistics::Group | |
| Group(const Group &)=delete | gem5::statistics::Group | |
| Group(Group *parent, const char *name=nullptr) | gem5::statistics::Group | |
| handleMemPacket(PacketPtr pkt, int memport_index) | gem5::ComputeUnit | |
| handleSQCReturn(PacketPtr pkt) | gem5::ComputeUnit | |
| hasDispResources(HSAQueueEntry *task, int &num_wfs_in_wg) | gem5::ComputeUnit | |
| headTailMap | gem5::ComputeUnit | private |
| idleCUTimeout | gem5::ComputeUnit | |
| idleWfs | gem5::ComputeUnit | |
| incNumAtBarrier(int bar_id) | gem5::ComputeUnit | |
| init() override | gem5::ComputeUnit | virtual |
| initiateFetch(Wavefront *wavefront) | gem5::ComputeUnit | |
| initState() | gem5::SimObject | virtual |
| injectGlobalMemFence(GPUDynInstPtr gpuDynInst, bool kernelMemSync, RequestPtr req=nullptr) | gem5::ComputeUnit | |
| insertInPipeMap(Wavefront *w) | gem5::ComputeUnit | |
| instExecPerSimd | gem5::ComputeUnit | |
| isDone() const | gem5::ComputeUnit | |
| issuePeriod | gem5::ComputeUnit | |
| isVectorAluIdle(uint32_t simdId) const | gem5::ComputeUnit | |
| lastExecCycle | gem5::ComputeUnit | |
| lastMemUnit() const | gem5::ComputeUnit | |
| lastVaddrCU | gem5::ComputeUnit | |
| lastVaddrSimd | gem5::ComputeUnit | |
| lastVaddrWF | gem5::ComputeUnit | |
| lds | gem5::ComputeUnit | protected |
| ldsPort | gem5::ComputeUnit | |
| loadBusLength() const | gem5::ComputeUnit | inline |
| loadState(CheckpointIn &cp) | gem5::SimObject | virtual |
| localMemBarrier | gem5::ComputeUnit | |
| localMemoryPipe | gem5::ComputeUnit | |
| locMemToVrfBus | gem5::ComputeUnit | |
| mapWaveToGlobalMem(Wavefront *w) const | gem5::ComputeUnit | |
| mapWaveToLocalMem(Wavefront *w) const | gem5::ComputeUnit | |
| mapWaveToScalarAlu(Wavefront *w) const | gem5::ComputeUnit | |
| mapWaveToScalarAluGlobalIdx(Wavefront *w) const | gem5::ComputeUnit | |
| mapWaveToScalarMem(Wavefront *w) const | gem5::ComputeUnit | |
| maxBarrierCnt(int bar_id) | gem5::ComputeUnit | |
| memInvalidate() | gem5::SimObject | inlinevirtual |
| memPort | gem5::ComputeUnit | |
| memPortTokens | gem5::ComputeUnit | |
| memWriteback() | gem5::SimObject | inlinevirtual |
| mergedParent | gem5::statistics::Group | private |
| mergedStatGroups | gem5::statistics::Group | private |
| mergeStatGroup(Group *block) | gem5::statistics::Group | |
| name() const | gem5::Named | inlinevirtual |
| Named(const std::string &name_) | gem5::Named | inline |
| nextCycle() const | gem5::Clocked | inline |
| notifyFork() | gem5::Drainable | inlinevirtual |
| numAtBarrier(int bar_id) | gem5::ComputeUnit | |
| numBarrierSlots() const | gem5::ComputeUnit | inline |
| numCyclesPerLoadTransfer | gem5::ComputeUnit | |
| numCyclesPerStoreTransfer | gem5::ComputeUnit | |
| numExeUnits() const | gem5::ComputeUnit | |
| numScalarALUs | gem5::ComputeUnit | |
| numScalarMemUnits | gem5::ComputeUnit | |
| numScalarRegsPerSimd | gem5::ComputeUnit | |
| numVecRegsPerSimd | gem5::ComputeUnit | |
| numVectorALUs | gem5::ComputeUnit | |
| numVectorGlobalMemUnits | gem5::ComputeUnit | |
| numVectorSharedMemUnits | gem5::ComputeUnit | |
| numWfsToSched | gem5::ComputeUnit | |
| numYetToReachBarrier(int bar_id) | gem5::ComputeUnit | |
| operandNetworkLength | gem5::ComputeUnit | |
| gem5::operator=(const Group &)=delete | gem5::statistics::Group | |
| gem5::Clocked::operator=(Clocked &)=delete | gem5::Clocked | protected |
| oprNetPipeLength() const | gem5::ComputeUnit | inline |
| pageAccesses | gem5::ComputeUnit | |
| pageDataStruct typedef | gem5::ComputeUnit | |
| pagesTouched | gem5::ComputeUnit | |
| Params typedef | gem5::ComputeUnit | |
| params() const | gem5::SimObject | inline |
| path | gem5::Serializable | privatestatic |
| perLaneTLB | gem5::ComputeUnit | |
| pipeMap | gem5::ComputeUnit | |
| powerState | gem5::ClockedObject | |
| preDumpStats() | gem5::statistics::Group | virtual |
| prefetchDepth | gem5::ComputeUnit | |
| prefetchStride | gem5::ComputeUnit | |
| prefetchType | gem5::ComputeUnit | |
| probeManager | gem5::SimObject | private |
| processFetchReturn(PacketPtr pkt) | gem5::ComputeUnit | |
| processTimingPacket(PacketPtr pkt) | gem5::ComputeUnit | |
| registerManager | gem5::ComputeUnit | |
| regProbeListeners() | gem5::SimObject | virtual |
| regProbePoints() | gem5::SimObject | virtual |
| regStats() | gem5::statistics::Group | virtual |
| releaseBarrier(int bar_id) | gem5::ComputeUnit | |
| releaseWFsFromBarrier(int bar_id) | gem5::ComputeUnit | |
| req_tick_latency | gem5::ComputeUnit | |
| requestorId() | gem5::ComputeUnit | inline |
| reschedule(Event &event, Tick when, bool always=false) | gem5::EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | gem5::EventManager | inline |
| resetBarrier(int bar_id) | gem5::ComputeUnit | |
| resetClock() const | gem5::Clocked | inlineprotected |
| resetRegisterPool() | gem5::ComputeUnit | |
| resetStats() | gem5::statistics::Group | virtual |
| resolveStat(std::string name) const | gem5::statistics::Group | |
| resp_tick_latency | gem5::ComputeUnit | |
| rfc | gem5::ComputeUnit | |
| rfcLength() const | gem5::ComputeUnit | inline |
| rfcPipeLength | gem5::ComputeUnit | |
| scalar_req_tick_latency | gem5::ComputeUnit | |
| scalar_resp_tick_latency | gem5::ComputeUnit | |
| scalarALUs | gem5::ComputeUnit | |
| scalarDataPort | gem5::ComputeUnit | |
| scalarDTLBPort | gem5::ComputeUnit | |
| scalarMemoryPipe | gem5::ComputeUnit | |
| scalarMemToSrfBus | gem5::ComputeUnit | |
| scalarMemUnit | gem5::ComputeUnit | |
| scalarPipeLength() const | gem5::ComputeUnit | inline |
| scalarPipeStages | gem5::ComputeUnit | |
| scalarRegsReserved | gem5::ComputeUnit | |
| schedule(Event &event, Tick when) | gem5::EventManager | inline |
| schedule(Event *event, Tick when) | gem5::EventManager | inline |
| scheduleStage | gem5::ComputeUnit | |
| scheduleToExecute | gem5::ComputeUnit | private |
| scoreboardCheckStage | gem5::ComputeUnit | |
| scoreboardCheckToSchedule | gem5::ComputeUnit | private |
| sendInvL2(Addr paddr) | gem5::ComputeUnit | |
| sendRequest(GPUDynInstPtr gpuDynInst, PortID index, PacketPtr pkt) | gem5::ComputeUnit | |
| sendScalarRequest(GPUDynInstPtr gpuDynInst, PacketPtr pkt) | gem5::ComputeUnit | |
| sendToLds(GPUDynInstPtr gpuDynInst) | gem5::ComputeUnit | |
| Serializable() | gem5::Serializable | |
| serialize(CheckpointOut &cp) const override | gem5::ClockedObject | virtual |
| serializeAll(const std::string &cpt_dir) | gem5::SimObject | static |
| serializeSection(CheckpointOut &cp, const char *name) const | gem5::Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | gem5::Serializable | inline |
| setCurTick(Tick newVal) | gem5::EventManager | inline |
| setSimObjectResolver(SimObjectResolver *resolver) | gem5::SimObject | static |
| shader | gem5::ComputeUnit | |
| signalDrainDone() const | gem5::Drainable | inlineprotected |
| simdUnitWidth() const | gem5::ComputeUnit | inline |
| simdWidth | gem5::ComputeUnit | |
| SimObject(const Params &p) | gem5::SimObject | |
| SimObjectList typedef | gem5::SimObject | private |
| simObjectList | gem5::SimObject | privatestatic |
| spBypassLength() const | gem5::ComputeUnit | inline |
| spBypassPipeLength | gem5::ComputeUnit | |
| sqcPort | gem5::ComputeUnit | |
| sqcTLBPort | gem5::ComputeUnit | |
| srf | gem5::ComputeUnit | |
| srf_scm_bus_latency | gem5::ComputeUnit | |
| srfToScalarMemPipeBus | gem5::ComputeUnit | |
| startup() | gem5::SimObject | virtual |
| startWavefront(Wavefront *w, int waveId, LdsChunk *ldsChunk, HSAQueueEntry *task, int bar_id, bool fetchContext=false) | gem5::ComputeUnit | |
| statGroups | gem5::statistics::Group | private |
| stats | gem5::ComputeUnit | |
| storeBusLength() const | gem5::ComputeUnit | inline |
| tick | gem5::Clocked | mutableprivate |
| tickEvent | gem5::ComputeUnit | |
| ticksToCycles(Tick t) const | gem5::Clocked | inline |
| tlbPort | gem5::ComputeUnit | |
| unserialize(CheckpointIn &cp) override | gem5::ClockedObject | virtual |
| unserializeSection(CheckpointIn &cp, const char *name) | gem5::Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | gem5::Serializable | inline |
| update() const | gem5::Clocked | inlineprivate |
| updateClockPeriod() | gem5::Clocked | inline |
| updateInstStats(GPUDynInstPtr gpuDynInst) | gem5::ComputeUnit | |
| updatePageDivergenceDist(Addr addr) | gem5::ComputeUnit | |
| vectorALUs | gem5::ComputeUnit | |
| vectorGlobalMemUnit | gem5::ComputeUnit | |
| vectorRegsReserved | gem5::ComputeUnit | |
| vectorSharedMemUnit | gem5::ComputeUnit | |
| voltage() const | gem5::Clocked | inline |
| vramRequestorId() | gem5::ComputeUnit | |
| vrf | gem5::ComputeUnit | |
| vrf_gm_bus_latency | gem5::ComputeUnit | |
| vrf_lm_bus_latency | gem5::ComputeUnit | |
| vrfToCoalescerBusWidth | gem5::ComputeUnit | |
| vrfToGlobalMemPipeBus | gem5::ComputeUnit | |
| vrfToLocalMemPipeBus | gem5::ComputeUnit | |
| wakeupEventQueue(Tick when=(Tick) -1) | gem5::EventManager | inline |
| wavefrontSize | gem5::ComputeUnit | private |
| wfBarrierSlots | gem5::ComputeUnit | private |
| wfList | gem5::ComputeUnit | |
| wfSize() const | gem5::ComputeUnit | inline |
| ~Clocked() | gem5::Clocked | inlineprotectedvirtual |
| ~ComputeUnit() | gem5::ComputeUnit | |
| ~Drainable() | gem5::Drainable | protectedvirtual |
| ~Group() | gem5::statistics::Group | virtual |
| ~Named()=default | gem5::Named | virtual |
| ~Serializable() | gem5::Serializable | virtual |
| ~SimObject() | gem5::SimObject | virtual |