gem5  v21.1.0.2
gem5::ComputeUnit Member List

This is the complete list of members for gem5::ComputeUnit, including all inherited members.

_cacheLineSizegem5::ComputeUnitprivate
_drainManagergem5::Drainableprivate
_drainStategem5::Drainablemutableprivate
_namegem5::Namedprivate
_numBarrierSlotsgem5::ComputeUnitprivate
_objNameResolvergem5::SimObjectprivatestatic
_paramsgem5::SimObjectprotected
_requestorIdgem5::ComputeUnitprotected
activeWavesgem5::ComputeUnit
addStat(statistics::Info *info)gem5::statistics::Group
addStatGroup(const char *name, Group *block)gem5::statistics::Group
allAtBarrier(int bar_id)gem5::ComputeUnit
barrierSlot(int bar_id)gem5::ComputeUnitinlineprivate
cacheLineBitsgem5::ComputeUnitprivate
cacheLineSize() constgem5::ComputeUnitinline
clockDomaingem5::Clockedprivate
Clocked(ClockDomain &clk_domain)gem5::Clockedinlineprotected
Clocked(Clocked &)=deletegem5::Clockedprotected
clockEdge(Cycles cycles=Cycles(0)) constgem5::Clockedinline
ClockedObject(const ClockedObjectParams &p)gem5::ClockedObject
clockPeriod() constgem5::Clockedinline
clockPeriodUpdated()gem5::Clockedinlineprotectedvirtual
coalescerToVrfBusWidthgem5::ComputeUnit
ComputeUnit(const Params &p)gem5::ComputeUnit
countPagesgem5::ComputeUnit
cu_idgem5::ComputeUnit
curCycle() constgem5::Clockedinline
currentSection()gem5::Serializablestatic
cyclegem5::Clockedmutableprivate
cyclesToTicks(Cycles c) constgem5::Clockedinline
debugSegFaultgem5::ComputeUnit
decMaxBarrierCnt(int bar_id)gem5::ComputeUnit
deleteFromPipeMap(Wavefront *w)gem5::ComputeUnit
deschedule(Event &event)gem5::EventManagerinline
deschedule(Event *event)gem5::EventManagerinline
dispWorkgroup(HSAQueueEntry *task, int num_wfs_in_wg)gem5::ComputeUnit
dmDrain()gem5::Drainableprivate
dmDrainResume()gem5::Drainableprivate
doFlush(GPUDynInstPtr gpuDynInst)gem5::ComputeUnit
doInvalidate(RequestPtr req, int kernId)gem5::ComputeUnit
doSmReturn(GPUDynInstPtr gpuDynInst)gem5::ComputeUnit
dpBypassLength() constgem5::ComputeUnitinline
dpBypassPipeLengthgem5::ComputeUnit
drain() overridegem5::SimObjectinlinevirtual
Drainable()gem5::Drainableprotected
drainResume()gem5::Drainableinlineprotectedvirtual
drainState() constgem5::Drainableinline
EventManager(EventManager &em)gem5::EventManagerinline
EventManager(EventManager *em)gem5::EventManagerinline
EventManager(EventQueue *eq)gem5::EventManagerinline
eventqgem5::EventManagerprotected
eventQueue() constgem5::EventManagerinline
exec()gem5::ComputeUnit
exec_policygem5::ComputeUnit
execStagegem5::ComputeUnit
exitCallback()gem5::ComputeUnit
fetch(PacketPtr pkt, Wavefront *wavefront)gem5::ComputeUnit
fetchStagegem5::ComputeUnit
fillKernelState(Wavefront *w, HSAQueueEntry *task)gem5::ComputeUnit
find(const char *name)gem5::SimObjectstatic
firstMemUnit() constgem5::ComputeUnit
freeBarrierIdsgem5::ComputeUnitprivate
frequency() constgem5::Clockedinline
functionalTLBgem5::ComputeUnit
generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream)gem5::Serializablestatic
getAndIncSeqNum()gem5::ComputeUnitinline
getCacheLineBits() constgem5::ComputeUnitinline
getFreeBarrierId()gem5::ComputeUnitinlineprivate
getLds() constgem5::ComputeUnitinline
getPort(const std::string &if_name, PortID idx) overridegem5::ComputeUnitinlinevirtual
getProbeManager()gem5::SimObject
getRefCounter(const uint32_t dispatchId, const uint32_t wgId) constgem5::ComputeUnit
getSimObjectResolver()gem5::SimObjectstatic
getStatGroups() constgem5::statistics::Group
getStats() constgem5::statistics::Group
getTokenManager()gem5::ComputeUnitinline
glbMemToVrfBusgem5::ComputeUnit
globalMemoryPipegem5::ComputeUnit
globalSeqNumgem5::ComputeUnitprivate
gmTokenPortgem5::ComputeUnit
Group()=deletegem5::statistics::Group
Group(const Group &)=deletegem5::statistics::Group
Group(Group *parent, const char *name=nullptr)gem5::statistics::Group
handleMemPacket(PacketPtr pkt, int memport_index)gem5::ComputeUnit
hasDispResources(HSAQueueEntry *task, int &num_wfs_in_wg)gem5::ComputeUnit
headTailMapgem5::ComputeUnitprivate
idleCUTimeoutgem5::ComputeUnit
idleWfsgem5::ComputeUnit
incNumAtBarrier(int bar_id)gem5::ComputeUnit
init() overridegem5::ComputeUnitvirtual
initiateFetch(Wavefront *wavefront)gem5::ComputeUnit
initState()gem5::SimObjectvirtual
injectGlobalMemFence(GPUDynInstPtr gpuDynInst, bool kernelMemSync, RequestPtr req=nullptr)gem5::ComputeUnit
insertInPipeMap(Wavefront *w)gem5::ComputeUnit
instExecPerSimdgem5::ComputeUnit
isDone() constgem5::ComputeUnit
issuePeriodgem5::ComputeUnit
isVectorAluIdle(uint32_t simdId) constgem5::ComputeUnit
lastExecCyclegem5::ComputeUnit
lastMemUnit() constgem5::ComputeUnit
lastVaddrCUgem5::ComputeUnit
lastVaddrSimdgem5::ComputeUnit
lastVaddrWFgem5::ComputeUnit
ldsgem5::ComputeUnitprotected
ldsPortgem5::ComputeUnit
loadBusLength() constgem5::ComputeUnitinline
loadState(CheckpointIn &cp)gem5::SimObjectvirtual
localMemBarriergem5::ComputeUnit
localMemoryPipegem5::ComputeUnit
locMemToVrfBusgem5::ComputeUnit
mapWaveToGlobalMem(Wavefront *w) constgem5::ComputeUnit
mapWaveToLocalMem(Wavefront *w) constgem5::ComputeUnit
mapWaveToScalarAlu(Wavefront *w) constgem5::ComputeUnit
mapWaveToScalarAluGlobalIdx(Wavefront *w) constgem5::ComputeUnit
mapWaveToScalarMem(Wavefront *w) constgem5::ComputeUnit
maxBarrierCnt(int bar_id)gem5::ComputeUnit
memInvalidate()gem5::SimObjectinlinevirtual
memPortgem5::ComputeUnit
memPortTokensgem5::ComputeUnit
memWriteback()gem5::SimObjectinlinevirtual
mergedParentgem5::statistics::Groupprivate
mergedStatGroupsgem5::statistics::Groupprivate
mergeStatGroup(Group *block)gem5::statistics::Group
name() constgem5::Namedinlinevirtual
Named(const std::string &name_)gem5::Namedinline
nextCycle() constgem5::Clockedinline
notifyFork()gem5::Drainableinlinevirtual
numAtBarrier(int bar_id)gem5::ComputeUnit
numBarrierSlots() constgem5::ComputeUnitinline
numCyclesPerLoadTransfergem5::ComputeUnit
numCyclesPerStoreTransfergem5::ComputeUnit
numExeUnits() constgem5::ComputeUnit
numScalarALUsgem5::ComputeUnit
numScalarMemUnitsgem5::ComputeUnit
numScalarRegsPerSimdgem5::ComputeUnit
numVecRegsPerSimdgem5::ComputeUnit
numVectorALUsgem5::ComputeUnit
numVectorGlobalMemUnitsgem5::ComputeUnit
numVectorSharedMemUnitsgem5::ComputeUnit
numWfsToSchedgem5::ComputeUnit
numYetToReachBarrier(int bar_id)gem5::ComputeUnit
operandNetworkLengthgem5::ComputeUnit
gem5::operator=(const Group &)=deletegem5::statistics::Group
gem5::Clocked::operator=(Clocked &)=deletegem5::Clockedprotected
oprNetPipeLength() constgem5::ComputeUnitinline
pageAccessesgem5::ComputeUnit
pageDataStruct typedefgem5::ComputeUnit
pagesTouchedgem5::ComputeUnit
Params typedefgem5::ComputeUnit
params() constgem5::SimObjectinline
pathgem5::Serializableprivatestatic
perLaneTLBgem5::ComputeUnit
pipeMapgem5::ComputeUnit
powerStategem5::ClockedObject
preDumpStats()gem5::statistics::Groupvirtual
prefetchDepthgem5::ComputeUnit
prefetchStridegem5::ComputeUnit
prefetchTypegem5::ComputeUnit
probeManagergem5::SimObjectprivate
processFetchReturn(PacketPtr pkt)gem5::ComputeUnit
processTimingPacket(PacketPtr pkt)gem5::ComputeUnit
registerManagergem5::ComputeUnit
regProbeListeners()gem5::SimObjectvirtual
regProbePoints()gem5::SimObjectvirtual
regStats()gem5::statistics::Groupvirtual
releaseBarrier(int bar_id)gem5::ComputeUnit
releaseWFsFromBarrier(int bar_id)gem5::ComputeUnit
req_tick_latencygem5::ComputeUnit
requestorId()gem5::ComputeUnitinline
reschedule(Event &event, Tick when, bool always=false)gem5::EventManagerinline
reschedule(Event *event, Tick when, bool always=false)gem5::EventManagerinline
resetBarrier(int bar_id)gem5::ComputeUnit
resetClock() constgem5::Clockedinlineprotected
resetRegisterPool()gem5::ComputeUnit
resetStats()gem5::statistics::Groupvirtual
resolveStat(std::string name) constgem5::statistics::Group
resp_tick_latencygem5::ComputeUnit
scalarALUsgem5::ComputeUnit
scalarDataPortgem5::ComputeUnit
scalarDTLBPortgem5::ComputeUnit
scalarMemoryPipegem5::ComputeUnit
scalarMemToSrfBusgem5::ComputeUnit
scalarMemUnitgem5::ComputeUnit
scalarPipeLength() constgem5::ComputeUnitinline
scalarPipeStagesgem5::ComputeUnit
scalarRegsReservedgem5::ComputeUnit
schedule(Event &event, Tick when)gem5::EventManagerinline
schedule(Event *event, Tick when)gem5::EventManagerinline
scheduleStagegem5::ComputeUnit
scheduleToExecutegem5::ComputeUnitprivate
scoreboardCheckStagegem5::ComputeUnit
scoreboardCheckToSchedulegem5::ComputeUnitprivate
sendRequest(GPUDynInstPtr gpuDynInst, PortID index, PacketPtr pkt)gem5::ComputeUnit
sendScalarRequest(GPUDynInstPtr gpuDynInst, PacketPtr pkt)gem5::ComputeUnit
sendToLds(GPUDynInstPtr gpuDynInst)gem5::ComputeUnit
Serializable()gem5::Serializable
serialize(CheckpointOut &cp) const overridegem5::ClockedObjectvirtual
serializeAll(const std::string &cpt_dir)gem5::SimObjectstatic
serializeSection(CheckpointOut &cp, const char *name) constgem5::Serializable
serializeSection(CheckpointOut &cp, const std::string &name) constgem5::Serializableinline
setCurTick(Tick newVal)gem5::EventManagerinline
setSimObjectResolver(SimObjectResolver *resolver)gem5::SimObjectstatic
shadergem5::ComputeUnit
signalDrainDone() constgem5::Drainableinlineprotected
simdUnitWidth() constgem5::ComputeUnitinline
simdWidthgem5::ComputeUnit
SimObject(const Params &p)gem5::SimObject
SimObjectList typedefgem5::SimObjectprivate
simObjectListgem5::SimObjectprivatestatic
spBypassLength() constgem5::ComputeUnitinline
spBypassPipeLengthgem5::ComputeUnit
sqcPortgem5::ComputeUnit
sqcTLBPortgem5::ComputeUnit
srfgem5::ComputeUnit
srf_scm_bus_latencygem5::ComputeUnit
srfToScalarMemPipeBusgem5::ComputeUnit
startup()gem5::SimObjectvirtual
startWavefront(Wavefront *w, int waveId, LdsChunk *ldsChunk, HSAQueueEntry *task, int bar_id, bool fetchContext=false)gem5::ComputeUnit
statGroupsgem5::statistics::Groupprivate
statsgem5::ComputeUnit
storeBusLength() constgem5::ComputeUnitinline
tickgem5::Clockedmutableprivate
tickEventgem5::ComputeUnit
ticksToCycles(Tick t) constgem5::Clockedinline
tlbPortgem5::ComputeUnit
unserialize(CheckpointIn &cp) overridegem5::ClockedObjectvirtual
unserializeSection(CheckpointIn &cp, const char *name)gem5::Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)gem5::Serializableinline
update() constgem5::Clockedinlineprivate
updateClockPeriod()gem5::Clockedinline
updateInstStats(GPUDynInstPtr gpuDynInst)gem5::ComputeUnit
updatePageDivergenceDist(Addr addr)gem5::ComputeUnit
vectorALUsgem5::ComputeUnit
vectorGlobalMemUnitgem5::ComputeUnit
vectorRegsReservedgem5::ComputeUnit
vectorSharedMemUnitgem5::ComputeUnit
voltage() constgem5::Clockedinline
vrfgem5::ComputeUnit
vrf_gm_bus_latencygem5::ComputeUnit
vrf_lm_bus_latencygem5::ComputeUnit
vrfToCoalescerBusWidthgem5::ComputeUnit
vrfToGlobalMemPipeBusgem5::ComputeUnit
vrfToLocalMemPipeBusgem5::ComputeUnit
wakeupEventQueue(Tick when=(Tick) -1)gem5::EventManagerinline
wavefrontSizegem5::ComputeUnitprivate
wfBarrierSlotsgem5::ComputeUnitprivate
wfListgem5::ComputeUnit
wfSize() constgem5::ComputeUnitinline
~Clocked()gem5::Clockedinlineprotectedvirtual
~ComputeUnit()gem5::ComputeUnit
~Drainable()gem5::Drainableprotectedvirtual
~Group()gem5::statistics::Groupvirtual
~Named()=defaultgem5::Namedvirtual
~Serializable()gem5::Serializablevirtual
~SimObject()gem5::SimObjectvirtual

Generated on Tue Sep 21 2021 12:27:24 for gem5 by doxygen 1.8.17