gem5 v24.0.0.0
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device.hh
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1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.*
36 */
37
38
43#ifndef __DEV_I2C_DEVICE_HH__
44#define __DEV_I2C_DEVICE_HH__
45
46#include "base/types.hh"
47#include "params/I2CDevice.hh"
48#include "sim/sim_object.hh"
49
50namespace gem5
51{
52
53class I2CDevice : public SimObject
54{
55
56 protected:
57
58 uint8_t _addr;
59
60 public:
61
62 I2CDevice(const I2CDeviceParams &p)
63 : SimObject(p), _addr(p.i2c_addr)
64 { }
65
66 virtual ~I2CDevice() { }
67
75 virtual uint8_t read() = 0;
76
84 virtual void write(uint8_t msg) = 0;
85
91 virtual void i2cStart() = 0;
92
93 uint8_t i2cAddr() const { return _addr; }
94
95};
96
97} // namespace gem5
98
99#endif // __DEV_I2C_DEVICE__
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
virtual uint8_t read()=0
Return the next message that the device expects to send.
uint8_t i2cAddr() const
Definition device.hh:93
virtual ~I2CDevice()
Definition device.hh:66
virtual void i2cStart()=0
Perform any initialization necessary for the device when it received a start signal from the bus mast...
uint8_t _addr
Definition device.hh:58
virtual void write(uint8_t msg)=0
Perform any actions triggered by an i2c write (save msg in a register, perform an interrupt,...
I2CDevice(const I2CDeviceParams &p)
Definition device.hh:62
Abstract superclass for simulation objects.
Bitfield< 0 > p
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36

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