gem5  v22.1.0.0
dramsim2_wrapper.hh
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37 
43 #ifndef __MEM_DRAMSIM2_WRAPPER_HH__
44 #define __MEM_DRAMSIM2_WRAPPER_HH__
45 
46 #include <string>
47 
48 #include "DRAMSim2/Callback.h"
49 
53 namespace DRAMSim {
54 
55 class MultiChannelMemorySystem;
56 
57 }
58 
59 namespace gem5
60 {
61 
62 namespace memory
63 {
64 
74 {
75 
76  private:
77 
78  DRAMSim::MultiChannelMemorySystem* dramsim;
79 
80  double _clockPeriod;
81 
82  unsigned int _queueSize;
83 
84  unsigned int _burstSize;
85 
86  template <typename T>
87  T extractConfig(const std::string& field_name,
88  const std::string& file_name) const;
89 
90  public:
91 
103  DRAMSim2Wrapper(const std::string& config_file,
104  const std::string& system_file,
105  const std::string& working_dir,
106  const std::string& trace_file,
107  unsigned int memory_size_mb,
108  bool enable_debug);
110 
114  void printStats();
115 
122  void setCallbacks(DRAMSim::TransactionCompleteCB* read_callback,
123  DRAMSim::TransactionCompleteCB* write_callback);
124 
130  bool canAccept() const;
131 
137  void enqueue(bool is_write, uint64_t addr);
138 
145  double clockPeriod() const;
146 
152  unsigned int queueSize() const;
153 
159  unsigned int burstSize() const;
160 
164  void tick();
165 };
166 
167 } // namespace memory
168 } // namespace gem5
169 
170 #endif //__MEM_DRAMSIM2_WRAPPER_HH__
Wrapper class to avoid having DRAMSim2 names like ClockDomain etc clashing with the normal gem5 world...
void enqueue(bool is_write, uint64_t addr)
Enqueue a packet.
void printStats()
Print the stats gathered in DRAMsim2.
double clockPeriod() const
Get the internal clock period used by DRAMSim2, specified in ns.
unsigned int queueSize() const
Get the transaction queue size used by DRAMSim2.
unsigned int burstSize() const
Get the burst size in bytes used by DRAMSim2.
DRAMSim2Wrapper(const std::string &config_file, const std::string &system_file, const std::string &working_dir, const std::string &trace_file, unsigned int memory_size_mb, bool enable_debug)
Create an instance of the DRAMSim2 multi-channel memory controller using a specific config and system...
bool canAccept() const
Determine if the controller can accept a new packet or not.
T extractConfig(const std::string &field_name, const std::string &file_name) const
void setCallbacks(DRAMSim::TransactionCompleteCB *read_callback, DRAMSim::TransactionCompleteCB *write_callback)
Set the callbacks to use for read and write completion.
void tick()
Progress the memory controller one cycle.
DRAMSim::MultiChannelMemorySystem * dramsim
Forward declaration to avoid includes.
Bitfield< 3 > addr
Definition: types.hh:84
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: mem.h:38

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