gem5  v22.1.0.0
elastic_trace.hh
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37 
46 #ifndef __CPU_O3_PROBE_ELASTIC_TRACE_HH__
47 #define __CPU_O3_PROBE_ELASTIC_TRACE_HH__
48 
49 #include <set>
50 #include <unordered_map>
51 #include <utility>
52 
53 #include "base/statistics.hh"
54 #include "cpu/o3/dyn_inst_ptr.hh"
55 #include "cpu/reg_class.hh"
56 #include "mem/request.hh"
57 #include "params/ElasticTrace.hh"
58 #include "proto/inst_dep_record.pb.h"
59 #include "proto/packet.pb.h"
60 #include "proto/protoio.hh"
61 #include "sim/eventq.hh"
62 #include "sim/probe/probe.hh"
63 
64 namespace gem5
65 {
66 
67 namespace o3
68 {
69 
70 class CPU;
71 
94 {
95 
96  public:
98 
100  typedef ProtoMessage::InstDepRecord::RecordType RecordType;
101  typedef ProtoMessage::InstDepRecord Record;
102 
104  ElasticTrace(const ElasticTraceParams &params);
105 
110  void regProbeListeners();
111 
113  void regEtraceListeners();
114 
119  void flushTraces();
120 
128  void fetchReqTrace(const RequestPtr &req);
129 
136  void recordExecTick(const DynInstConstPtr& dyn_inst);
137 
145  void recordToCommTick(const DynInstConstPtr& dyn_inst);
146 
156  void updateRegDep(const DynInstConstPtr& dyn_inst);
157 
165  void removeRegDepMapEntry(const SeqNumRegPair &inst_reg_pair);
166 
173  void addSquashedInst(const DynInstConstPtr& head_inst);
174 
180  void addCommittedInst(const DynInstConstPtr& head_inst);
181 
184 
185  private:
191  bool firstWin;
192 
198  {
214  std::set<InstSeqNum> physRegDepSet;
219  : executeTick(MaxTick),
221  { }
222  };
223 
231  std::unordered_map<InstSeqNum, InstExecInfo*> tempStore;
232 
238 
244  std::unordered_map<RegIndex, InstSeqNum> physRegDepMap;
245 
256  struct TraceInfo
257  {
262  /* Instruction sequence number. */
266  /* Tick when instruction was in execute stage. */
268  /* Tick when instruction was marked ready and sent to commit stage. */
270  /* Tick when instruction was committed. */
272  /* If instruction was committed, as against squashed. */
273  bool commit;
274  /* List of order dependencies. */
276  /* List of physical register RAW dependencies. */
282  int64_t compDelay;
283  /* Number of dependents. */
284  uint32_t numDepts;
285  /* The instruction PC for a load, store or non load/store. */
287  /* Request flags in case of a load/store instruction */
289  /* Request physical address in case of a load/store instruction */
291  /* Request virtual address in case of a load/store instruction */
293  /* Request size in case of a load/store instruction */
294  unsigned size;
297  : type(Record::INVALID)
298  { }
300  bool isLoad() const { return (type == Record::LOAD); }
302  bool isStore() const { return (type == Record::STORE); }
304  bool isComp() const { return (type == Record::COMP); }
306  const std::string& typeToStr() const;
314  Tick getExecuteTick() const;
315  };
316 
330 
335  std::unordered_map<InstSeqNum, TraceInfo*> traceInfoMap;
336 
339 
341  typedef typename std::reverse_iterator<depTraceItr> depTraceRevItr;
342 
349  uint32_t depWindowSize;
350 
353 
356 
359 
367 
369  const bool traceVirtAddr;
370 
373 
384  void addDepTraceRecord(const DynInstConstPtr& head_inst,
385  InstExecInfo* exec_info_ptr, bool commit);
386 
393  void clearTempStoreUntil(const DynInstConstPtr& head_inst);
394 
405  void compDelayRob(TraceInfo* past_record, TraceInfo* new_record);
406 
418  void compDelayPhysRegDep(TraceInfo* past_record, TraceInfo* new_record);
419 
427  void writeDepTrace(uint32_t num_to_write);
428 
441  void updateCommitOrderDep(TraceInfo* new_record, bool find_load_not_store);
442 
454  void updateIssueOrderDep(TraceInfo* new_record);
455 
465  void assignRobDep(TraceInfo* past_record, TraceInfo* new_record);
466 
475  bool hasStoreCommitted(TraceInfo* past_record, Tick execute_tick) const;
476 
487  bool hasLoadCompleted(TraceInfo* past_record, Tick execute_tick) const;
488 
497  bool hasLoadBeenSent(TraceInfo* past_record, Tick execute_tick) const;
498 
509  bool hasCompCompleted(TraceInfo* past_record, Tick execute_tick) const;
510 
512  {
514 
517 
523 
529 
535 
541 
544 
547 
553 
559  } stats;
560 
561 };
562 
563 } // namespace o3
564 } // namespace gem5
565 
566 #endif//__CPU_O3_PROBE_ELASTIC_TRACE_HH__
A ProtoOutputStream wraps a coded stream, potentially with compression, based on looking at the file ...
Definition: protoio.hh:91
This class is a minimal wrapper around SimObject.
Definition: probe.hh:108
If you want a reference counting pointer to a mutable object, create it like this:
Definition: refcnt.hh:127
uint64_t FlagsType
Definition: request.hh:100
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:94
The elastic trace is a type of probe listener and listens to probe points in multiple stages of the O...
void compDelayRob(TraceInfo *past_record, TraceInfo *new_record)
Calculate the computational delay between an instruction and a subsequent instruction that has an ROB...
const bool traceVirtAddr
Whether to trace virtual addresses for memory requests.
bool hasCompCompleted(TraceInfo *past_record, Tick execute_tick) const
Check if past record is a comp node that completed earlier than the execute tick.
void updateIssueOrderDep(TraceInfo *new_record)
Reverse iterate through the graph, search for an issue order dependency for a new node and update the...
bool allProbesReg
Whther the elastic trace listener has been registered for all probes.
std::vector< TraceInfo * >::iterator depTraceItr
Typedef of iterator to the instruction dependency trace.
void addCommittedInst(const DynInstConstPtr &head_inst)
Add an instruction that is at the head of the ROB and is committed.
bool hasLoadCompleted(TraceInfo *past_record, Tick execute_tick) const
Check if past record is a load that completed earlier than the execute tick.
ProtoOutputStream * dataTraceStream
Protobuf output stream for data dependency trace.
void recordToCommTick(const DynInstConstPtr &dyn_inst)
Populate the timestamp field in an InstExecInfo object for an instruction in flight when it is execut...
std::unordered_map< InstSeqNum, InstExecInfo * > tempStore
Temporary store of InstExecInfo objects.
void writeDepTrace(uint32_t num_to_write)
Write out given number of records to the trace starting with the first record in depTrace and iterati...
std::vector< TraceInfo * > depTrace
The instruction dependency trace containing TraceInfo objects.
void clearTempStoreUntil(const DynInstConstPtr &head_inst)
Clear entries in the temporary store of execution info objects to free allocated memory until the pre...
uint32_t depWindowSize
The maximum distance for a dependency and is set by a top level level parameter.
void assignRobDep(TraceInfo *past_record, TraceInfo *new_record)
The new_record has an order dependency on a past_record, thus update the new record's Rob dependency ...
ElasticTrace(const ElasticTraceParams &params)
Constructor.
CPU * cpu
Pointer to the O3CPU that is this listener's parent a.k.a.
bool firstWin
Used for checking the first window for processing and writing of dependency trace.
std::reverse_iterator< depTraceItr > depTraceRevItr
Typedef of the reverse iterator to the instruction dependency trace.
void addDepTraceRecord(const DynInstConstPtr &head_inst, InstExecInfo *exec_info_ptr, bool commit)
Add a record to the dependency trace depTrace which is a sequential container.
void compDelayPhysRegDep(TraceInfo *past_record, TraceInfo *new_record)
Calculate the computational delay between an instruction and a subsequent instruction that has a Phys...
void removeRegDepMapEntry(const SeqNumRegPair &inst_reg_pair)
When an instruction gets squashed the destination register mapped to it is freed up in the rename sta...
EventFunctionWrapper regEtraceListenersEvent
Event to trigger registering this listener for all probe points.
void regEtraceListeners()
Register all listeners.
std::pair< InstSeqNum, RegIndex > SeqNumRegPair
void recordExecTick(const DynInstConstPtr &dyn_inst)
Populate the execute timestamp field in an InstExecInfo object for an instruction in flight.
ProtoMessage::InstDepRecord::RecordType RecordType
Trace record types corresponding to instruction node types.
void regProbeListeners()
Register the probe listeners that is the methods called on a probe point notify() call.
std::unordered_map< RegIndex, InstSeqNum > physRegDepMap
Map for recording the producer of a physical register to check Read After Write dependencies.
std::unordered_map< InstSeqNum, TraceInfo * > traceInfoMap
Map where the instruction sequence number is mapped to the pointer to the TraceInfo object.
void addSquashedInst(const DynInstConstPtr &head_inst)
Add an instruction that is at the head of the ROB and is squashed only if it is a load and a request ...
bool hasLoadBeenSent(TraceInfo *past_record, Tick execute_tick) const
Check if past record is a load sent earlier than the execute tick.
void fetchReqTrace(const RequestPtr &req)
Take the fields of the request class object that are relevant to create an instruction fetch request.
InstSeqNum lastClearedSeqNum
The last cleared instruction sequence number used to free up the memory allocated in the temporary st...
gem5::o3::ElasticTrace::ElasticTraceStats stats
ProtoOutputStream * instTraceStream
Protobuf output stream for instruction fetch trace.
void updateRegDep(const DynInstConstPtr &dyn_inst)
Record a Read After Write physical register dependency if there has been a write to the source regist...
void flushTraces()
Process any outstanding trace records, flush them out to the protobuf output streams and delete the s...
ProtoMessage::InstDepRecord Record
void updateCommitOrderDep(TraceInfo *new_record, bool find_load_not_store)
Reverse iterate through the graph, search for a store-after-store or store-after-load dependency and ...
const InstSeqNum startTraceInst
Number of instructions after which to enable tracing.
bool hasStoreCommitted(TraceInfo *past_record, Tick execute_tick) const
Check if past record is a store sent earlier than the execute tick.
Statistics container.
Definition: group.hh:94
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1931
STL pair class.
Definition: stl.hh:58
STL vector class.
Definition: stl.hh:37
Tick executeTick
Timestamp when instruction was first processed by execute stage.
Tick toCommitTick
Timestamp when instruction execution is completed in execute stage and instruction is marked as ready...
std::set< InstSeqNum > physRegDepSet
Set of instruction sequence numbers that this instruction depends on due to Read After Write data dep...
const std::string & typeToStr() const
Return string specifying the type of the node.
bool isLoad() const
Is the record a load.
std::list< InstSeqNum > robDepList
std::list< InstSeqNum > physRegDepList
int64_t compDelay
Computational delay after the last dependent inst.
TraceInfo()
Default Constructor.
bool isComp() const
Is the record a fetch triggering an Icache request.
RecordType type
The type of trace record for the instruction node.
bool isStore() const
Is the record a store.
const Params & params() const
Definition: sim_object.hh:176
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
uint64_t Tick
Tick count type.
Definition: types.hh:58
const Tick MaxTick
Definition: types.hh:60
uint64_t InstSeqNum
Definition: inst_seq.hh:40
Declaration of a wrapper for protobuf output streams and input streams.
Declaration of a request, the overall memory request consisting of the parts of the request that are ...
Declaration of Statistics objects.
statistics::Scalar maxNumDependents
Maximum number of dependents on any instruction.
statistics::Scalar maxTempStoreSize
Maximum size of the temporary store mostly useful as a check that it is not growing.
statistics::Scalar numIssueOrderDepLoads
Number of load insts that got assigned an issue order dependency because they were dependency-free.
statistics::Scalar numIssueOrderDepStores
Number of store insts that got assigned an issue order dependency because they were dependency-free.
ElasticTraceStats(statistics::Group *parent)
statistics::Scalar numRegDep
Number of register dependencies recorded during tracing.
statistics::Scalar numFilteredNodes
Number of filtered nodes.
statistics::Scalar maxPhysRegDepMapSize
Maximum size of the map that holds the last writer to a physical register.
statistics::Scalar numOrderDepStores
Number of stores that got assigned a commit order dependency on a past load/store.
statistics::Scalar numIssueOrderDepOther
Number of non load/store insts that got assigned an issue order dependency because they were dependen...
Tick getExecuteTick() const
Get the execute tick of the instruction.

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