gem5
v24.0.0.0
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gpu-compute
gpu_exec_context.cc
Go to the documentation of this file.
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/*
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* Copyright (c) 2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "
gpu-compute/gpu_exec_context.hh
"
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#include "
gpu-compute/wavefront.hh
"
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namespace
gem5
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{
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GPUExecContext::GPUExecContext
(
ComputeUnit
*_cu,
Wavefront
*_wf)
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: cu(_cu), wf(_wf), gpuISA(_wf ? &_wf->gpuISA() : nullptr)
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{
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}
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ComputeUnit
*
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GPUExecContext::computeUnit
()
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{
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return
cu
;
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}
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Wavefront
*
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GPUExecContext::wavefront
()
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{
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return
wf
;
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}
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RegVal
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GPUExecContext::readMiscReg
(
int
opIdx)
const
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{
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assert(
gpuISA
);
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return
gpuISA
->readMiscReg(opIdx);
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}
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void
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GPUExecContext::writeMiscReg
(
int
opIdx,
RegVal
val
)
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{
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assert(
gpuISA
);
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gpuISA
->writeMiscReg(opIdx,
val
);
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}
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}
// namespace gem5
gem5::ComputeUnit
Definition
compute_unit.hh:203
gem5::GPUExecContext::cu
ComputeUnit * cu
Definition
gpu_exec_context.hh:62
gem5::GPUExecContext::writeMiscReg
void writeMiscReg(int opIdx, RegVal operandVal)
Definition
gpu_exec_context.cc:63
gem5::GPUExecContext::gpuISA
TheGpuISA::GPUISA * gpuISA
Definition
gpu_exec_context.hh:64
gem5::GPUExecContext::computeUnit
ComputeUnit * computeUnit()
Definition
gpu_exec_context.cc:44
gem5::GPUExecContext::wf
Wavefront * wf
Definition
gpu_exec_context.hh:63
gem5::GPUExecContext::readMiscReg
RegVal readMiscReg(int opIdx) const
Definition
gpu_exec_context.cc:56
gem5::GPUExecContext::wavefront
Wavefront * wavefront()
Definition
gpu_exec_context.cc:50
gem5::GPUExecContext::GPUExecContext
GPUExecContext(ComputeUnit *_cu, Wavefront *_wf)
Definition
gpu_exec_context.cc:38
gem5::Wavefront
Definition
wavefront.hh:61
gpu_exec_context.hh
gem5::X86ISA::val
Bitfield< 63 > val
Definition
misc.hh:804
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition
binary32.hh:36
gem5::RegVal
uint64_t RegVal
Definition
types.hh:173
wavefront.hh
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