gem5  v22.0.0.1
gpu_exec_context.cc
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31 
33 #include "gpu-compute/wavefront.hh"
34 
35 namespace gem5
36 {
37 
39  : cu(_cu), wf(_wf), gpuISA(_wf ? &_wf->gpuISA() : nullptr)
40 {
41 }
42 
45 {
46  return cu;
47 }
48 
49 Wavefront*
51 {
52  return wf;
53 }
54 
55 RegVal
57 {
58  assert(gpuISA);
59  return gpuISA->readMiscReg(opIdx);
60 }
61 
62 void
64 {
65  assert(gpuISA);
66  gpuISA->writeMiscReg(opIdx, val);
67 }
68 
69 } // namespace gem5
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::GPUExecContext::writeMiscReg
void writeMiscReg(int opIdx, RegVal operandVal)
Definition: gpu_exec_context.cc:63
gem5::Wavefront
Definition: wavefront.hh:60
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::GPUExecContext::wf
Wavefront * wf
Definition: gpu_exec_context.hh:63
gem5::GPUExecContext::gpuISA
TheGpuISA::GPUISA * gpuISA
Definition: gpu_exec_context.hh:64
wavefront.hh
gem5::GPUExecContext::computeUnit
ComputeUnit * computeUnit()
Definition: gpu_exec_context.cc:44
gem5::ComputeUnit
Definition: compute_unit.hh:201
gem5::GPUExecContext::GPUExecContext
GPUExecContext(ComputeUnit *_cu, Wavefront *_wf)
Definition: gpu_exec_context.cc:38
gem5::GPUExecContext::readMiscReg
RegVal readMiscReg(int opIdx) const
Definition: gpu_exec_context.cc:56
gem5::GPUExecContext::wavefront
Wavefront * wavefront()
Definition: gpu_exec_context.cc:50
gpu_exec_context.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::GPUExecContext::cu
ComputeUnit * cu
Definition: gpu_exec_context.hh:62

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