gem5  v22.1.0.0
gpu_exec_context.cc
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31 
33 #include "gpu-compute/wavefront.hh"
34 
35 namespace gem5
36 {
37 
39  : cu(_cu), wf(_wf), gpuISA(_wf ? &_wf->gpuISA() : nullptr)
40 {
41 }
42 
45 {
46  return cu;
47 }
48 
49 Wavefront*
51 {
52  return wf;
53 }
54 
55 RegVal
57 {
58  assert(gpuISA);
59  return gpuISA->readMiscReg(opIdx);
60 }
61 
62 void
64 {
65  assert(gpuISA);
66  gpuISA->writeMiscReg(opIdx, val);
67 }
68 
69 } // namespace gem5
void writeMiscReg(int opIdx, RegVal operandVal)
TheGpuISA::GPUISA * gpuISA
ComputeUnit * computeUnit()
RegVal readMiscReg(int opIdx) const
GPUExecContext(ComputeUnit *_cu, Wavefront *_wf)
Bitfield< 63 > val
Definition: misc.hh:776
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint64_t RegVal
Definition: types.hh:173

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