gem5  v21.1.0.2
compute_unit.hh
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33 
34 #ifndef __COMPUTE_UNIT_HH__
35 #define __COMPUTE_UNIT_HH__
36 
37 #include <deque>
38 #include <map>
39 #include <unordered_set>
40 #include <vector>
41 
42 #include "base/callback.hh"
43 #include "base/compiler.hh"
44 #include "base/statistics.hh"
45 #include "base/stats/group.hh"
46 #include "base/types.hh"
47 #include "config/the_gpu_isa.hh"
48 #include "enums/PrefetchType.hh"
49 #include "gpu-compute/comm.hh"
59 #include "mem/port.hh"
60 #include "mem/token_port.hh"
61 #include "sim/clocked_object.hh"
62 
63 namespace gem5
64 {
65 
66 class HSAQueueEntry;
67 class LdsChunk;
68 class ScalarRegisterFile;
69 class Shader;
70 class VectorRegisterFile;
71 
72 struct ComputeUnitParams;
73 
75 {
76  OLDEST = 0,
78 };
79 
81 {
86 };
87 
92 class WFBarrier
93 {
94  public:
96  {
97  }
98 
99  static const int InvalidID = -1;
100 
101  int
102  numAtBarrier() const
103  {
104  return _numAtBarrier;
105  }
106 
110  int
112  {
113  return _maxBarrierCnt - _numAtBarrier;
114  }
115 
116  int
118  {
119  return _maxBarrierCnt;
120  }
121 
126  void
127  setMaxBarrierCnt(int max_barrier_cnt)
128  {
129  _maxBarrierCnt = max_barrier_cnt;
130  }
131 
135  void
137  {
138  assert(_numAtBarrier < _maxBarrierCnt);
139  ++_numAtBarrier;
140  }
141 
147  bool
148  allAtBarrier() const
149  {
150  return _numAtBarrier == _maxBarrierCnt;
151  }
152 
157  void
159  {
160  assert(_maxBarrierCnt > 0);
161  --_maxBarrierCnt;
162  }
163 
168  void
170  {
171  _numAtBarrier = 0;
172  _maxBarrierCnt = 0;
173  }
174 
179  void
181  {
182  _numAtBarrier = 0;
183  }
184 
185  private:
192 
201 };
202 
204 {
205  public:
206 
207 
208  // Execution resources
209  //
210  // The ordering of units is:
211  // Vector ALUs
212  // Scalar ALUs
213  // GM Pipe
214  // LM Pipe
215  // Scalar Mem Pipe
216  //
217  // Note: the ordering of units is important and the code assumes the
218  // above ordering. However, there may be more than one resource of
219  // each type (e.g., 4 VALUs or 2 SALUs)
220 
222  // Resource control for global memory to VRF data/address bus
224  // Resource control for Vector Register File->Global Memory pipe buses
226  // Resource control for Vector Global Memory execution unit
228 
230  // Resource control for local memory to VRF data/address bus
232  // Resource control for Vector Register File->Local Memory pipe buses
234  // Resource control for Vector Shared/Local Memory execution unit
236 
238  // Resource control for scalar memory to SRF data/address bus
240  // Resource control for Scalar Register File->Scalar Memory pipe buses
242  // Resource control for Scalar Memory execution unit
244 
245  // vector ALU execution resources
248 
249  // scalar ALU execution resources
252 
253  // Return total number of execution units on this CU
254  int numExeUnits() const;
255  // index into readyList of the first memory unit
256  int firstMemUnit() const;
257  // index into readyList of the last memory unit
258  int lastMemUnit() const;
259  // index into scalarALUs vector of SALU used by the wavefront
260  int mapWaveToScalarAlu(Wavefront *w) const;
261  // index into readyList of SALU used by wavefront
263  // index into readyList of Global Memory unit used by wavefront
264  int mapWaveToGlobalMem(Wavefront *w) const;
265  // index into readyList of Local Memory unit used by wavefront
266  int mapWaveToLocalMem(Wavefront *w) const;
267  // index into readyList of Scalar Memory unit used by wavefront
268  int mapWaveToScalarMem(Wavefront *w) const;
269 
270  int vrfToCoalescerBusWidth; // VRF->Coalescer data bus width in bytes
271  int coalescerToVrfBusWidth; // Coalescer->VRF data bus width in bytes
272  int numCyclesPerStoreTransfer; // number of cycles per vector store
273  int numCyclesPerLoadTransfer; // number of cycles per vector load
274 
275  // track presence of dynamic instructions in the Schedule pipeline
276  // stage. This is used to check the readiness of the oldest,
277  // non-dispatched instruction of every WF in the Scoreboard stage.
278  std::unordered_set<uint64_t> pipeMap;
279 
281 
289 
291 
292  typedef ComputeUnitParams Params;
294  int cu_id;
295 
296  // array of vector register files, one per SIMD
298  // array of scalar register files, one per SIMD
300 
301  // Width per VALU/SIMD unit: number of work items that can be executed
302  // on the vector ALU simultaneously in a SIMD unit
304  // number of pipe stages for bypassing data to next dependent single
305  // precision vector instruction inside the vector ALU pipeline
307  // number of pipe stages for bypassing data to next dependent double
308  // precision vector instruction inside the vector ALU pipeline
310  // number of pipe stages for scalar ALU
312  // number of pipe stages for operand collection & distribution network
314  // number of cycles per instruction issue period
316 
317  // VRF to GM Bus latency
319  // SRF to Scalar Mem Bus latency
321  // VRF to LM Bus latency
323 
324  // tracks the last cycle a vector instruction was executed on a SIMD
326 
327  // tracks the number of dyn inst executed per SIMD
329 
330  // true if we allow a separate TLB per lane
332  // if 0, TLB prefetching is off.
334  // if fixed-stride prefetching, this is the stride.
336 
340  enums::PrefetchType prefetchType;
342 
344  // Idle CU timeout in ticks
346  int idleWfs;
349 
350  /*
351  * for Counting page accesses
352  */
354 
356 
359 
367 
368  // number of currently reserved vector registers per SIMD unit
370  // number of currently reserved scalar registers per SIMD unit
372  // number of vector registers per SIMD unit
374  // number of available scalar registers per SIMD unit
376 
377  // this hash map will keep track of page divergence
378  // per memory instruction per wavefront. The hash map
379  // is cleared in GPUDynInst::updateStats() in gpu_dyn_inst.cc.
380  std::map<Addr, int> pagesTouched;
381 
382  void insertInPipeMap(Wavefront *w);
384 
385  ComputeUnit(const Params &p);
386  ~ComputeUnit();
387 
388  // Timing Functions
389  int oprNetPipeLength() const { return operandNetworkLength; }
390  int simdUnitWidth() const { return simdWidth; }
391  int spBypassLength() const { return spBypassPipeLength; }
392  int dpBypassLength() const { return dpBypassPipeLength; }
393  int scalarPipeLength() const { return scalarPipeStages; }
395  int loadBusLength() const { return numCyclesPerLoadTransfer; }
396  int wfSize() const { return wavefrontSize; }
397 
398  void exec();
399  void initiateFetch(Wavefront *wavefront);
400  void fetch(PacketPtr pkt, Wavefront *wavefront);
402 
403  void startWavefront(Wavefront *w, int waveId, LdsChunk *ldsChunk,
404  HSAQueueEntry *task, int bar_id,
405  bool fetchContext=false);
406 
407  void doInvalidate(RequestPtr req, int kernId);
408  void doFlush(GPUDynInstPtr gpuDynInst);
409 
410  void dispWorkgroup(HSAQueueEntry *task, int num_wfs_in_wg);
411  bool hasDispResources(HSAQueueEntry *task, int &num_wfs_in_wg);
412 
413  int cacheLineSize() const { return _cacheLineSize; }
414  int getCacheLineBits() const { return cacheLineBits; }
415 
416  void resetRegisterPool();
417 
418  private:
419  WFBarrier&
420  barrierSlot(int bar_id)
421  {
422  assert(bar_id > WFBarrier::InvalidID);
423  return wfBarrierSlots.at(bar_id);
424  }
425 
426  int
428  {
429  assert(freeBarrierIds.size());
430  auto free_bar_id = freeBarrierIds.begin();
431  int bar_id = *free_bar_id;
432  freeBarrierIds.erase(free_bar_id);
433  return bar_id;
434  }
435 
436  public:
437  int numYetToReachBarrier(int bar_id);
438  bool allAtBarrier(int bar_id);
439  void incNumAtBarrier(int bar_id);
440  int numAtBarrier(int bar_id);
441  int maxBarrierCnt(int bar_id);
442  void resetBarrier(int bar_id);
443  void decMaxBarrierCnt(int bar_id);
444  void releaseBarrier(int bar_id);
445  void releaseWFsFromBarrier(int bar_id);
446  int numBarrierSlots() const { return _numBarrierSlots; }
447 
448  template<typename c0, typename c1>
449  void doSmReturn(GPUDynInstPtr gpuDynInst);
450 
451  virtual void init() override;
452  void sendRequest(GPUDynInstPtr gpuDynInst, PortID index, PacketPtr pkt);
453  void sendScalarRequest(GPUDynInstPtr gpuDynInst, PacketPtr pkt);
454  void injectGlobalMemFence(GPUDynInstPtr gpuDynInst,
455  bool kernelMemSync,
456  RequestPtr req=nullptr);
457  void handleMemPacket(PacketPtr pkt, int memport_index);
458  bool processTimingPacket(PacketPtr pkt);
459  void processFetchReturn(PacketPtr pkt);
461 
463 
464  bool isDone() const;
465  bool isVectorAluIdle(uint32_t simdId) const;
466 
467  protected:
469 
471 
472  public:
473  LdsState &
474  getLds() const
475  {
476  return lds;
477  }
478 
479  int32_t
480  getRefCounter(const uint32_t dispatchId, const uint32_t wgId) const;
481 
482  GEM5_NO_DISCARD bool sendToLds(GPUDynInstPtr gpuDynInst);
483 
484  typedef std::unordered_map<Addr, std::pair<int, int>> pageDataStruct;
486 
487  void exitCallback();
488 
490  {
491  public:
492  GMTokenPort(const std::string& name, SimObject *owner,
493  PortID id = InvalidPortID)
495  { }
497 
498  protected:
499  bool recvTimingResp(PacketPtr) { return false; }
500  void recvReqRetry() { }
501  };
502 
503  // Manager for the number of tokens available to this compute unit to
504  // send global memory request packets to the coalescer this is only used
505  // between global memory pipe and TCP coalescer.
508 
510  class DataPort : public RequestPort
511  {
512  public:
513  DataPort(const std::string &_name, ComputeUnit *_cu, PortID id)
514  : RequestPort(_name, _cu, id), computeUnit(_cu) { }
515 
517 
519  {
523 
524  SenderState(GPUDynInstPtr gpuDynInst, PortID _port_index,
525  Packet::SenderState *sender_state=nullptr)
526  : _gpuDynInst(gpuDynInst),
527  port_index(_port_index),
528  saved(sender_state) { }
529  };
530 
531  void processMemReqEvent(PacketPtr pkt);
533 
534  void processMemRespEvent(PacketPtr pkt);
536 
538 
539  protected:
541 
542  virtual bool recvTimingResp(PacketPtr pkt);
543  virtual Tick recvAtomic(PacketPtr pkt) { return 0; }
544  virtual void recvFunctional(PacketPtr pkt) { }
545  virtual void recvRangeChange() { }
546  virtual void recvReqRetry();
547 
548  virtual void
550  {
551  resp.clear();
552  snoop = true;
553  }
554 
555  };
556 
557  // Scalar data cache access port
559  {
560  public:
561  ScalarDataPort(const std::string &_name, ComputeUnit *_cu)
562  : RequestPort(_name, _cu), computeUnit(_cu)
563  {
564  }
565 
566  bool recvTimingResp(PacketPtr pkt) override;
567  void recvReqRetry() override;
568 
570  {
572  Packet::SenderState *sender_state=nullptr)
573  : _gpuDynInst(gpuDynInst), saved(sender_state)
574  {
575  }
576 
579  };
580 
581  class MemReqEvent : public Event
582  {
583  private:
586 
587  public:
588  MemReqEvent(ScalarDataPort &_scalar_data_port, PacketPtr _pkt)
589  : Event(), scalarDataPort(_scalar_data_port), pkt(_pkt)
590  {
592  }
593 
594  void process();
595  const char *description() const;
596  };
597 
599 
600  private:
602  };
603 
604  // Instruction cache access port
605  class SQCPort : public RequestPort
606  {
607  public:
608  SQCPort(const std::string &_name, ComputeUnit *_cu)
609  : RequestPort(_name, _cu), computeUnit(_cu) { }
610 
612 
614  {
617  // kernel id to be used in handling I-Cache invalidate response
618  int kernId;
619 
621  *sender_state=nullptr, int _kernId=-1)
622  : wavefront(_wavefront), saved(sender_state),
623  kernId(_kernId){ }
624  };
625 
627 
628  protected:
630 
631  virtual bool recvTimingResp(PacketPtr pkt);
632  virtual Tick recvAtomic(PacketPtr pkt) { return 0; }
633  virtual void recvFunctional(PacketPtr pkt) { }
634  virtual void recvRangeChange() { }
635  virtual void recvReqRetry();
636 
637  virtual void
639  {
640  resp.clear();
641  snoop = true;
642  }
643  };
644 
646  class DTLBPort : public RequestPort
647  {
648  public:
649  DTLBPort(const std::string &_name, ComputeUnit *_cu, PortID id)
650  : RequestPort(_name, _cu, id), computeUnit(_cu),
651  stalled(false)
652  { }
653 
654  bool isStalled() { return stalled; }
655  void stallPort() { stalled = true; }
656  void unstallPort() { stalled = false; }
657 
663 
668  {
669  // the memInst that this is associated with
671 
672  // the lane in the memInst this is associated with, so we send
673  // the memory request down the right port
675 
676  // constructor used for packets involved in timing accesses
677  SenderState(GPUDynInstPtr gpuDynInst, PortID port_index)
678  : _gpuDynInst(gpuDynInst), portIndex(port_index) { }
679 
680  };
681 
682  protected:
684  bool stalled;
685 
686  virtual bool recvTimingResp(PacketPtr pkt);
687  virtual Tick recvAtomic(PacketPtr pkt) { return 0; }
688  virtual void recvFunctional(PacketPtr pkt) { }
689  virtual void recvRangeChange() { }
690  virtual void recvReqRetry();
691  };
692 
694  {
695  public:
696  ScalarDTLBPort(const std::string &_name, ComputeUnit *_cu)
697  : RequestPort(_name, _cu), computeUnit(_cu), stalled(false)
698  {
699  }
700 
702  {
703  SenderState(GPUDynInstPtr gpuDynInst) : _gpuDynInst(gpuDynInst) { }
705  };
706 
707  bool recvTimingResp(PacketPtr pkt) override;
708  void recvReqRetry() override { assert(false); }
709 
710  bool isStalled() const { return stalled; }
711  void stallPort() { stalled = true; }
712  void unstallPort() { stalled = false; }
713 
715 
716  private:
718  bool stalled;
719  };
720 
721  class ITLBPort : public RequestPort
722  {
723  public:
724  ITLBPort(const std::string &_name, ComputeUnit *_cu)
725  : RequestPort(_name, _cu), computeUnit(_cu), stalled(false) { }
726 
727 
728  bool isStalled() { return stalled; }
729  void stallPort() { stalled = true; }
730  void unstallPort() { stalled = false; }
731 
737 
742  {
743  // The wavefront associated with this request
745 
746  SenderState(Wavefront *_wavefront) : wavefront(_wavefront) { }
747  };
748 
749  protected:
751  bool stalled;
752 
753  virtual bool recvTimingResp(PacketPtr pkt);
754  virtual Tick recvAtomic(PacketPtr pkt) { return 0; }
755  virtual void recvFunctional(PacketPtr pkt) { }
756  virtual void recvRangeChange() { }
757  virtual void recvReqRetry();
758  };
759 
763  class LDSPort : public RequestPort
764  {
765  public:
766  LDSPort(const std::string &_name, ComputeUnit *_cu)
767  : RequestPort(_name, _cu), computeUnit(_cu)
768  {
769  }
770 
771  bool isStalled() const { return stalled; }
772  void stallPort() { stalled = true; }
773  void unstallPort() { stalled = false; }
774 
779  std::queue<PacketPtr> retries;
780 
786  {
787  protected:
788  // The actual read/write/atomic request that goes with this command
790 
791  public:
793  _gpuDynInst(gpuDynInst)
794  {
795  }
796 
798  getMemInst() const
799  {
800  return _gpuDynInst;
801  }
802  };
803 
804  virtual bool
806 
807  protected:
808 
809  bool stalled = false;
810 
812 
813  virtual bool
815 
816  virtual Tick
817  recvAtomic(PacketPtr pkt) { return 0; }
818 
819  virtual void
821  {
822  }
823 
824  virtual void
826  {
827  }
828 
829  virtual void
830  recvReqRetry();
831  };
832 
837 
838  TokenManager *
840  {
841  return memPortTokens;
842  }
843 
848  // port to the TLB hierarchy (i.e., the L1 TLB)
850  // port to the scalar data cache
852  // port to the scalar data TLB
854  // port to the SQC (i.e. the I-cache)
856  // port to the SQC TLB (there's a separate TLB for each I-cache)
858 
859  Port &
860  getPort(const std::string &if_name, PortID idx) override
861  {
862  if (if_name == "memory_port" && idx < memPort.size()) {
863  return memPort[idx];
864  } else if (if_name == "translation_port" && idx < tlbPort.size()) {
865  return tlbPort[idx];
866  } else if (if_name == "scalar_port") {
867  return scalarDataPort;
868  } else if (if_name == "scalar_tlb_port") {
869  return scalarDTLBPort;
870  } else if (if_name == "sqc_port") {
871  return sqcPort;
872  } else if (if_name == "sqc_tlb_port") {
873  return sqcTLBPort;
874  } else if (if_name == "ldsPort") {
875  return ldsPort;
876  } else if (if_name == "gmTokenPort") {
877  return gmTokenPort;
878  } else {
879  return ClockedObject::getPort(if_name, idx);
880  }
881  }
882 
884 
885  private:
886  const int _cacheLineSize;
887  const int _numBarrierSlots;
891 
926 
934  std::unordered_set<int> freeBarrierIds;
935 
936  // hold the time of the arrival of the first cache block related to
937  // a particular GPUDynInst. This is used to calculate the difference
938  // between the first and last chace block arrival times.
939  std::unordered_map<GPUDynInstPtr, Tick> headTailMap;
940 
941  public:
942  void updateInstStats(GPUDynInstPtr gpuDynInst);
944 
946  {
947  ComputeUnitStats(statistics::Group *parent, int n_wf);
948 
971 
978 
979  // Cycles required to send register source (addr and data) from
980  // register files to memory pipeline, per SIMD.
984 
1006 
1008 
1009  // the following stats compute the avg. TLB accesslatency per
1010  // uncoalesced request (only for data)
1014  // hitsPerTLBLevel[x] are the hits in Level x TLB.
1015  // x = 0 is the page table.
1017 
1020 
1021  // over all memory instructions executed over all wavefronts
1022  // how many touched 0-4 pages, 4-8, ..., 60-64 pages
1024  // count of non-flat global memory vector instructions executed
1026  // count of flat global memory vector instructions executed
1029 
1032  // Number of instructions executed, i.e. if 64 (or 32 or 7) lanes are
1033  // active when the instruction is committed, this number is still
1034  // incremented by 1
1036  // Number of cycles among successive instruction executions across all
1037  // wavefronts of the same CU
1039  // number of individual vector operations executed
1041  // number of individual f16 vector operations executed
1043  // number of individual f32 vector operations executed
1045  // number of individual f64 vector operations executed
1047  // number of individual FMA 16,32,64 vector operations executed
1051  // number of individual MAC 16,32,64 vector operations executed
1055  // number of individual MAD 16,32,64 vector operations executed
1059  // total number of two op FP vector operations executed
1061  // Total cycles that something is running on the GPU
1063  statistics::Formula vpc; // vector ops per cycle
1064  statistics::Formula vpc_f16; // vector ops per cycle
1065  statistics::Formula vpc_f32; // vector ops per cycle
1066  statistics::Formula vpc_f64; // vector ops per cycle
1067  statistics::Formula ipc; // vector instructions per cycle
1071  // number of vector ALU instructions received
1073  // number of times a WG cannot start due to lack of free VGPRs in SIMDs
1075  // number of times a WG cannot start due to lack of free SGPRs in SIMDs
1081 
1082  // distrubtion in latency difference between first and last cache block
1083  // arrival ticks
1085 
1086  // Track the amount of interleaving between wavefronts on each SIMD.
1087  // This stat is sampled using instExecPerSimd to compute the number
1088  // of instructions that have been executed on a SIMD between a WF
1089  // executing two successive instructions.
1091  } stats;
1092 };
1093 
1094 } // namespace gem5
1095 
1096 #endif // __COMPUTE_UNIT_HH__
gem5::ComputeUnit::SQCPort::SenderState
Definition: compute_unit.hh:613
gem5::ComputeUnit::ComputeUnitStats::tlbRequests
statistics::Scalar tlbRequests
Definition: compute_unit.hh:1011
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1927
gem5::ComputeUnit::GMTokenPort::recvTimingResp
bool recvTimingResp(PacketPtr)
Receive a timing response from the peer.
Definition: compute_unit.hh:499
gem5::ComputeUnit::GMTokenPort::GMTokenPort
GMTokenPort(const std::string &name, SimObject *owner, PortID id=InvalidPortID)
Definition: compute_unit.hh:492
gem5::ComputeUnit::ComputeUnitStats::sALUInstsPerWF
statistics::Formula sALUInstsPerWF
Definition: compute_unit.hh:952
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::ComputeUnit::ComputeUnitStats::vALUUtilization
statistics::Formula vALUUtilization
Definition: compute_unit.hh:956
gem5::ComputeUnit::getAndIncSeqNum
InstSeqNum getAndIncSeqNum()
Definition: compute_unit.hh:883
gem5::ComputeUnit::ScalarDTLBPort
Definition: compute_unit.hh:693
gem5::SimObject::getPort
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Definition: sim_object.cc:126
hsa_queue_entry.hh
gem5::ComputeUnit::ScalarDataPort::SenderState::saved
Packet::SenderState * saved
Definition: compute_unit.hh:578
gem5::ComputeUnit::wfList
std::vector< std::vector< Wavefront * > > wfList
Definition: compute_unit.hh:293
gem5::ComputeUnit::ComputeUnit
ComputeUnit(const Params &p)
Definition: compute_unit.cc:66
gem5::ScoreboardCheckStage
Definition: scoreboard_check_stage.hh:63
gem5::ComputeUnit::ComputeUnitStats::scalarMemReadsPerWF
statistics::Formula scalarMemReadsPerWF
Definition: compute_unit.hh:970
gem5::ComputeUnit::wfBarrierSlots
std::vector< WFBarrier > wfBarrierSlots
The barrier slots for this CU.
Definition: compute_unit.hh:930
gem5::ComputeUnit::doSmReturn
void doSmReturn(GPUDynInstPtr gpuDynInst)
gem5::ComputeUnit::ComputeUnitStats::instCyclesSALU
statistics::Scalar instCyclesSALU
Definition: compute_unit.hh:954
gem5::ComputeUnit::scoreboardCheckToSchedule
ScoreboardCheckToSchedule scoreboardCheckToSchedule
TODO: Update these comments once the pipe stage interface has been fully refactored.
Definition: compute_unit.hh:924
gem5::ComputeUnit::fetchStage
FetchStage fetchStage
Definition: compute_unit.hh:282
gem5::ComputeUnit::ComputeUnitStats::instInterleave
statistics::VectorDistribution instInterleave
Definition: compute_unit.hh:1090
gem5::ComputeUnit::ComputeUnitStats::flatVMemInsts
statistics::Scalar flatVMemInsts
Definition: compute_unit.hh:959
gem5::Port::name
const std::string name() const
Return port name (for DPRINTF).
Definition: port.hh:111
gem5::ComputeUnit::ComputeUnitStats::numVecOpsExecutedTwoOpFP
statistics::Scalar numVecOpsExecutedTwoOpFP
Definition: compute_unit.hh:1060
gem5::ComputeUnit::ScalarDTLBPort::retries
std::deque< PacketPtr > retries
Definition: compute_unit.hh:714
gem5::ComputeUnit::sendRequest
void sendRequest(GPUDynInstPtr gpuDynInst, PortID index, PacketPtr pkt)
Definition: compute_unit.cc:1011
gem5::MipsISA::w
Bitfield< 0 > w
Definition: pra_constants.hh:281
gem5::statistics::Distribution
A simple distribution stat.
Definition: statistics.hh:2081
gem5::ComputeUnit::coalescerToVrfBusWidth
int coalescerToVrfBusWidth
Definition: compute_unit.hh:271
gem5::ComputeUnit::lastExecCycle
std::vector< uint64_t > lastExecCycle
Definition: compute_unit.hh:325
gem5::ComputeUnit::globalSeqNum
InstSeqNum globalSeqNum
Definition: compute_unit.hh:889
gem5::ComputeUnit::debugSegFault
bool debugSegFault
Definition: compute_unit.hh:343
gem5::ComputeUnit::DTLBPort::recvRangeChange
virtual void recvRangeChange()
Called to receive an address range change from the peer response port.
Definition: compute_unit.hh:689
gem5::ComputeUnit::ITLBPort::isStalled
bool isStalled()
Definition: compute_unit.hh:728
gem5::ComputeUnit::DataPort::processMemReqEvent
void processMemReqEvent(PacketPtr pkt)
Definition: compute_unit.cc:1573
gem5::ComputeUnit::localMemoryPipe
LocalMemPipeline localMemoryPipe
Definition: compute_unit.hh:287
gem5::ComputeUnit::ComputeUnitStats::privWrites
statistics::Scalar privWrites
Definition: compute_unit.hh:998
gem5::ComputeUnit::ComputeUnitStats::kernargWrites
statistics::Scalar kernargWrites
Definition: compute_unit.hh:1004
fetch_stage.hh
gem5::ComputeUnit::numVecRegsPerSimd
int numVecRegsPerSimd
Definition: compute_unit.hh:373
gem5::ComputeUnit::DataPort::SenderState::SenderState
SenderState(GPUDynInstPtr gpuDynInst, PortID _port_index, Packet::SenderState *sender_state=nullptr)
Definition: compute_unit.hh:524
gem5::ComputeUnit::DTLBPort
Data TLB port.
Definition: compute_unit.hh:646
group.hh
comm.hh
gem5::ComputeUnit::srf
std::vector< ScalarRegisterFile * > srf
Definition: compute_unit.hh:299
gem5::WFBarrier::numYetToReachBarrier
int numYetToReachBarrier() const
Number of WFs that have not yet reached the barrier.
Definition: compute_unit.hh:111
gem5::ComputeUnit::ComputeUnitStats::scalarMemWritesPerWF
statistics::Formula scalarMemWritesPerWF
Definition: compute_unit.hh:968
gem5::ComputeUnit::LDSPort::SenderState::SenderState
SenderState(GPUDynInstPtr gpuDynInst)
Definition: compute_unit.hh:792
gem5::ComputeUnit::ComputeUnitStats::argMemInsts
statistics::Formula argMemInsts
Definition: compute_unit.hh:990
gem5::ComputeUnit::ITLBPort::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Definition: compute_unit.cc:1722
gem5::ComputeUnit::ComputeUnitStats::spillWrites
statistics::Scalar spillWrites
Definition: compute_unit.hh:992
gem5::ComputeUnit::exec_policy
EXEC_POLICY exec_policy
Definition: compute_unit.hh:341
gem5::ComputeUnit::ComputeUnitStats::spillMemInsts
statistics::Formula spillMemInsts
Definition: compute_unit.hh:993
gem5::ComputeUnit::ComputeUnitStats::scalarMemWritesPerKiloInst
statistics::Formula scalarMemWritesPerKiloInst
Definition: compute_unit.hh:976
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::ComputeUnit::ScalarDTLBPort::recvReqRetry
void recvReqRetry() override
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: compute_unit.hh:708
gem5::ComputeUnit::ComputeUnitStats::readonlyReads
statistics::Scalar readonlyReads
Definition: compute_unit.hh:1000
gem5::ScheduleToExecute
Communication interface between Schedule and Execute stages.
Definition: comm.hh:100
gem5::ComputeUnit::LDSPort::SenderState
SenderState is information carried along with the packet, esp.
Definition: compute_unit.hh:785
gem5::ComputeUnit::ComputeUnitStats::wgBlockedDueBarrierAllocation
statistics::Scalar wgBlockedDueBarrierAllocation
Definition: compute_unit.hh:1030
gem5::TLB_MISS_CACHE_HIT
@ TLB_MISS_CACHE_HIT
Definition: compute_unit.hh:83
gem5::ComputeUnit::DataPort::snoopRangeSent
bool snoopRangeSent
Definition: compute_unit.hh:516
gem5::ComputeUnit::DTLBPort::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Definition: compute_unit.cc:1389
global_memory_pipeline.hh
gem5::ComputeUnit::ComputeUnitStats::completedWGs
statistics::Scalar completedWGs
Definition: compute_unit.hh:1080
gem5::ComputeUnit::DTLBPort::stallPort
void stallPort()
Definition: compute_unit.hh:655
gem5::ComputeUnit::ComputeUnitStats::vectorMemReads
statistics::Scalar vectorMemReads
Definition: compute_unit.hh:965
gem5::ComputeUnit::DTLBPort::recvFunctional
virtual void recvFunctional(PacketPtr pkt)
Definition: compute_unit.hh:688
gem5::ComputeUnit::lastVaddrSimd
std::vector< std::vector< Addr > > lastVaddrSimd
Definition: compute_unit.hh:338
gem5::ComputeUnit::simdWidth
int simdWidth
Definition: compute_unit.hh:303
gem5::Wavefront
Definition: wavefront.hh:62
gem5::ComputeUnit::ScalarDTLBPort::isStalled
bool isStalled() const
Definition: compute_unit.hh:710
gem5::ComputeUnit::ComputeUnitStats::numVecOpsExecutedF64
statistics::Scalar numVecOpsExecutedF64
Definition: compute_unit.hh:1046
gem5::ComputeUnit::fetch
void fetch(PacketPtr pkt, Wavefront *wavefront)
gem5::TokenManager
Definition: token_port.hh:132
gem5::ComputeUnit::GMTokenPort::recvReqRetry
void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: compute_unit.hh:500
gem5::ComputeUnit::ComputeUnitStats::dynamicGMemInstrCnt
statistics::Scalar dynamicGMemInstrCnt
Definition: compute_unit.hh:1025
gem5::HSAQueueEntry
Definition: hsa_queue_entry.hh:61
gem5::ComputeUnit::numCyclesPerStoreTransfer
int numCyclesPerStoreTransfer
Definition: compute_unit.hh:272
gem5::ComputeUnit::DTLBPort::isStalled
bool isStalled()
Definition: compute_unit.hh:654
gem5::ComputeUnit::firstMemUnit
int firstMemUnit() const
Definition: compute_unit.cc:241
gem5::ComputeUnit::numCyclesPerLoadTransfer
int numCyclesPerLoadTransfer
Definition: compute_unit.hh:273
gem5::Port::id
const PortID id
A numeric identifier to distinguish ports in a vector, and set to InvalidPortID in case this port is ...
Definition: port.hh:79
gem5::ComputeUnit::ITLBPort::retries
std::deque< PacketPtr > retries
here we queue all the translation requests that were not successfully sent.
Definition: compute_unit.hh:736
gem5::ComputeUnit::pagesTouched
std::map< Addr, int > pagesTouched
Definition: compute_unit.hh:380
gem5::ComputeUnit::DataPort::recvAtomic
virtual Tick recvAtomic(PacketPtr pkt)
Definition: compute_unit.hh:543
gem5::ComputeUnit::ScalarDataPort::MemReqEvent::pkt
PacketPtr pkt
Definition: compute_unit.hh:585
gem5::ComputeUnit::LDSPort::stalled
bool stalled
whether or not it is stalled
Definition: compute_unit.hh:809
gem5::ComputeUnit::scoreboardCheckStage
ScoreboardCheckStage scoreboardCheckStage
Definition: compute_unit.hh:283
gem5::ComputeUnit::stats
gem5::ComputeUnit::ComputeUnitStats stats
gem5::ComputeUnit::DTLBPort::computeUnit
ComputeUnit * computeUnit
Definition: compute_unit.hh:683
gem5::ComputeUnit::headTailMap
std::unordered_map< GPUDynInstPtr, Tick > headTailMap
Definition: compute_unit.hh:939
gem5::ComputeUnit::ComputeUnitStats::vpc_f16
statistics::Formula vpc_f16
Definition: compute_unit.hh:1064
gem5::ComputeUnit::ComputeUnitStats::tlbLatency
statistics::Formula tlbLatency
Definition: compute_unit.hh:1013
gem5::ComputeUnit::_requestorId
RequestorID _requestorId
Definition: compute_unit.hh:468
gem5::ComputeUnit::DataPort::processMemRespEvent
void processMemRespEvent(PacketPtr pkt)
Definition: compute_unit.cc:1309
gem5::ComputeUnit::lastVaddrCU
std::vector< Addr > lastVaddrCU
Definition: compute_unit.hh:337
gem5::WFBarrier::release
void release()
Release this barrier resource so it can be used by other WGs.
Definition: compute_unit.hh:169
gem5::ComputeUnit::ScalarDTLBPort::recvTimingResp
bool recvTimingResp(PacketPtr pkt) override
Receive a timing response from the peer.
Definition: compute_unit.cc:1662
gem5::ComputeUnit::resp_tick_latency
Tick resp_tick_latency
Definition: compute_unit.hh:358
gem5::ComputeUnit::ComputeUnitStats::sALUInsts
statistics::Scalar sALUInsts
Definition: compute_unit.hh:951
gem5::ComputeUnit::exec
void exec()
Definition: compute_unit.cc:721
gem5::ExecStage
Definition: exec_stage.hh:75
gem5::ComputeUnit::DTLBPort::SenderState::SenderState
SenderState(GPUDynInstPtr gpuDynInst, PortID port_index)
Definition: compute_unit.hh:677
gem5::ComputeUnit::SQCPort::SenderState::wavefront
Wavefront * wavefront
Definition: compute_unit.hh:615
gem5::ComputeUnit::srfToScalarMemPipeBus
WaitClass srfToScalarMemPipeBus
Definition: compute_unit.hh:241
gem5::ComputeUnit::releaseBarrier
void releaseBarrier(int bar_id)
Definition: compute_unit.cc:698
scoreboard_check_stage.hh
gem5::ComputeUnit::ComputeUnitStats::instCyclesScMemPerSimd
statistics::Vector instCyclesScMemPerSimd
Definition: compute_unit.hh:982
gem5::WFBarrier::_maxBarrierCnt
int _maxBarrierCnt
The maximum number of WFs that can reach this barrier.
Definition: compute_unit.hh:200
gem5::ComputeUnit::spBypassLength
int spBypassLength() const
Definition: compute_unit.hh:391
gem5::ComputeUnit::numYetToReachBarrier
int numYetToReachBarrier(int bar_id)
Definition: compute_unit.cc:649
gem5::statistics::Vector
A vector of scalar stats.
Definition: statistics.hh:2003
gem5::ComputeUnit::dpBypassPipeLength
int dpBypassPipeLength
Definition: compute_unit.hh:309
gem5::ComputeUnit::ComputeUnitStats::ldsBankConflictDist
statistics::Distribution ldsBankConflictDist
Definition: compute_unit.hh:1019
gem5::ComputeUnit::getRefCounter
int32_t getRefCounter(const uint32_t dispatchId, const uint32_t wgId) const
Definition: compute_unit.cc:1969
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2536
gem5::ComputeUnit::ITLBPort::SenderState::wavefront
Wavefront * wavefront
Definition: compute_unit.hh:744
std::vector
STL vector class.
Definition: stl.hh:37
gem5::ComputeUnit::LDSPort::recvAtomic
virtual Tick recvAtomic(PacketPtr pkt)
Definition: compute_unit.hh:817
gem5::ComputeUnit::scalarPipeLength
int scalarPipeLength() const
Definition: compute_unit.hh:393
gem5::ComputeUnit::ComputeUnitStats::kernargReads
statistics::Scalar kernargReads
Definition: compute_unit.hh:1003
gem5::ComputeUnit::prefetchDepth
int prefetchDepth
Definition: compute_unit.hh:333
gem5::ComputeUnit::ComputeUnitStats::numVecOpsExecutedFMA32
statistics::Scalar numVecOpsExecutedFMA32
Definition: compute_unit.hh:1049
gem5::ComputeUnit::vrfToGlobalMemPipeBus
WaitClass vrfToGlobalMemPipeBus
Definition: compute_unit.hh:225
gem5::ComputeUnit::ComputeUnitStats::ldsNoFlatInsts
statistics::Scalar ldsNoFlatInsts
Definition: compute_unit.hh:957
gem5::ComputeUnit::resetBarrier
void resetBarrier(int bar_id)
Definition: compute_unit.cc:684
gem5::ComputeUnit::SQCPort::computeUnit
ComputeUnit * computeUnit
Definition: compute_unit.hh:629
gem5::ComputeUnit::ComputeUnitStats::globalReads
statistics::Scalar globalReads
Definition: compute_unit.hh:985
gem5::ComputeUnit::storeBusLength
int storeBusLength() const
Definition: compute_unit.hh:394
gem5::ComputeUnit::SQCPort::retries
std::deque< std::pair< PacketPtr, Wavefront * > > retries
Definition: compute_unit.hh:626
gem5::ComputeUnit::ComputeUnitStats::groupMemInsts
statistics::Formula groupMemInsts
Definition: compute_unit.hh:996
gem5::ComputeUnit::ComputeUnitStats::vpc
statistics::Formula vpc
Definition: compute_unit.hh:1063
gem5::ComputeUnit::ComputeUnitStats::activeLanesPerLMemInstrDist
statistics::Distribution activeLanesPerLMemInstrDist
Definition: compute_unit.hh:1070
gem5::ComputeUnit::memPortTokens
TokenManager * memPortTokens
Definition: compute_unit.hh:506
gem5::WFBarrier::decMaxBarrierCnt
void decMaxBarrierCnt()
Decrement the number of WFs that are participating in this barrier.
Definition: compute_unit.hh:158
gem5::ComputeUnit::getLds
LdsState & getLds() const
Definition: compute_unit.hh:474
gem5::FetchStage
Definition: fetch_stage.hh:56
gem5::ScheduleStage
Definition: schedule_stage.hh:64
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::ComputeUnit::numVectorSharedMemUnits
int numVectorSharedMemUnits
Definition: compute_unit.hh:229
gem5::ComputeUnit::shader
Shader * shader
Definition: compute_unit.hh:355
gem5::ComputeUnit::req_tick_latency
Tick req_tick_latency
Definition: compute_unit.hh:357
gem5::ComputeUnit::ComputeUnitStats::vectorMemWritesPerWF
statistics::Formula vectorMemWritesPerWF
Definition: compute_unit.hh:964
gem5::ComputeUnit::ComputeUnitStats::numVecOpsExecutedMAD64
statistics::Scalar numVecOpsExecutedMAD64
Definition: compute_unit.hh:1058
gem5::ComputeUnit::issuePeriod
Cycles issuePeriod
Definition: compute_unit.hh:315
gem5::ComputeUnit::ComputeUnitStats::headTailLatency
statistics::Distribution headTailLatency
Definition: compute_unit.hh:1084
gem5::ComputeUnit::scalarDataPort
ScalarDataPort scalarDataPort
Definition: compute_unit.hh:851
gem5::ComputeUnit::ITLBPort::stallPort
void stallPort()
Definition: compute_unit.hh:729
gem5::ComputeUnit::ComputeUnitStats::threadCyclesVALU
statistics::Scalar threadCyclesVALU
Definition: compute_unit.hh:955
gem5::ComputeUnit::cu_id
int cu_id
Definition: compute_unit.hh:294
gem5::ComputeUnit::ComputeUnitStats::numVecOpsExecutedMAC32
statistics::Scalar numVecOpsExecutedMAC32
Definition: compute_unit.hh:1053
gem5::ComputeUnit::ComputeUnitStats::numVecOpsExecutedMAD32
statistics::Scalar numVecOpsExecutedMAD32
Definition: compute_unit.hh:1057
gem5::ComputeUnit::ComputeUnitStats::vectorMemReadsPerWF
statistics::Formula vectorMemReadsPerWF
Definition: compute_unit.hh:966
gem5::ComputeUnit::vrf
std::vector< VectorRegisterFile * > vrf
Definition: compute_unit.hh:297
gem5::ComputeUnit::ComputeUnitStats::instCyclesVMemPerSimd
statistics::Vector instCyclesVMemPerSimd
Definition: compute_unit.hh:981
gem5::ComputeUnit::ComputeUnitStats::dynamicFlatMemInstrCnt
statistics::Scalar dynamicFlatMemInstrCnt
Definition: compute_unit.hh:1027
gem5::Event::setFlags
void setFlags(Flags _flags)
Definition: eventq.hh:328
gem5::ComputeUnit::SQCPort::recvReqRetry
virtual void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: compute_unit.cc:988
gem5::ComputeUnit::ComputeUnitStats::groupReads
statistics::Scalar groupReads
Definition: compute_unit.hh:994
gem5::ComputeUnit::ComputeUnitStats::vpc_f64
statistics::Formula vpc_f64
Definition: compute_unit.hh:1066
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::ComputeUnit::injectGlobalMemFence
void injectGlobalMemFence(GPUDynInstPtr gpuDynInst, bool kernelMemSync, RequestPtr req=nullptr)
Definition: compute_unit.cc:1231
gem5::ComputeUnit::ScalarDataPort::computeUnit
ComputeUnit * computeUnit
Definition: compute_unit.hh:601
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::EventBase::AutoDelete
static const FlagsType AutoDelete
Definition: eventq.hh:107
gem5::ComputeUnit::LDSPort::sendTimingReq
virtual bool sendTimingReq(PacketPtr pkt)
attempt to send this packet, either the port is already stalled, the request is nack'd and must stall...
Definition: compute_unit.cc:2037
gem5::ComputeUnit::locMemToVrfBus
WaitClass locMemToVrfBus
Definition: compute_unit.hh:231
gem5::ComputeUnit::LDSPort::unstallPort
void unstallPort()
Definition: compute_unit.hh:773
gem5::ComputeUnit::idleWfs
int idleWfs
Definition: compute_unit.hh:346
gem5::ComputeUnit::ComputeUnitStats::kernargMemInsts
statistics::Formula kernargMemInsts
Definition: compute_unit.hh:1005
gem5::TLB_CACHE
TLB_CACHE
Definition: compute_unit.hh:80
gem5::ComputeUnit::ComputeUnitStats::flatVMemInstsPerWF
statistics::Formula flatVMemInstsPerWF
Definition: compute_unit.hh:960
gem5::ComputeUnit::SQCPort::recvRangeChange
virtual void recvRangeChange()
Called to receive an address range change from the peer response port.
Definition: compute_unit.hh:634
gem5::ComputeUnit::idleCUTimeout
Tick idleCUTimeout
Definition: compute_unit.hh:345
gem5::ComputeUnit::loadBusLength
int loadBusLength() const
Definition: compute_unit.hh:395
gem5::ComputeUnit::ComputeUnitStats
Definition: compute_unit.hh:945
gem5::ComputeUnit::numScalarMemUnits
int numScalarMemUnits
Definition: compute_unit.hh:237
gem5::ComputeUnit::DTLBPort::recvReqRetry
virtual void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: compute_unit.cc:1631
gem5::ComputeUnit::processTimingPacket
bool processTimingPacket(PacketPtr pkt)
gem5::ComputeUnit::ITLBPort::SenderState
SenderState is information carried along with the packet throughout the TLB hierarchy.
Definition: compute_unit.hh:741
gem5::ComputeUnit
Definition: compute_unit.hh:203
gem5::ComputeUnit::ScalarDataPort::MemReqEvent::process
void process()
Definition: compute_unit.cc:1602
gem5::ComputeUnit::pageAccesses
pageDataStruct pageAccesses
Definition: compute_unit.hh:485
gem5::ComputeUnit::ScalarDataPort::retries
std::deque< PacketPtr > retries
Definition: compute_unit.hh:598
gem5::ComputeUnit::ScalarDataPort::SenderState::_gpuDynInst
GPUDynInstPtr _gpuDynInst
Definition: compute_unit.hh:577
gem5::ComputeUnit::ComputeUnitStats::flatLDSInsts
statistics::Scalar flatLDSInsts
Definition: compute_unit.hh:961
gem5::ComputeUnit::numScalarALUs
int numScalarALUs
Definition: compute_unit.hh:250
gem5::ComputeUnit::numVectorALUs
int numVectorALUs
Definition: compute_unit.hh:246
gem5::ComputeUnit::DataPort::DataPort
DataPort(const std::string &_name, ComputeUnit *_cu, PortID id)
Definition: compute_unit.hh:513
gem5::ComputeUnit::wavefrontSize
int wavefrontSize
Definition: compute_unit.hh:890
gem5::ComputeUnit::startWavefront
void startWavefront(Wavefront *w, int waveId, LdsChunk *ldsChunk, HSAQueueEntry *task, int bar_id, bool fetchContext=false)
Definition: compute_unit.cc:311
gem5::ComputeUnit::sqcTLBPort
ITLBPort sqcTLBPort
Definition: compute_unit.hh:857
gem5::ComputeUnit::ComputeUnitStats::privReads
statistics::Scalar privReads
Definition: compute_unit.hh:997
gem5::ComputeUnit::functionalTLB
bool functionalTLB
Definition: compute_unit.hh:347
gem5::ComputeUnit::numAtBarrier
int numAtBarrier(int bar_id)
Definition: compute_unit.cc:670
gem5::WFBarrier::numAtBarrier
int numAtBarrier() const
Definition: compute_unit.hh:102
gem5::ComputeUnit::incNumAtBarrier
void incNumAtBarrier(int bar_id)
Definition: compute_unit.cc:663
gem5::ComputeUnit::ScalarDataPort::MemReqEvent::scalarDataPort
ScalarDataPort & scalarDataPort
Definition: compute_unit.hh:584
gem5::ComputeUnit::ComputeUnitStats::completedWfs
statistics::Scalar completedWfs
Definition: compute_unit.hh:1079
gem5::ComputeUnit::DTLBPort::recvAtomic
virtual Tick recvAtomic(PacketPtr pkt)
Definition: compute_unit.hh:687
gem5::ScalarMemPipeline
Definition: scalar_memory_pipeline.hh:60
gem5::ComputeUnit::ComputeUnitStats::numVecOpsExecuted
statistics::Scalar numVecOpsExecuted
Definition: compute_unit.hh:1040
gem5::ComputeUnit::oprNetPipeLength
int oprNetPipeLength() const
Definition: compute_unit.hh:389
gem5::TLB_HIT_CACHE_MISS
@ TLB_HIT_CACHE_MISS
Definition: compute_unit.hh:84
gem5::ComputeUnit::cacheLineBits
int cacheLineBits
Definition: compute_unit.hh:888
gem5::WFBarrier::InvalidID
static const int InvalidID
Definition: compute_unit.hh:99
gem5::ComputeUnit::ITLBPort::computeUnit
ComputeUnit * computeUnit
Definition: compute_unit.hh:750
gem5::ComputeUnit::SQCPort::recvFunctional
virtual void recvFunctional(PacketPtr pkt)
Definition: compute_unit.hh:633
gem5::ComputeUnit::decMaxBarrierCnt
void decMaxBarrierCnt(int bar_id)
Definition: compute_unit.cc:691
gem5::ComputeUnit::vectorSharedMemUnit
WaitClass vectorSharedMemUnit
Definition: compute_unit.hh:235
gem5::ComputeUnit::SQCPort::SenderState::kernId
int kernId
Definition: compute_unit.hh:618
gem5::ComputeUnit::releaseWFsFromBarrier
void releaseWFsFromBarrier(int bar_id)
Definition: compute_unit.cc:706
gem5::ComputeUnit::ITLBPort
Definition: compute_unit.hh:721
gem5::ComputeUnit::ComputeUnitStats::activeLanesPerGMemInstrDist
statistics::Distribution activeLanesPerGMemInstrDist
Definition: compute_unit.hh:1069
gem5::ComputeUnit::ScalarDTLBPort::ScalarDTLBPort
ScalarDTLBPort(const std::string &_name, ComputeUnit *_cu)
Definition: compute_unit.hh:696
gem5::Event
Definition: eventq.hh:251
gem5::ComputeUnit::scalarMemUnit
WaitClass scalarMemUnit
Definition: compute_unit.hh:243
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::ComputeUnit::initiateFetch
void initiateFetch(Wavefront *wavefront)
gem5::ComputeUnit::execStage
ExecStage execStage
Definition: compute_unit.hh:285
gem5::ComputeUnit::ScalarDataPort::MemReqEvent::description
const char * description() const
Return a C string describing the event.
Definition: compute_unit.cc:1596
gem5::ComputeUnit::ComputeUnitStats::vALUInsts
statistics::Scalar vALUInsts
Definition: compute_unit.hh:949
gem5::ComputeUnit::ComputeUnitStats::instCyclesVALU
statistics::Scalar instCyclesVALU
Definition: compute_unit.hh:953
gem5::ComputeUnit::ComputeUnitStats::numVecOpsExecutedMAC64
statistics::Scalar numVecOpsExecutedMAC64
Definition: compute_unit.hh:1054
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
statistics.hh
gem5::ComputeUnit::handleMemPacket
void handleMemPacket(PacketPtr pkt, int memport_index)
gem5::ComputeUnit::LDSPort::SenderState::_gpuDynInst
GPUDynInstPtr _gpuDynInst
Definition: compute_unit.hh:789
gem5::ComputeUnit::DTLBPort::unstallPort
void unstallPort()
Definition: compute_unit.hh:656
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::ComputeUnit::tickEvent
EventFunctionWrapper tickEvent
Definition: compute_unit.hh:290
gem5::WaitClass
Definition: misc.hh:69
gem5::ComputeUnit::scheduleToExecute
ScheduleToExecute scheduleToExecute
Definition: compute_unit.hh:925
gem5::RR
@ RR
Definition: compute_unit.hh:77
gem5::ComputeUnit::globalMemoryPipe
GlobalMemPipeline globalMemoryPipe
Definition: compute_unit.hh:286
gem5::ComputeUnit::resetRegisterPool
void resetRegisterPool()
Definition: compute_unit.cc:412
gem5::ComputeUnit::ScalarDTLBPort::computeUnit
ComputeUnit * computeUnit
Definition: compute_unit.hh:717
gem5::ComputeUnit::registerManager
RegisterManager * registerManager
Definition: compute_unit.hh:280
gem5::ComputeUnit::ComputeUnitStats::numInstrExecuted
statistics::Scalar numInstrExecuted
Definition: compute_unit.hh:1035
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WFBarrier()
Definition: compute_unit.hh:95
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@ TLB_MISS_CACHE_MISS
Definition: compute_unit.hh:82
gem5::ComputeUnit::ScalarDataPort::recvTimingResp
bool recvTimingResp(PacketPtr pkt) override
Receive a timing response from the peer.
Definition: compute_unit.cc:904
gem5::ComputeUnit::ITLBPort::recvReqRetry
virtual void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: compute_unit.cc:1775
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void stallPort()
Definition: compute_unit.hh:711
GEM5_NO_DISCARD
#define GEM5_NO_DISCARD
Definition: compiler.hh:70
gem5::ComputeUnit::ComputeUnitStats::numCASOps
statistics::Scalar numCASOps
Definition: compute_unit.hh:1077
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gem5::ComputeUnit::DataPort::createMemReqEvent
EventFunctionWrapper * createMemReqEvent(PacketPtr pkt)
Definition: compute_unit.cc:1557
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statistics::Formula vectorMemInstsPerKiloInst
Definition: compute_unit.hh:974
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EXEC_POLICY
Definition: compute_unit.hh:74
gem5::ComputeUnit::~ComputeUnit
~ComputeUnit()
Definition: compute_unit.cc:220
gem5::ComputeUnit::DTLBPort::retries
std::deque< PacketPtr > retries
here we queue all the translation requests that were not successfully sent.
Definition: compute_unit.hh:662
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Data access Port.
Definition: compute_unit.hh:510
gem5::ComputeUnit::ComputeUnitStats::ldsBankAccesses
statistics::Scalar ldsBankAccesses
Definition: compute_unit.hh:1018
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Definition: compute_unit.hh:605
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Cycles vrf_lm_bus_latency
Definition: compute_unit.hh:322
gem5::ComputeUnit::GMTokenPort
Definition: compute_unit.hh:489
gem5::ComputeUnit::ScalarDTLBPort::stalled
bool stalled
Definition: compute_unit.hh:718
gem5::ComputeUnit::spBypassPipeLength
int spBypassPipeLength
Definition: compute_unit.hh:306
gem5::ComputeUnit::DTLBPort::SenderState::_gpuDynInst
GPUDynInstPtr _gpuDynInst
Definition: compute_unit.hh:670
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int activeWaves
Definition: compute_unit.hh:943
gem5::ComputeUnit::ComputeUnitStats::numTimesWgBlockedDueVgprAlloc
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Definition: compute_unit.hh:1074
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void processFetchReturn(PacketPtr pkt)
gem5::ComputeUnit::DataPort::getDeviceAddressRanges
virtual void getDeviceAddressRanges(AddrRangeList &resp, bool &snoop)
Definition: compute_unit.hh:549
gem5::ComputeUnit::ITLBPort::recvAtomic
virtual Tick recvAtomic(PacketPtr pkt)
Definition: compute_unit.hh:754
compiler.hh
gem5::LdsChunk
this represents a slice of the overall LDS, intended to be associated with an individual workgroup
Definition: lds_state.hh:58
gem5::ComputeUnit::cacheLineSize
int cacheLineSize() const
Definition: compute_unit.hh:413
gem5::ComputeUnit::ITLBPort::recvRangeChange
virtual void recvRangeChange()
Called to receive an address range change from the peer response port.
Definition: compute_unit.hh:756
gem5::ComputeUnit::mapWaveToScalarMem
int mapWaveToScalarMem(Wavefront *w) const
Definition: compute_unit.cc:289
gem5::ComputeUnit::mapWaveToGlobalMem
int mapWaveToGlobalMem(Wavefront *w) const
Definition: compute_unit.cc:273
gem5::ComputeUnit::deleteFromPipeMap
void deleteFromPipeMap(Wavefront *w)
Definition: compute_unit.cc:509
gem5::ComputeUnit::SQCPort::recvAtomic
virtual Tick recvAtomic(PacketPtr pkt)
Definition: compute_unit.hh:632
gem5::ComputeUnit::LDSPort
the port intended to communicate between the CU and its LDS
Definition: compute_unit.hh:763
gem5::ComputeUnit::doFlush
void doFlush(GPUDynInstPtr gpuDynInst)
trigger flush operation in the cu
Definition: compute_unit.cc:404
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::ComputeUnit::DataPort::SenderState::port_index
PortID port_index
Definition: compute_unit.hh:521
gem5::ComputeUnit::init
virtual void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: compute_unit.cc:754
gem5::ComputeUnit::scalarALUs
std::vector< WaitClass > scalarALUs
Definition: compute_unit.hh:251
gem5::ComputeUnit::DataPort::SenderState::_gpuDynInst
GPUDynInstPtr _gpuDynInst
Definition: compute_unit.hh:520
gem5::ComputeUnit::dpBypassLength
int dpBypassLength() const
Definition: compute_unit.hh:392
gem5::ComputeUnit::memPort
std::vector< DataPort > memPort
The memory port for SIMD data accesses.
Definition: compute_unit.hh:847
gem5::OLDEST
@ OLDEST
Definition: compute_unit.hh:76
gem5::ComputeUnit::ComputeUnitStats::scalarMemReadsPerKiloInst
statistics::Formula scalarMemReadsPerKiloInst
Definition: compute_unit.hh:975
gem5::Packet::SenderState
A virtual base opaque structure used to hold state associated with the packet (e.g....
Definition: packet.hh:457
gem5::ComputeUnit::ComputeUnitStats::vectorMemReadsPerKiloInst
statistics::Formula vectorMemReadsPerKiloInst
Definition: compute_unit.hh:972
gem5::ComputeUnit::DTLBPort::SenderState::portIndex
PortID portIndex
Definition: compute_unit.hh:674
gem5::ComputeUnit::perLaneTLB
bool perLaneTLB
Definition: compute_unit.hh:331
local_memory_pipeline.hh
gem5::ComputeUnit::instExecPerSimd
std::vector< uint64_t > instExecPerSimd
Definition: compute_unit.hh:328
gem5::ComputeUnit::lastMemUnit
int lastMemUnit() const
Definition: compute_unit.cc:248
gem5::ComputeUnit::ITLBPort::SenderState::SenderState
SenderState(Wavefront *_wavefront)
Definition: compute_unit.hh:746
gem5::ComputeUnit::ScalarDTLBPort::unstallPort
void unstallPort()
Definition: compute_unit.hh:712
gem5::ComputeUnit::lastVaddrWF
std::vector< std::vector< std::vector< Addr > > > lastVaddrWF
Definition: compute_unit.hh:339
gem5::ComputeUnit::ScalarDTLBPort::SenderState::_gpuDynInst
GPUDynInstPtr _gpuDynInst
Definition: compute_unit.hh:704
gem5::ComputeUnit::ComputeUnitStats::groupWrites
statistics::Scalar groupWrites
Definition: compute_unit.hh:995
gem5::ComputeUnit::LDSPort::LDSPort
LDSPort(const std::string &_name, ComputeUnit *_cu)
Definition: compute_unit.hh:766
gem5::ComputeUnit::numBarrierSlots
int numBarrierSlots() const
Definition: compute_unit.hh:446
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ComputeUnit::ComputeUnitStats::globalWrites
statistics::Scalar globalWrites
Definition: compute_unit.hh:986
gem5::ComputeUnit::ComputeUnitStats::vALUInstsPerWF
statistics::Formula vALUInstsPerWF
Definition: compute_unit.hh:950
gem5::ComputeUnit::getTokenManager
TokenManager * getTokenManager()
Definition: compute_unit.hh:839
gem5::ComputeUnit::ScalarDataPort::MemReqEvent::MemReqEvent
MemReqEvent(ScalarDataPort &_scalar_data_port, PacketPtr _pkt)
Definition: compute_unit.hh:588
gem5::ComputeUnit::ComputeUnitStats::numTimesWgBlockedDueSgprAlloc
statistics::Scalar numTimesWgBlockedDueSgprAlloc
Definition: compute_unit.hh:1076
gem5::ComputeUnit::ComputeUnitStats::numVecOpsExecutedF16
statistics::Scalar numVecOpsExecutedF16
Definition: compute_unit.hh:1042
gem5::ComputeUnit::barrierSlot
WFBarrier & barrierSlot(int bar_id)
Definition: compute_unit.hh:420
scalar_memory_pipeline.hh
gem5::ComputeUnit::exitCallback
void exitCallback()
Definition: compute_unit.cc:1922
gem5::ComputeUnit::SQCPort::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Definition: compute_unit.cc:981
gem5::ComputeUnit::ComputeUnitStats::privMemInsts
statistics::Formula privMemInsts
Definition: compute_unit.hh:999
gem5::ComputeUnit::mapWaveToScalarAlu
int mapWaveToScalarAlu(Wavefront *w) const
Definition: compute_unit.cc:255
schedule_stage.hh
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:51
gem5::ComputeUnit::hasDispResources
bool hasDispResources(HSAQueueEntry *task, int &num_wfs_in_wg)
Definition: compute_unit.cc:521
gem5::ComputeUnit::DataPort::computeUnit
ComputeUnit * computeUnit
Definition: compute_unit.hh:540
gem5::ComputeUnit::getFreeBarrierId
int getFreeBarrierId()
Definition: compute_unit.hh:427
gem5::ComputeUnit::wfSize
int wfSize() const
Definition: compute_unit.hh:396
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::ComputeUnit::pipeMap
std::unordered_set< uint64_t > pipeMap
Definition: compute_unit.hh:278
gem5::ComputeUnit::SQCPort::snoopRangeSent
bool snoopRangeSent
Definition: compute_unit.hh:611
gem5::TLB_HIT_CACHE_HIT
@ TLB_HIT_CACHE_HIT
Definition: compute_unit.hh:85
gem5::ComputeUnit::LDSPort::recvReqRetry
virtual void recvReqRetry()
the bus is telling the port that there is now space so retrying stalled requests should work now this...
Definition: compute_unit.cc:2079
gem5::ComputeUnit::DataPort::recvFunctional
virtual void recvFunctional(PacketPtr pkt)
Definition: compute_unit.hh:544
gem5::ComputeUnit::SQCPort::SenderState::saved
Packet::SenderState * saved
Definition: compute_unit.hh:616
gem5::ComputeUnit::DataPort::retries
std::deque< std::pair< PacketPtr, GPUDynInstPtr > > retries
Definition: compute_unit.hh:537
gem5::ComputeUnit::SQCPort::getDeviceAddressRanges
virtual void getDeviceAddressRanges(AddrRangeList &resp, bool &snoop)
Definition: compute_unit.hh:638
gem5::ComputeUnit::SQCPort::SenderState::SenderState
SenderState(Wavefront *_wavefront, Packet::SenderState *sender_state=nullptr, int _kernId=-1)
Definition: compute_unit.hh:620
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::ComputeUnit::updateInstStats
void updateInstStats(GPUDynInstPtr gpuDynInst)
Definition: compute_unit.cc:1805
gem5::ComputeUnit::ComputeUnitStats::numALUInstsExecuted
statistics::Formula numALUInstsExecuted
Definition: compute_unit.hh:1072
gem5::ComputeUnit::ComputeUnitStats::instCyclesLdsPerSimd
statistics::Vector instCyclesLdsPerSimd
Definition: compute_unit.hh:983
register_manager.hh
gem5::ComputeUnit::ComputeUnitStats::argReads
statistics::Scalar argReads
Definition: compute_unit.hh:988
gem5::ComputeUnit::getCacheLineBits
int getCacheLineBits() const
Definition: compute_unit.hh:414
gem5::ComputeUnit::pageDataStruct
std::unordered_map< Addr, std::pair< int, int > > pageDataStruct
Definition: compute_unit.hh:484
gem5::ComputeUnit::ComputeUnitStats::globalMemInsts
statistics::Formula globalMemInsts
Definition: compute_unit.hh:987
gem5::ComputeUnit::ComputeUnitStats::wgBlockedDueLdsAllocation
statistics::Scalar wgBlockedDueLdsAllocation
Definition: compute_unit.hh:1031
gem5::ComputeUnit::LDSPort::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
get the result of packets sent to the LDS when they return
Definition: compute_unit.cc:2015
gem5::ComputeUnit::operandNetworkLength
int operandNetworkLength
Definition: compute_unit.hh:313
gem5::ComputeUnit::numVectorGlobalMemUnits
int numVectorGlobalMemUnits
Definition: compute_unit.hh:221
gem5::ComputeUnit::prefetchStride
int prefetchStride
Definition: compute_unit.hh:335
gem5::ComputeUnit::Params
ComputeUnitParams Params
Definition: compute_unit.hh:292
gem5::ComputeUnit::ComputeUnitStats::numVecOpsExecutedMAD16
statistics::Scalar numVecOpsExecutedMAD16
Definition: compute_unit.hh:1056
gem5::ComputeUnit::ComputeUnitStats::ipc
statistics::Formula ipc
Definition: compute_unit.hh:1067
gem5::ComputeUnit::localMemBarrier
bool localMemBarrier
Definition: compute_unit.hh:348
gem5::ComputeUnit::updatePageDivergenceDist
void updatePageDivergenceDist(Addr addr)
Definition: compute_unit.cc:1911
gem5::ScoreboardCheckToSchedule
Communication interface between ScoreboardCheck and Schedule stages.
Definition: comm.hh:64
gem5::ComputeUnit::vectorRegsReserved
std::vector< int > vectorRegsReserved
Definition: compute_unit.hh:369
gem5::ComputeUnit::ComputeUnitStats::readonlyWrites
statistics::Scalar readonlyWrites
Definition: compute_unit.hh:1001
gem5::ComputeUnit::ComputeUnitStats::numVecOpsExecutedMAC16
statistics::Scalar numVecOpsExecutedMAC16
Definition: compute_unit.hh:1052
gem5::ComputeUnit::ComputeUnitStats::waveLevelParallelism
statistics::Distribution waveLevelParallelism
Definition: compute_unit.hh:1007
gem5::ComputeUnit::ComputeUnitStats::scalarMemWrites
statistics::Scalar scalarMemWrites
Definition: compute_unit.hh:967
gem5::ComputeUnit::ITLBPort::unstallPort
void unstallPort()
Definition: compute_unit.hh:730
gem5::ComputeUnit::vrf_gm_bus_latency
Cycles vrf_gm_bus_latency
Definition: compute_unit.hh:318
gem5::ComputeUnit::vrfToCoalescerBusWidth
int vrfToCoalescerBusWidth
Definition: compute_unit.hh:270
gem5::ComputeUnit::ComputeUnitStats::controlFlowDivergenceDist
statistics::Distribution controlFlowDivergenceDist
Definition: compute_unit.hh:1068
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::ComputeUnit::ComputeUnitStats::vectorMemWrites
statistics::Scalar vectorMemWrites
Definition: compute_unit.hh:963
gem5::ComputeUnit::insertInPipeMap
void insertInPipeMap(Wavefront *w)
Definition: compute_unit.cc:500
gem5::GlobalMemPipeline
Definition: global_memory_pipeline.hh:61
types.hh
gem5::ComputeUnit::LDSPort::stallPort
void stallPort()
Definition: compute_unit.hh:772
gem5::WFBarrier::_numAtBarrier
int _numAtBarrier
The number of WFs in the WG that have reached the barrier.
Definition: compute_unit.hh:191
gem5::ComputeUnit::ScalarDTLBPort::SenderState
Definition: compute_unit.hh:701
gem5::ComputeUnit::mapWaveToLocalMem
int mapWaveToLocalMem(Wavefront *w) const
Definition: compute_unit.cc:281
gem5::ComputeUnit::LDSPort::recvRangeChange
virtual void recvRangeChange()
Called to receive an address range change from the peer response port.
Definition: compute_unit.hh:825
gem5::ComputeUnit::ldsPort
LDSPort ldsPort
The port to access the Local Data Store Can be connected to a LDS object.
Definition: compute_unit.hh:836
gem5::ComputeUnit::LDSPort::computeUnit
ComputeUnit * computeUnit
Definition: compute_unit.hh:811
gem5::ComputeUnit::ComputeUnitStats::numVecOpsExecutedFMA64
statistics::Scalar numVecOpsExecutedFMA64
Definition: compute_unit.hh:1050
clocked_object.hh
gem5::ComputeUnit::ComputeUnitStats::flatLDSInstsPerWF
statistics::Formula flatLDSInstsPerWF
Definition: compute_unit.hh:962
std::deque
STL deque class.
Definition: stl.hh:44
gem5::WFBarrier
WF barrier slots.
Definition: compute_unit.hh:92
gem5::ComputeUnit::DataPort::SenderState::saved
Packet::SenderState * saved
Definition: compute_unit.hh:522
gem5::ComputeUnit::isDone
bool isDone() const
Definition: compute_unit.cc:1939
gem5::ComputeUnit::LDSPort::SenderState::getMemInst
GPUDynInstPtr getMemInst() const
Definition: compute_unit.hh:798
gem5::ComputeUnit::ComputeUnitStats::hitsPerTLBLevel
statistics::Vector hitsPerTLBLevel
Definition: compute_unit.hh:1016
token_port.hh
gem5::ComputeUnit::maxBarrierCnt
int maxBarrierCnt(int bar_id)
Definition: compute_unit.cc:677
gem5::ComputeUnit::scalarRegsReserved
std::vector< int > scalarRegsReserved
Definition: compute_unit.hh:371
gem5::ComputeUnit::fillKernelState
void fillKernelState(Wavefront *w, HSAQueueEntry *task)
Definition: compute_unit.cc:297
gem5::ComputeUnit::lds
LdsState & lds
Definition: compute_unit.hh:470
gem5::ComputeUnit::LDSPort::recvFunctional
virtual void recvFunctional(PacketPtr pkt)
Definition: compute_unit.hh:820
gem5::ComputeUnit::DTLBPort::SenderState
SenderState is information carried along with the packet throughout the TLB hierarchy.
Definition: compute_unit.hh:667
gem5::ComputeUnit::SQCPort::SQCPort
SQCPort(const std::string &_name, ComputeUnit *_cu)
Definition: compute_unit.hh:608
gem5::ComputeUnit::vrfToLocalMemPipeBus
WaitClass vrfToLocalMemPipeBus
Definition: compute_unit.hh:233
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::ComputeUnit::ComputeUnitStats::execRateDist
statistics::Distribution execRateDist
Definition: compute_unit.hh:1038
gem5::ComputeUnit::tlbPort
std::vector< DTLBPort > tlbPort
Definition: compute_unit.hh:849
gem5::ComputeUnit::ComputeUnitStats::numVecOpsExecutedF32
statistics::Scalar numVecOpsExecutedF32
Definition: compute_unit.hh:1044
gem5::ComputeUnit::isVectorAluIdle
bool isVectorAluIdle(uint32_t simdId) const
Definition: compute_unit.cc:1976
gem5::ComputeUnit::numScalarRegsPerSimd
int numScalarRegsPerSimd
Definition: compute_unit.hh:375
gem5::ComputeUnit::vectorALUs
std::vector< WaitClass > vectorALUs
Definition: compute_unit.hh:247
gem5::WFBarrier::allAtBarrier
bool allAtBarrier() const
Have all WFs participating in this barrier reached the barrier? If so, then the barrier is satisfied ...
Definition: compute_unit.hh:148
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::ComputeUnit::sendScalarRequest
void sendScalarRequest(GPUDynInstPtr gpuDynInst, PacketPtr pkt)
Definition: compute_unit.cc:1204
gem5::ComputeUnit::LDSPort::isStalled
bool isStalled() const
Definition: compute_unit.hh:771
gem5::ComputeUnit::countPages
bool countPages
Definition: compute_unit.hh:353
gem5::ComputeUnit::_cacheLineSize
const int _cacheLineSize
Definition: compute_unit.hh:886
gem5::ComputeUnit::freeBarrierIds
std::unordered_set< int > freeBarrierIds
A set used to easily retrieve a free barrier ID.
Definition: compute_unit.hh:934
gem5::ComputeUnit::ComputeUnitStats::ComputeUnitStats
ComputeUnitStats(statistics::Group *parent, int n_wf)
Definition: compute_unit.cc:2110
gem5::RegisterManager
Definition: register_manager.hh:59
gem5::ComputeUnit::LDSPort::retries
std::queue< PacketPtr > retries
here we queue all the requests that were not successfully sent.
Definition: compute_unit.hh:779
gem5::ComputeUnit::scalarMemToSrfBus
WaitClass scalarMemToSrfBus
Definition: compute_unit.hh:239
gem5::ComputeUnit::scalarDTLBPort
ScalarDTLBPort scalarDTLBPort
Definition: compute_unit.hh:853
gem5::LocalMemPipeline
Definition: local_memory_pipeline.hh:59
gem5::ComputeUnit::ComputeUnitStats::pageDivergenceDist
statistics::Distribution pageDivergenceDist
Definition: compute_unit.hh:1023
gem5::ComputeUnit::DataPort::recvRangeChange
virtual void recvRangeChange()
Called to receive an address range change from the peer response port.
Definition: compute_unit.hh:545
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
gem5::WFBarrier::setMaxBarrierCnt
void setMaxBarrierCnt(int max_barrier_cnt)
Set the maximum barrier count (i.e., the number of WFs that are participating in the barrier).
Definition: compute_unit.hh:127
gem5::statistics::VectorDistribution
A vector of distributions.
Definition: statistics.hh:2242
gem5::ComputeUnit::ScalarDataPort::MemReqEvent
Definition: compute_unit.hh:581
gem5::ComputeUnit::ScalarDataPort::ScalarDataPort
ScalarDataPort(const std::string &_name, ComputeUnit *_cu)
Definition: compute_unit.hh:561
gem5::ComputeUnit::ComputeUnitStats::argWrites
statistics::Scalar argWrites
Definition: compute_unit.hh:989
gem5::ComputeUnit::GMTokenPort::~GMTokenPort
~GMTokenPort()
Definition: compute_unit.hh:496
gem5::WFBarrier::reset
void reset()
Reset the barrier.
Definition: compute_unit.hh:180
gem5::ComputeUnit::ComputeUnitStats::vpc_f32
statistics::Formula vpc_f32
Definition: compute_unit.hh:1065
gem5::WFBarrier::incNumAtBarrier
void incNumAtBarrier()
Mark that a WF has reached the barrier.
Definition: compute_unit.hh:136
std::list< AddrRange >
gem5::WFBarrier::maxBarrierCnt
int maxBarrierCnt() const
Definition: compute_unit.hh:117
gem5::ComputeUnit::sendToLds
GEM5_NO_DISCARD bool sendToLds(GPUDynInstPtr gpuDynInst)
send a general request to the LDS make sure to look at the return value here as your request might be...
Definition: compute_unit.cc:1995
gem5::ComputeUnit::ComputeUnitStats::dynamicLMemInstrCnt
statistics::Scalar dynamicLMemInstrCnt
Definition: compute_unit.hh:1028
gem5::RequestPort::owner
SimObject & owner
Definition: port.hh:86
gem5::ComputeUnit::ComputeUnitStats::numFailedCASOps
statistics::Scalar numFailedCASOps
Definition: compute_unit.hh:1078
gem5::ComputeUnit::ITLBPort::stalled
bool stalled
Definition: compute_unit.hh:751
gem5::ComputeUnit::scalarMemoryPipe
ScalarMemPipeline scalarMemoryPipe
Definition: compute_unit.hh:288
gem5::ComputeUnit::ITLBPort::recvFunctional
virtual void recvFunctional(PacketPtr pkt)
Definition: compute_unit.hh:755
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ComputeUnit::DataPort::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Definition: compute_unit.cc:803
gem5::ComputeUnit::vectorGlobalMemUnit
WaitClass vectorGlobalMemUnit
Definition: compute_unit.hh:227
gem5::ComputeUnit::simdUnitWidth
int simdUnitWidth() const
Definition: compute_unit.hh:390
gem5::ComputeUnit::ComputeUnitStats::readonlyMemInsts
statistics::Formula readonlyMemInsts
Definition: compute_unit.hh:1002
gem5::ComputeUnit::ScalarDataPort::recvReqRetry
void recvReqRetry() override
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: compute_unit.cc:942
gem5::ComputeUnit::ComputeUnitStats::scalarMemReads
statistics::Scalar scalarMemReads
Definition: compute_unit.hh:969
gem5::ComputeUnit::ComputeUnitStats::totalCycles
statistics::Scalar totalCycles
Definition: compute_unit.hh:1062
gem5::ComputeUnit::dispWorkgroup
void dispWorkgroup(HSAQueueEntry *task, int num_wfs_in_wg)
Definition: compute_unit.cc:422
gem5::ComputeUnit::prefetchType
enums::PrefetchType prefetchType
Definition: compute_unit.hh:340
exec_stage.hh
gem5::ComputeUnit::ComputeUnitStats::tlbCycles
statistics::Scalar tlbCycles
Definition: compute_unit.hh:1012
gem5::ComputeUnit::mapWaveToScalarAluGlobalIdx
int mapWaveToScalarAluGlobalIdx(Wavefront *w) const
Definition: compute_unit.cc:266
gem5::ComputeUnit::gmTokenPort
GMTokenPort gmTokenPort
Definition: compute_unit.hh:507
gem5::ComputeUnit::getPort
Port & getPort(const std::string &if_name, PortID idx) override
Get a port with a given name and index.
Definition: compute_unit.hh:860
gem5::ComputeUnit::scalarPipeStages
int scalarPipeStages
Definition: compute_unit.hh:311
gem5::ComputeUnit::DataPort::recvReqRetry
virtual void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: compute_unit.cc:954
gem5::ComputeUnit::DTLBPort::stalled
bool stalled
Definition: compute_unit.hh:684
gem5::ComputeUnit::doInvalidate
void doInvalidate(RequestPtr req, int kernId)
trigger invalidate operation in the cu
Definition: compute_unit.cc:385
gem5::ComputeUnit::sqcPort
SQCPort sqcPort
Definition: compute_unit.hh:855
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statistics::Scalar spillReads
Definition: compute_unit.hh:991
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Definition: compute_unit.hh:724
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Definition: compute_unit.cc:656
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std::vector< int > numWfsToSched
Number of WFs to schedule to each SIMD.
Definition: compute_unit.hh:366
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statistics::Formula ldsNoFlatInstsPerWF
Definition: compute_unit.hh:958
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Definition: lds_state.hh:122
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SenderState(GPUDynInstPtr gpuDynInst)
Definition: compute_unit.hh:703
gem5::ComputeUnit::srf_scm_bus_latency
Cycles srf_scm_bus_latency
Definition: compute_unit.hh:320
callback.hh
gem5::ComputeUnit::ScalarDataPort
Definition: compute_unit.hh:558
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Definition: compute_unit.hh:1048
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Definition: compute_unit.hh:518
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Definition: named.hh:41
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Definition: compute_unit.hh:649
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Definition: compute_unit.hh:569
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Definition: compute_unit.hh:284
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Definition: compute_unit.hh:887
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Definition: compute_unit.hh:571
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Definition: compute_unit.cc:1565
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Definition: compute_unit.hh:462
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Definition: types.hh:84
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statistics::Formula scalarMemInstsPerKiloInst
Definition: compute_unit.hh:977
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Definition: compute_unit.hh:973
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Definition: token_port.hh:46
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Definition: compute_unit.cc:233
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Definition: compute_unit.hh:223

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