gem5  v21.2.0.0
compute_unit.hh
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31 
32 #ifndef __COMPUTE_UNIT_HH__
33 #define __COMPUTE_UNIT_HH__
34 
35 #include <deque>
36 #include <map>
37 #include <unordered_set>
38 #include <vector>
39 
40 #include "base/callback.hh"
41 #include "base/compiler.hh"
42 #include "base/statistics.hh"
43 #include "base/stats/group.hh"
44 #include "base/types.hh"
45 #include "config/the_gpu_isa.hh"
46 #include "enums/PrefetchType.hh"
47 #include "gpu-compute/comm.hh"
57 #include "mem/port.hh"
58 #include "mem/token_port.hh"
59 #include "sim/clocked_object.hh"
60 
61 namespace gem5
62 {
63 
64 class HSAQueueEntry;
65 class LdsChunk;
66 class ScalarRegisterFile;
67 class Shader;
68 class VectorRegisterFile;
69 
70 struct ComputeUnitParams;
71 
73 {
74  OLDEST = 0,
76 };
77 
79 {
84 };
85 
90 class WFBarrier
91 {
92  public:
94  {
95  }
96 
97  static const int InvalidID = -1;
98 
99  int
100  numAtBarrier() const
101  {
102  return _numAtBarrier;
103  }
104 
108  int
110  {
111  return _maxBarrierCnt - _numAtBarrier;
112  }
113 
114  int
116  {
117  return _maxBarrierCnt;
118  }
119 
124  void
125  setMaxBarrierCnt(int max_barrier_cnt)
126  {
127  _maxBarrierCnt = max_barrier_cnt;
128  }
129 
133  void
135  {
136  assert(_numAtBarrier < _maxBarrierCnt);
137  ++_numAtBarrier;
138  }
139 
145  bool
146  allAtBarrier() const
147  {
148  return _numAtBarrier == _maxBarrierCnt;
149  }
150 
155  void
157  {
158  assert(_maxBarrierCnt > 0);
159  --_maxBarrierCnt;
160  }
161 
166  void
168  {
169  _numAtBarrier = 0;
170  _maxBarrierCnt = 0;
171  }
172 
177  void
179  {
180  _numAtBarrier = 0;
181  }
182 
183  private:
190 
199 };
200 
202 {
203  public:
204 
205 
206  // Execution resources
207  //
208  // The ordering of units is:
209  // Vector ALUs
210  // Scalar ALUs
211  // GM Pipe
212  // LM Pipe
213  // Scalar Mem Pipe
214  //
215  // Note: the ordering of units is important and the code assumes the
216  // above ordering. However, there may be more than one resource of
217  // each type (e.g., 4 VALUs or 2 SALUs)
218 
220  // Resource control for global memory to VRF data/address bus
222  // Resource control for Vector Register File->Global Memory pipe buses
224  // Resource control for Vector Global Memory execution unit
226 
228  // Resource control for local memory to VRF data/address bus
230  // Resource control for Vector Register File->Local Memory pipe buses
232  // Resource control for Vector Shared/Local Memory execution unit
234 
236  // Resource control for scalar memory to SRF data/address bus
238  // Resource control for Scalar Register File->Scalar Memory pipe buses
240  // Resource control for Scalar Memory execution unit
242 
243  // vector ALU execution resources
246 
247  // scalar ALU execution resources
250 
251  // Return total number of execution units on this CU
252  int numExeUnits() const;
253  // index into readyList of the first memory unit
254  int firstMemUnit() const;
255  // index into readyList of the last memory unit
256  int lastMemUnit() const;
257  // index into scalarALUs vector of SALU used by the wavefront
258  int mapWaveToScalarAlu(Wavefront *w) const;
259  // index into readyList of SALU used by wavefront
261  // index into readyList of Global Memory unit used by wavefront
262  int mapWaveToGlobalMem(Wavefront *w) const;
263  // index into readyList of Local Memory unit used by wavefront
264  int mapWaveToLocalMem(Wavefront *w) const;
265  // index into readyList of Scalar Memory unit used by wavefront
266  int mapWaveToScalarMem(Wavefront *w) const;
267 
268  int vrfToCoalescerBusWidth; // VRF->Coalescer data bus width in bytes
269  int coalescerToVrfBusWidth; // Coalescer->VRF data bus width in bytes
270  int numCyclesPerStoreTransfer; // number of cycles per vector store
271  int numCyclesPerLoadTransfer; // number of cycles per vector load
272 
273  // track presence of dynamic instructions in the Schedule pipeline
274  // stage. This is used to check the readiness of the oldest,
275  // non-dispatched instruction of every WF in the Scoreboard stage.
276  std::unordered_set<uint64_t> pipeMap;
277 
279 
287 
289 
290  typedef ComputeUnitParams Params;
292  int cu_id;
293 
294  // array of vector register files, one per SIMD
296  // array of scalar register files, one per SIMD
298 
299  // Width per VALU/SIMD unit: number of work items that can be executed
300  // on the vector ALU simultaneously in a SIMD unit
302  // number of pipe stages for bypassing data to next dependent single
303  // precision vector instruction inside the vector ALU pipeline
305  // number of pipe stages for bypassing data to next dependent double
306  // precision vector instruction inside the vector ALU pipeline
308  // number of pipe stages for scalar ALU
310  // number of pipe stages for operand collection & distribution network
312  // number of cycles per instruction issue period
314 
315  // VRF to GM Bus latency
317  // SRF to Scalar Mem Bus latency
319  // VRF to LM Bus latency
321 
322  // tracks the last cycle a vector instruction was executed on a SIMD
324 
325  // tracks the number of dyn inst executed per SIMD
327 
328  // true if we allow a separate TLB per lane
330  // if 0, TLB prefetching is off.
332  // if fixed-stride prefetching, this is the stride.
334 
338  enums::PrefetchType prefetchType;
340 
342  // Idle CU timeout in ticks
344  int idleWfs;
347 
348  /*
349  * for Counting page accesses
350  */
352 
354 
357 
365 
366  // number of currently reserved vector registers per SIMD unit
368  // number of currently reserved scalar registers per SIMD unit
370  // number of vector registers per SIMD unit
372  // number of available scalar registers per SIMD unit
374 
375  // this hash map will keep track of page divergence
376  // per memory instruction per wavefront. The hash map
377  // is cleared in GPUDynInst::updateStats() in gpu_dyn_inst.cc.
378  std::map<Addr, int> pagesTouched;
379 
380  void insertInPipeMap(Wavefront *w);
382 
383  ComputeUnit(const Params &p);
384  ~ComputeUnit();
385 
386  // Timing Functions
387  int oprNetPipeLength() const { return operandNetworkLength; }
388  int simdUnitWidth() const { return simdWidth; }
389  int spBypassLength() const { return spBypassPipeLength; }
390  int dpBypassLength() const { return dpBypassPipeLength; }
391  int scalarPipeLength() const { return scalarPipeStages; }
393  int loadBusLength() const { return numCyclesPerLoadTransfer; }
394  int wfSize() const { return wavefrontSize; }
395 
396  void exec();
397  void initiateFetch(Wavefront *wavefront);
398  void fetch(PacketPtr pkt, Wavefront *wavefront);
400 
401  void startWavefront(Wavefront *w, int waveId, LdsChunk *ldsChunk,
402  HSAQueueEntry *task, int bar_id,
403  bool fetchContext=false);
404 
405  void doInvalidate(RequestPtr req, int kernId);
406  void doFlush(GPUDynInstPtr gpuDynInst);
407 
408  void dispWorkgroup(HSAQueueEntry *task, int num_wfs_in_wg);
409  bool hasDispResources(HSAQueueEntry *task, int &num_wfs_in_wg);
410 
411  int cacheLineSize() const { return _cacheLineSize; }
412  int getCacheLineBits() const { return cacheLineBits; }
413 
414  void resetRegisterPool();
415 
416  private:
417  WFBarrier&
418  barrierSlot(int bar_id)
419  {
420  assert(bar_id > WFBarrier::InvalidID);
421  return wfBarrierSlots.at(bar_id);
422  }
423 
424  int
426  {
427  assert(freeBarrierIds.size());
428  auto free_bar_id = freeBarrierIds.begin();
429  int bar_id = *free_bar_id;
430  freeBarrierIds.erase(free_bar_id);
431  return bar_id;
432  }
433 
434  public:
435  int numYetToReachBarrier(int bar_id);
436  bool allAtBarrier(int bar_id);
437  void incNumAtBarrier(int bar_id);
438  int numAtBarrier(int bar_id);
439  int maxBarrierCnt(int bar_id);
440  void resetBarrier(int bar_id);
441  void decMaxBarrierCnt(int bar_id);
442  void releaseBarrier(int bar_id);
443  void releaseWFsFromBarrier(int bar_id);
444  int numBarrierSlots() const { return _numBarrierSlots; }
445 
446  template<typename c0, typename c1>
447  void doSmReturn(GPUDynInstPtr gpuDynInst);
448 
449  virtual void init() override;
450  void sendRequest(GPUDynInstPtr gpuDynInst, PortID index, PacketPtr pkt);
451  void sendScalarRequest(GPUDynInstPtr gpuDynInst, PacketPtr pkt);
452  void injectGlobalMemFence(GPUDynInstPtr gpuDynInst,
453  bool kernelMemSync,
454  RequestPtr req=nullptr);
455  void handleMemPacket(PacketPtr pkt, int memport_index);
456  bool processTimingPacket(PacketPtr pkt);
457  void processFetchReturn(PacketPtr pkt);
459 
461 
462  bool isDone() const;
463  bool isVectorAluIdle(uint32_t simdId) const;
464 
465  protected:
467 
469 
470  public:
471  LdsState &
472  getLds() const
473  {
474  return lds;
475  }
476 
477  int32_t
478  getRefCounter(const uint32_t dispatchId, const uint32_t wgId) const;
479 
480  [[nodiscard]] bool sendToLds(GPUDynInstPtr gpuDynInst);
481 
482  typedef std::unordered_map<Addr, std::pair<int, int>> pageDataStruct;
484 
485  void exitCallback();
486 
488  {
489  public:
490  GMTokenPort(const std::string& name, SimObject *owner,
491  PortID id = InvalidPortID)
493  { }
495 
496  protected:
497  bool recvTimingResp(PacketPtr) { return false; }
498  void recvReqRetry() { }
499  };
500 
501  // Manager for the number of tokens available to this compute unit to
502  // send global memory request packets to the coalescer this is only used
503  // between global memory pipe and TCP coalescer.
506 
508  class DataPort : public RequestPort
509  {
510  public:
511  DataPort(const std::string &_name, ComputeUnit *_cu, PortID id)
512  : RequestPort(_name, _cu, id), computeUnit(_cu) { }
513 
515 
517  {
521 
522  SenderState(GPUDynInstPtr gpuDynInst, PortID _port_index,
523  Packet::SenderState *sender_state=nullptr)
524  : _gpuDynInst(gpuDynInst),
525  port_index(_port_index),
526  saved(sender_state) { }
527  };
528 
529  void processMemReqEvent(PacketPtr pkt);
531 
532  void processMemRespEvent(PacketPtr pkt);
534 
536 
537  protected:
539 
540  virtual bool recvTimingResp(PacketPtr pkt);
541  virtual Tick recvAtomic(PacketPtr pkt) { return 0; }
542  virtual void recvFunctional(PacketPtr pkt) { }
543  virtual void recvRangeChange() { }
544  virtual void recvReqRetry();
545 
546  virtual void
548  {
549  resp.clear();
550  snoop = true;
551  }
552 
553  };
554 
555  // Scalar data cache access port
557  {
558  public:
559  ScalarDataPort(const std::string &_name, ComputeUnit *_cu)
560  : RequestPort(_name, _cu), computeUnit(_cu)
561  {
562  }
563 
564  bool recvTimingResp(PacketPtr pkt) override;
565  void recvReqRetry() override;
566 
568  {
570  Packet::SenderState *sender_state=nullptr)
571  : _gpuDynInst(gpuDynInst), saved(sender_state)
572  {
573  }
574 
577  };
578 
579  class MemReqEvent : public Event
580  {
581  private:
584 
585  public:
586  MemReqEvent(ScalarDataPort &_scalar_data_port, PacketPtr _pkt)
587  : Event(), scalarDataPort(_scalar_data_port), pkt(_pkt)
588  {
590  }
591 
592  void process();
593  const char *description() const;
594  };
595 
597 
598  private:
600  };
601 
602  // Instruction cache access port
603  class SQCPort : public RequestPort
604  {
605  public:
606  SQCPort(const std::string &_name, ComputeUnit *_cu)
607  : RequestPort(_name, _cu), computeUnit(_cu) { }
608 
610 
612  {
615  // kernel id to be used in handling I-Cache invalidate response
616  int kernId;
617 
619  *sender_state=nullptr, int _kernId=-1)
620  : wavefront(_wavefront), saved(sender_state),
621  kernId(_kernId){ }
622  };
623 
625 
626  protected:
628 
629  virtual bool recvTimingResp(PacketPtr pkt);
630  virtual Tick recvAtomic(PacketPtr pkt) { return 0; }
631  virtual void recvFunctional(PacketPtr pkt) { }
632  virtual void recvRangeChange() { }
633  virtual void recvReqRetry();
634 
635  virtual void
637  {
638  resp.clear();
639  snoop = true;
640  }
641  };
642 
644  class DTLBPort : public RequestPort
645  {
646  public:
647  DTLBPort(const std::string &_name, ComputeUnit *_cu, PortID id)
648  : RequestPort(_name, _cu, id), computeUnit(_cu),
649  stalled(false)
650  { }
651 
652  bool isStalled() { return stalled; }
653  void stallPort() { stalled = true; }
654  void unstallPort() { stalled = false; }
655 
661 
666  {
667  // the memInst that this is associated with
669 
670  // the lane in the memInst this is associated with, so we send
671  // the memory request down the right port
673 
674  // constructor used for packets involved in timing accesses
675  SenderState(GPUDynInstPtr gpuDynInst, PortID port_index)
676  : _gpuDynInst(gpuDynInst), portIndex(port_index) { }
677 
678  };
679 
680  protected:
682  bool stalled;
683 
684  virtual bool recvTimingResp(PacketPtr pkt);
685  virtual Tick recvAtomic(PacketPtr pkt) { return 0; }
686  virtual void recvFunctional(PacketPtr pkt) { }
687  virtual void recvRangeChange() { }
688  virtual void recvReqRetry();
689  };
690 
692  {
693  public:
694  ScalarDTLBPort(const std::string &_name, ComputeUnit *_cu)
695  : RequestPort(_name, _cu), computeUnit(_cu), stalled(false)
696  {
697  }
698 
700  {
701  SenderState(GPUDynInstPtr gpuDynInst) : _gpuDynInst(gpuDynInst) { }
703  };
704 
705  bool recvTimingResp(PacketPtr pkt) override;
706  void recvReqRetry() override { assert(false); }
707 
708  bool isStalled() const { return stalled; }
709  void stallPort() { stalled = true; }
710  void unstallPort() { stalled = false; }
711 
713 
714  private:
716  bool stalled;
717  };
718 
719  class ITLBPort : public RequestPort
720  {
721  public:
722  ITLBPort(const std::string &_name, ComputeUnit *_cu)
723  : RequestPort(_name, _cu), computeUnit(_cu), stalled(false) { }
724 
725 
726  bool isStalled() { return stalled; }
727  void stallPort() { stalled = true; }
728  void unstallPort() { stalled = false; }
729 
735 
740  {
741  // The wavefront associated with this request
743 
744  SenderState(Wavefront *_wavefront) : wavefront(_wavefront) { }
745  };
746 
747  protected:
749  bool stalled;
750 
751  virtual bool recvTimingResp(PacketPtr pkt);
752  virtual Tick recvAtomic(PacketPtr pkt) { return 0; }
753  virtual void recvFunctional(PacketPtr pkt) { }
754  virtual void recvRangeChange() { }
755  virtual void recvReqRetry();
756  };
757 
761  class LDSPort : public RequestPort
762  {
763  public:
764  LDSPort(const std::string &_name, ComputeUnit *_cu)
765  : RequestPort(_name, _cu), computeUnit(_cu)
766  {
767  }
768 
769  bool isStalled() const { return stalled; }
770  void stallPort() { stalled = true; }
771  void unstallPort() { stalled = false; }
772 
777  std::queue<PacketPtr> retries;
778 
784  {
785  protected:
786  // The actual read/write/atomic request that goes with this command
788 
789  public:
791  _gpuDynInst(gpuDynInst)
792  {
793  }
794 
796  getMemInst() const
797  {
798  return _gpuDynInst;
799  }
800  };
801 
802  virtual bool
804 
805  protected:
806 
807  bool stalled = false;
808 
810 
811  virtual bool
813 
814  virtual Tick
815  recvAtomic(PacketPtr pkt) { return 0; }
816 
817  virtual void
819  {
820  }
821 
822  virtual void
824  {
825  }
826 
827  virtual void
828  recvReqRetry();
829  };
830 
835 
836  TokenManager *
838  {
839  return memPortTokens;
840  }
841 
846  // port to the TLB hierarchy (i.e., the L1 TLB)
848  // port to the scalar data cache
850  // port to the scalar data TLB
852  // port to the SQC (i.e. the I-cache)
854  // port to the SQC TLB (there's a separate TLB for each I-cache)
856 
857  Port &
858  getPort(const std::string &if_name, PortID idx) override
859  {
860  if (if_name == "memory_port" && idx < memPort.size()) {
861  return memPort[idx];
862  } else if (if_name == "translation_port" && idx < tlbPort.size()) {
863  return tlbPort[idx];
864  } else if (if_name == "scalar_port") {
865  return scalarDataPort;
866  } else if (if_name == "scalar_tlb_port") {
867  return scalarDTLBPort;
868  } else if (if_name == "sqc_port") {
869  return sqcPort;
870  } else if (if_name == "sqc_tlb_port") {
871  return sqcTLBPort;
872  } else if (if_name == "ldsPort") {
873  return ldsPort;
874  } else if (if_name == "gmTokenPort") {
875  return gmTokenPort;
876  } else {
877  return ClockedObject::getPort(if_name, idx);
878  }
879  }
880 
882 
883  private:
884  const int _cacheLineSize;
885  const int _numBarrierSlots;
889 
924 
932  std::unordered_set<int> freeBarrierIds;
933 
934  // hold the time of the arrival of the first cache block related to
935  // a particular GPUDynInst. This is used to calculate the difference
936  // between the first and last chace block arrival times.
937  std::unordered_map<GPUDynInstPtr, Tick> headTailMap;
938 
939  public:
940  void updateInstStats(GPUDynInstPtr gpuDynInst);
942 
944  {
945  ComputeUnitStats(statistics::Group *parent, int n_wf);
946 
969 
976 
977  // Cycles required to send register source (addr and data) from
978  // register files to memory pipeline, per SIMD.
982 
1004 
1006 
1007  // the following stats compute the avg. TLB accesslatency per
1008  // uncoalesced request (only for data)
1012  // hitsPerTLBLevel[x] are the hits in Level x TLB.
1013  // x = 0 is the page table.
1015 
1018 
1019  // over all memory instructions executed over all wavefronts
1020  // how many touched 0-4 pages, 4-8, ..., 60-64 pages
1022  // count of non-flat global memory vector instructions executed
1024  // count of flat global memory vector instructions executed
1027 
1030  // Number of instructions executed, i.e. if 64 (or 32 or 7) lanes are
1031  // active when the instruction is committed, this number is still
1032  // incremented by 1
1034  // Number of cycles among successive instruction executions across all
1035  // wavefronts of the same CU
1037  // number of individual vector operations executed
1039  // number of individual f16 vector operations executed
1041  // number of individual f32 vector operations executed
1043  // number of individual f64 vector operations executed
1045  // number of individual FMA 16,32,64 vector operations executed
1049  // number of individual MAC 16,32,64 vector operations executed
1053  // number of individual MAD 16,32,64 vector operations executed
1057  // total number of two op FP vector operations executed
1059  // Total cycles that something is running on the GPU
1061  statistics::Formula vpc; // vector ops per cycle
1062  statistics::Formula vpc_f16; // vector ops per cycle
1063  statistics::Formula vpc_f32; // vector ops per cycle
1064  statistics::Formula vpc_f64; // vector ops per cycle
1065  statistics::Formula ipc; // vector instructions per cycle
1069  // number of vector ALU instructions received
1071  // number of times a WG cannot start due to lack of free VGPRs in SIMDs
1073  // number of times a WG cannot start due to lack of free SGPRs in SIMDs
1079 
1080  // distrubtion in latency difference between first and last cache block
1081  // arrival ticks
1083 
1084  // Track the amount of interleaving between wavefronts on each SIMD.
1085  // This stat is sampled using instExecPerSimd to compute the number
1086  // of instructions that have been executed on a SIMD between a WF
1087  // executing two successive instructions.
1089  } stats;
1090 };
1091 
1092 } // namespace gem5
1093 
1094 #endif // __COMPUTE_UNIT_HH__
gem5::ComputeUnit::SQCPort::SenderState
Definition: compute_unit.hh:611
gem5::ComputeUnit::ComputeUnitStats::tlbRequests
statistics::Scalar tlbRequests
Definition: compute_unit.hh:1009
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1930
gem5::ComputeUnit::GMTokenPort::recvTimingResp
bool recvTimingResp(PacketPtr)
Receive a timing response from the peer.
Definition: compute_unit.hh:497
gem5::ComputeUnit::GMTokenPort::GMTokenPort
GMTokenPort(const std::string &name, SimObject *owner, PortID id=InvalidPortID)
Definition: compute_unit.hh:490
gem5::ComputeUnit::ComputeUnitStats::sALUInstsPerWF
statistics::Formula sALUInstsPerWF
Definition: compute_unit.hh:950
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::ComputeUnit::ComputeUnitStats::vALUUtilization
statistics::Formula vALUUtilization
Definition: compute_unit.hh:954
gem5::ComputeUnit::getAndIncSeqNum
InstSeqNum getAndIncSeqNum()
Definition: compute_unit.hh:881
gem5::ComputeUnit::ScalarDTLBPort
Definition: compute_unit.hh:691
gem5::SimObject::getPort
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Definition: sim_object.cc:126
hsa_queue_entry.hh
gem5::ComputeUnit::ScalarDataPort::SenderState::saved
Packet::SenderState * saved
Definition: compute_unit.hh:576
gem5::ComputeUnit::wfList
std::vector< std::vector< Wavefront * > > wfList
Definition: compute_unit.hh:291
gem5::ComputeUnit::ComputeUnit
ComputeUnit(const Params &p)
Definition: compute_unit.cc:64
gem5::ScoreboardCheckStage
Definition: scoreboard_check_stage.hh:61
gem5::ComputeUnit::ComputeUnitStats::scalarMemReadsPerWF
statistics::Formula scalarMemReadsPerWF
Definition: compute_unit.hh:968
gem5::ComputeUnit::wfBarrierSlots
std::vector< WFBarrier > wfBarrierSlots
The barrier slots for this CU.
Definition: compute_unit.hh:928
gem5::ComputeUnit::doSmReturn
void doSmReturn(GPUDynInstPtr gpuDynInst)
gem5::ComputeUnit::ComputeUnitStats::instCyclesSALU
statistics::Scalar instCyclesSALU
Definition: compute_unit.hh:952
gem5::ComputeUnit::scoreboardCheckToSchedule
ScoreboardCheckToSchedule scoreboardCheckToSchedule
TODO: Update these comments once the pipe stage interface has been fully refactored.
Definition: compute_unit.hh:922
gem5::ComputeUnit::fetchStage
FetchStage fetchStage
Definition: compute_unit.hh:280
gem5::ComputeUnit::ComputeUnitStats::instInterleave
statistics::VectorDistribution instInterleave
Definition: compute_unit.hh:1088
gem5::ComputeUnit::ComputeUnitStats::flatVMemInsts
statistics::Scalar flatVMemInsts
Definition: compute_unit.hh:957
gem5::Port::name
const std::string name() const
Return port name (for DPRINTF).
Definition: port.hh:111
gem5::ComputeUnit::ComputeUnitStats::numVecOpsExecutedTwoOpFP
statistics::Scalar numVecOpsExecutedTwoOpFP
Definition: compute_unit.hh:1058
gem5::ComputeUnit::ScalarDTLBPort::retries
std::deque< PacketPtr > retries
Definition: compute_unit.hh:712
gem5::ComputeUnit::sendRequest
void sendRequest(GPUDynInstPtr gpuDynInst, PortID index, PacketPtr pkt)
Definition: compute_unit.cc:1009
gem5::MipsISA::w
Bitfield< 0 > w
Definition: pra_constants.hh:281
gem5::statistics::Distribution
A simple distribution stat.
Definition: statistics.hh:2084
gem5::ComputeUnit::coalescerToVrfBusWidth
int coalescerToVrfBusWidth
Definition: compute_unit.hh:269
gem5::ComputeUnit::lastExecCycle
std::vector< uint64_t > lastExecCycle
Definition: compute_unit.hh:323
gem5::ComputeUnit::globalSeqNum
InstSeqNum globalSeqNum
Definition: compute_unit.hh:887
gem5::ComputeUnit::debugSegFault
bool debugSegFault
Definition: compute_unit.hh:341
gem5::ComputeUnit::DTLBPort::recvRangeChange
virtual void recvRangeChange()
Called to receive an address range change from the peer response port.
Definition: compute_unit.hh:687
gem5::ComputeUnit::ITLBPort::isStalled
bool isStalled()
Definition: compute_unit.hh:726
gem5::ComputeUnit::DataPort::processMemReqEvent
void processMemReqEvent(PacketPtr pkt)
Definition: compute_unit.cc:1571
gem5::ComputeUnit::localMemoryPipe
LocalMemPipeline localMemoryPipe
Definition: compute_unit.hh:285
gem5::ComputeUnit::ComputeUnitStats::privWrites
statistics::Scalar privWrites
Definition: compute_unit.hh:996
gem5::ComputeUnit::ComputeUnitStats::kernargWrites
statistics::Scalar kernargWrites
Definition: compute_unit.hh:1002
fetch_stage.hh
gem5::ComputeUnit::numVecRegsPerSimd
int numVecRegsPerSimd
Definition: compute_unit.hh:371
gem5::ComputeUnit::DataPort::SenderState::SenderState
SenderState(GPUDynInstPtr gpuDynInst, PortID _port_index, Packet::SenderState *sender_state=nullptr)
Definition: compute_unit.hh:522
gem5::ComputeUnit::DTLBPort
Data TLB port.
Definition: compute_unit.hh:644
group.hh
comm.hh
gem5::ComputeUnit::srf
std::vector< ScalarRegisterFile * > srf
Definition: compute_unit.hh:297
gem5::WFBarrier::numYetToReachBarrier
int numYetToReachBarrier() const
Number of WFs that have not yet reached the barrier.
Definition: compute_unit.hh:109
gem5::ComputeUnit::ComputeUnitStats::scalarMemWritesPerWF
statistics::Formula scalarMemWritesPerWF
Definition: compute_unit.hh:966
gem5::ComputeUnit::LDSPort::SenderState::SenderState
SenderState(GPUDynInstPtr gpuDynInst)
Definition: compute_unit.hh:790
gem5::ComputeUnit::ComputeUnitStats::argMemInsts
statistics::Formula argMemInsts
Definition: compute_unit.hh:988
gem5::ComputeUnit::ITLBPort::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Definition: compute_unit.cc:1720
gem5::ComputeUnit::ComputeUnitStats::spillWrites
statistics::Scalar spillWrites
Definition: compute_unit.hh:990
gem5::ComputeUnit::exec_policy
EXEC_POLICY exec_policy
Definition: compute_unit.hh:339
gem5::ComputeUnit::ComputeUnitStats::spillMemInsts
statistics::Formula spillMemInsts
Definition: compute_unit.hh:991
gem5::ComputeUnit::ComputeUnitStats::scalarMemWritesPerKiloInst
statistics::Formula scalarMemWritesPerKiloInst
Definition: compute_unit.hh:974
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::ComputeUnit::ScalarDTLBPort::recvReqRetry
void recvReqRetry() override
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: compute_unit.hh:706
gem5::ComputeUnit::ComputeUnitStats::readonlyReads
statistics::Scalar readonlyReads
Definition: compute_unit.hh:998
gem5::ScheduleToExecute
Communication interface between Schedule and Execute stages.
Definition: comm.hh:98
gem5::ComputeUnit::LDSPort::SenderState
SenderState is information carried along with the packet, esp.
Definition: compute_unit.hh:783
gem5::ComputeUnit::ComputeUnitStats::wgBlockedDueBarrierAllocation
statistics::Scalar wgBlockedDueBarrierAllocation
Definition: compute_unit.hh:1028
gem5::TLB_MISS_CACHE_HIT
@ TLB_MISS_CACHE_HIT
Definition: compute_unit.hh:81
gem5::ComputeUnit::DataPort::snoopRangeSent
bool snoopRangeSent
Definition: compute_unit.hh:514
gem5::ComputeUnit::DTLBPort::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Definition: compute_unit.cc:1387
global_memory_pipeline.hh
gem5::ComputeUnit::ComputeUnitStats::completedWGs
statistics::Scalar completedWGs
Definition: compute_unit.hh:1078
gem5::ComputeUnit::DTLBPort::stallPort
void stallPort()
Definition: compute_unit.hh:653
gem5::ComputeUnit::ComputeUnitStats::vectorMemReads
statistics::Scalar vectorMemReads
Definition: compute_unit.hh:963
gem5::ComputeUnit::DTLBPort::recvFunctional
virtual void recvFunctional(PacketPtr pkt)
Definition: compute_unit.hh:686
gem5::ComputeUnit::lastVaddrSimd
std::vector< std::vector< Addr > > lastVaddrSimd
Definition: compute_unit.hh:336
gem5::ComputeUnit::simdWidth
int simdWidth
Definition: compute_unit.hh:301
gem5::Wavefront
Definition: wavefront.hh:60
gem5::ComputeUnit::ScalarDTLBPort::isStalled
bool isStalled() const
Definition: compute_unit.hh:708
gem5::ComputeUnit::ComputeUnitStats::numVecOpsExecutedF64
statistics::Scalar numVecOpsExecutedF64
Definition: compute_unit.hh:1044
gem5::ComputeUnit::fetch
void fetch(PacketPtr pkt, Wavefront *wavefront)
gem5::TokenManager
Definition: token_port.hh:130
gem5::ComputeUnit::GMTokenPort::recvReqRetry
void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: compute_unit.hh:498
gem5::ComputeUnit::ComputeUnitStats::dynamicGMemInstrCnt
statistics::Scalar dynamicGMemInstrCnt
Definition: compute_unit.hh:1023
gem5::HSAQueueEntry
Definition: hsa_queue_entry.hh:59
gem5::ComputeUnit::numCyclesPerStoreTransfer
int numCyclesPerStoreTransfer
Definition: compute_unit.hh:270
gem5::ComputeUnit::DTLBPort::isStalled
bool isStalled()
Definition: compute_unit.hh:652
gem5::ComputeUnit::firstMemUnit
int firstMemUnit() const
Definition: compute_unit.cc:239
gem5::ComputeUnit::numCyclesPerLoadTransfer
int numCyclesPerLoadTransfer
Definition: compute_unit.hh:271
gem5::Port::id
const PortID id
A numeric identifier to distinguish ports in a vector, and set to InvalidPortID in case this port is ...
Definition: port.hh:79
gem5::ComputeUnit::ITLBPort::retries
std::deque< PacketPtr > retries
here we queue all the translation requests that were not successfully sent.
Definition: compute_unit.hh:734
gem5::ComputeUnit::pagesTouched
std::map< Addr, int > pagesTouched
Definition: compute_unit.hh:378
gem5::ComputeUnit::DataPort::recvAtomic
virtual Tick recvAtomic(PacketPtr pkt)
Definition: compute_unit.hh:541
gem5::ComputeUnit::ScalarDataPort::MemReqEvent::pkt
PacketPtr pkt
Definition: compute_unit.hh:583
gem5::ComputeUnit::LDSPort::stalled
bool stalled
whether or not it is stalled
Definition: compute_unit.hh:807
gem5::ComputeUnit::scoreboardCheckStage
ScoreboardCheckStage scoreboardCheckStage
Definition: compute_unit.hh:281
gem5::ComputeUnit::stats
gem5::ComputeUnit::ComputeUnitStats stats
gem5::ComputeUnit::DTLBPort::computeUnit
ComputeUnit * computeUnit
Definition: compute_unit.hh:681
gem5::ComputeUnit::headTailMap
std::unordered_map< GPUDynInstPtr, Tick > headTailMap
Definition: compute_unit.hh:937
gem5::ComputeUnit::ComputeUnitStats::vpc_f16
statistics::Formula vpc_f16
Definition: compute_unit.hh:1062
gem5::ComputeUnit::ComputeUnitStats::tlbLatency
statistics::Formula tlbLatency
Definition: compute_unit.hh:1011
gem5::ComputeUnit::_requestorId
RequestorID _requestorId
Definition: compute_unit.hh:466
gem5::ComputeUnit::DataPort::processMemRespEvent
void processMemRespEvent(PacketPtr pkt)
Definition: compute_unit.cc:1307
gem5::ComputeUnit::lastVaddrCU
std::vector< Addr > lastVaddrCU
Definition: compute_unit.hh:335
gem5::WFBarrier::release
void release()
Release this barrier resource so it can be used by other WGs.
Definition: compute_unit.hh:167
gem5::ComputeUnit::ScalarDTLBPort::recvTimingResp
bool recvTimingResp(PacketPtr pkt) override
Receive a timing response from the peer.
Definition: compute_unit.cc:1660
gem5::ComputeUnit::resp_tick_latency
Tick resp_tick_latency
Definition: compute_unit.hh:356
gem5::ComputeUnit::ComputeUnitStats::sALUInsts
statistics::Scalar sALUInsts
Definition: compute_unit.hh:949
gem5::ComputeUnit::exec
void exec()
Definition: compute_unit.cc:719
gem5::ExecStage
Definition: exec_stage.hh:73
gem5::ComputeUnit::DTLBPort::SenderState::SenderState
SenderState(GPUDynInstPtr gpuDynInst, PortID port_index)
Definition: compute_unit.hh:675
gem5::ComputeUnit::SQCPort::SenderState::wavefront
Wavefront * wavefront
Definition: compute_unit.hh:613
gem5::ComputeUnit::srfToScalarMemPipeBus
WaitClass srfToScalarMemPipeBus
Definition: compute_unit.hh:239
gem5::ComputeUnit::releaseBarrier
void releaseBarrier(int bar_id)
Definition: compute_unit.cc:696
scoreboard_check_stage.hh
gem5::ComputeUnit::ComputeUnitStats::instCyclesScMemPerSimd
statistics::Vector instCyclesScMemPerSimd
Definition: compute_unit.hh:980
gem5::WFBarrier::_maxBarrierCnt
int _maxBarrierCnt
The maximum number of WFs that can reach this barrier.
Definition: compute_unit.hh:198
gem5::ComputeUnit::spBypassLength
int spBypassLength() const
Definition: compute_unit.hh:389
gem5::ComputeUnit::numYetToReachBarrier
int numYetToReachBarrier(int bar_id)
Definition: compute_unit.cc:647
gem5::statistics::Vector
A vector of scalar stats.
Definition: statistics.hh:2006
gem5::ComputeUnit::dpBypassPipeLength
int dpBypassPipeLength
Definition: compute_unit.hh:307
gem5::ComputeUnit::ComputeUnitStats::ldsBankConflictDist
statistics::Distribution ldsBankConflictDist
Definition: compute_unit.hh:1017
gem5::ComputeUnit::getRefCounter
int32_t getRefCounter(const uint32_t dispatchId, const uint32_t wgId) const
Definition: compute_unit.cc:1969
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2539
gem5::ComputeUnit::ITLBPort::SenderState::wavefront
Wavefront * wavefront
Definition: compute_unit.hh:742
std::vector
STL vector class.
Definition: stl.hh:37
gem5::ComputeUnit::LDSPort::recvAtomic
virtual Tick recvAtomic(PacketPtr pkt)
Definition: compute_unit.hh:815
gem5::ComputeUnit::scalarPipeLength
int scalarPipeLength() const
Definition: compute_unit.hh:391
gem5::ComputeUnit::ComputeUnitStats::kernargReads
statistics::Scalar kernargReads
Definition: compute_unit.hh:1001
gem5::ComputeUnit::prefetchDepth
int prefetchDepth
Definition: compute_unit.hh:331
gem5::ComputeUnit::ComputeUnitStats::numVecOpsExecutedFMA32
statistics::Scalar numVecOpsExecutedFMA32
Definition: compute_unit.hh:1047
gem5::ComputeUnit::vrfToGlobalMemPipeBus
WaitClass vrfToGlobalMemPipeBus
Definition: compute_unit.hh:223
gem5::ComputeUnit::ComputeUnitStats::ldsNoFlatInsts
statistics::Scalar ldsNoFlatInsts
Definition: compute_unit.hh:955
gem5::ComputeUnit::resetBarrier
void resetBarrier(int bar_id)
Definition: compute_unit.cc:682
gem5::ComputeUnit::SQCPort::computeUnit
ComputeUnit * computeUnit
Definition: compute_unit.hh:627
gem5::ComputeUnit::ComputeUnitStats::globalReads
statistics::Scalar globalReads
Definition: compute_unit.hh:983
gem5::ComputeUnit::storeBusLength
int storeBusLength() const
Definition: compute_unit.hh:392
gem5::ComputeUnit::SQCPort::retries
std::deque< std::pair< PacketPtr, Wavefront * > > retries
Definition: compute_unit.hh:624
gem5::ComputeUnit::ComputeUnitStats::groupMemInsts
statistics::Formula groupMemInsts
Definition: compute_unit.hh:994
gem5::ComputeUnit::ComputeUnitStats::vpc
statistics::Formula vpc
Definition: compute_unit.hh:1061
gem5::ComputeUnit::ComputeUnitStats::activeLanesPerLMemInstrDist
statistics::Distribution activeLanesPerLMemInstrDist
Definition: compute_unit.hh:1068
gem5::ComputeUnit::memPortTokens
TokenManager * memPortTokens
Definition: compute_unit.hh:504
gem5::WFBarrier::decMaxBarrierCnt
void decMaxBarrierCnt()
Decrement the number of WFs that are participating in this barrier.
Definition: compute_unit.hh:156
gem5::ComputeUnit::getLds
LdsState & getLds() const
Definition: compute_unit.hh:472
gem5::FetchStage
Definition: fetch_stage.hh:54
gem5::ScheduleStage
Definition: schedule_stage.hh:62
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::ComputeUnit::numVectorSharedMemUnits
int numVectorSharedMemUnits
Definition: compute_unit.hh:227
gem5::ComputeUnit::shader
Shader * shader
Definition: compute_unit.hh:353
gem5::ComputeUnit::req_tick_latency
Tick req_tick_latency
Definition: compute_unit.hh:355
gem5::ComputeUnit::ComputeUnitStats::vectorMemWritesPerWF
statistics::Formula vectorMemWritesPerWF
Definition: compute_unit.hh:962
gem5::ComputeUnit::ComputeUnitStats::numVecOpsExecutedMAD64
statistics::Scalar numVecOpsExecutedMAD64
Definition: compute_unit.hh:1056
gem5::ComputeUnit::issuePeriod
Cycles issuePeriod
Definition: compute_unit.hh:313
gem5::ComputeUnit::ComputeUnitStats::headTailLatency
statistics::Distribution headTailLatency
Definition: compute_unit.hh:1082
gem5::ComputeUnit::scalarDataPort
ScalarDataPort scalarDataPort
Definition: compute_unit.hh:849
gem5::ComputeUnit::ITLBPort::stallPort
void stallPort()
Definition: compute_unit.hh:727
gem5::ComputeUnit::ComputeUnitStats::threadCyclesVALU
statistics::Scalar threadCyclesVALU
Definition: compute_unit.hh:953
gem5::ComputeUnit::cu_id
int cu_id
Definition: compute_unit.hh:292
gem5::ComputeUnit::ComputeUnitStats::numVecOpsExecutedMAC32
statistics::Scalar numVecOpsExecutedMAC32
Definition: compute_unit.hh:1051
gem5::ComputeUnit::ComputeUnitStats::numVecOpsExecutedMAD32
statistics::Scalar numVecOpsExecutedMAD32
Definition: compute_unit.hh:1055
gem5::ComputeUnit::ComputeUnitStats::vectorMemReadsPerWF
statistics::Formula vectorMemReadsPerWF
Definition: compute_unit.hh:964
gem5::ComputeUnit::vrf
std::vector< VectorRegisterFile * > vrf
Definition: compute_unit.hh:295
gem5::ComputeUnit::ComputeUnitStats::instCyclesVMemPerSimd
statistics::Vector instCyclesVMemPerSimd
Definition: compute_unit.hh:979
gem5::ComputeUnit::ComputeUnitStats::dynamicFlatMemInstrCnt
statistics::Scalar dynamicFlatMemInstrCnt
Definition: compute_unit.hh:1025
gem5::Event::setFlags
void setFlags(Flags _flags)
Definition: eventq.hh:328
gem5::ComputeUnit::SQCPort::recvReqRetry
virtual void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: compute_unit.cc:986
gem5::ComputeUnit::ComputeUnitStats::groupReads
statistics::Scalar groupReads
Definition: compute_unit.hh:992
gem5::ComputeUnit::ComputeUnitStats::vpc_f64
statistics::Formula vpc_f64
Definition: compute_unit.hh:1064
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::ComputeUnit::injectGlobalMemFence
void injectGlobalMemFence(GPUDynInstPtr gpuDynInst, bool kernelMemSync, RequestPtr req=nullptr)
Definition: compute_unit.cc:1229
gem5::ComputeUnit::ScalarDataPort::computeUnit
ComputeUnit * computeUnit
Definition: compute_unit.hh:599
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::EventBase::AutoDelete
static const FlagsType AutoDelete
Definition: eventq.hh:107
gem5::ComputeUnit::LDSPort::sendTimingReq
virtual bool sendTimingReq(PacketPtr pkt)
attempt to send this packet, either the port is already stalled, the request is nack'd and must stall...
Definition: compute_unit.cc:2037
gem5::ComputeUnit::locMemToVrfBus
WaitClass locMemToVrfBus
Definition: compute_unit.hh:229
gem5::ComputeUnit::LDSPort::unstallPort
void unstallPort()
Definition: compute_unit.hh:771
gem5::ComputeUnit::idleWfs
int idleWfs
Definition: compute_unit.hh:344
gem5::ComputeUnit::ComputeUnitStats::kernargMemInsts
statistics::Formula kernargMemInsts
Definition: compute_unit.hh:1003
gem5::TLB_CACHE
TLB_CACHE
Definition: compute_unit.hh:78
gem5::ComputeUnit::ComputeUnitStats::flatVMemInstsPerWF
statistics::Formula flatVMemInstsPerWF
Definition: compute_unit.hh:958
gem5::ComputeUnit::SQCPort::recvRangeChange
virtual void recvRangeChange()
Called to receive an address range change from the peer response port.
Definition: compute_unit.hh:632
gem5::ComputeUnit::idleCUTimeout
Tick idleCUTimeout
Definition: compute_unit.hh:343
gem5::ComputeUnit::loadBusLength
int loadBusLength() const
Definition: compute_unit.hh:393
gem5::ComputeUnit::ComputeUnitStats
Definition: compute_unit.hh:943
gem5::ComputeUnit::numScalarMemUnits
int numScalarMemUnits
Definition: compute_unit.hh:235
gem5::ComputeUnit::DTLBPort::recvReqRetry
virtual void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: compute_unit.cc:1629
gem5::ComputeUnit::processTimingPacket
bool processTimingPacket(PacketPtr pkt)
gem5::ComputeUnit::ITLBPort::SenderState
SenderState is information carried along with the packet throughout the TLB hierarchy.
Definition: compute_unit.hh:739
gem5::ComputeUnit
Definition: compute_unit.hh:201
gem5::ComputeUnit::ScalarDataPort::MemReqEvent::process
void process()
Definition: compute_unit.cc:1600
gem5::ComputeUnit::pageAccesses
pageDataStruct pageAccesses
Definition: compute_unit.hh:483
gem5::ComputeUnit::ScalarDataPort::retries
std::deque< PacketPtr > retries
Definition: compute_unit.hh:596
gem5::ComputeUnit::ScalarDataPort::SenderState::_gpuDynInst
GPUDynInstPtr _gpuDynInst
Definition: compute_unit.hh:575
gem5::ComputeUnit::ComputeUnitStats::flatLDSInsts
statistics::Scalar flatLDSInsts
Definition: compute_unit.hh:959
gem5::ComputeUnit::numScalarALUs
int numScalarALUs
Definition: compute_unit.hh:248
gem5::ComputeUnit::numVectorALUs
int numVectorALUs
Definition: compute_unit.hh:244
gem5::ComputeUnit::DataPort::DataPort
DataPort(const std::string &_name, ComputeUnit *_cu, PortID id)
Definition: compute_unit.hh:511
gem5::ComputeUnit::wavefrontSize
int wavefrontSize
Definition: compute_unit.hh:888
gem5::ComputeUnit::startWavefront
void startWavefront(Wavefront *w, int waveId, LdsChunk *ldsChunk, HSAQueueEntry *task, int bar_id, bool fetchContext=false)
Definition: compute_unit.cc:309
gem5::ComputeUnit::sqcTLBPort
ITLBPort sqcTLBPort
Definition: compute_unit.hh:855
gem5::ComputeUnit::ComputeUnitStats::privReads
statistics::Scalar privReads
Definition: compute_unit.hh:995
gem5::ComputeUnit::functionalTLB
bool functionalTLB
Definition: compute_unit.hh:345
gem5::ComputeUnit::numAtBarrier
int numAtBarrier(int bar_id)
Definition: compute_unit.cc:668
gem5::WFBarrier::numAtBarrier
int numAtBarrier() const
Definition: compute_unit.hh:100
gem5::ComputeUnit::incNumAtBarrier
void incNumAtBarrier(int bar_id)
Definition: compute_unit.cc:661
gem5::ComputeUnit::ScalarDataPort::MemReqEvent::scalarDataPort
ScalarDataPort & scalarDataPort
Definition: compute_unit.hh:582
gem5::ComputeUnit::ComputeUnitStats::completedWfs
statistics::Scalar completedWfs
Definition: compute_unit.hh:1077
gem5::ComputeUnit::DTLBPort::recvAtomic
virtual Tick recvAtomic(PacketPtr pkt)
Definition: compute_unit.hh:685
gem5::ScalarMemPipeline
Definition: scalar_memory_pipeline.hh:58
gem5::ComputeUnit::ComputeUnitStats::numVecOpsExecuted
statistics::Scalar numVecOpsExecuted
Definition: compute_unit.hh:1038
gem5::ComputeUnit::oprNetPipeLength
int oprNetPipeLength() const
Definition: compute_unit.hh:387
gem5::TLB_HIT_CACHE_MISS
@ TLB_HIT_CACHE_MISS
Definition: compute_unit.hh:82
gem5::ComputeUnit::cacheLineBits
int cacheLineBits
Definition: compute_unit.hh:886
gem5::WFBarrier::InvalidID
static const int InvalidID
Definition: compute_unit.hh:97
gem5::ComputeUnit::ITLBPort::computeUnit
ComputeUnit * computeUnit
Definition: compute_unit.hh:748
gem5::ComputeUnit::SQCPort::recvFunctional
virtual void recvFunctional(PacketPtr pkt)
Definition: compute_unit.hh:631
gem5::ComputeUnit::decMaxBarrierCnt
void decMaxBarrierCnt(int bar_id)
Definition: compute_unit.cc:689
gem5::ComputeUnit::vectorSharedMemUnit
WaitClass vectorSharedMemUnit
Definition: compute_unit.hh:233
gem5::ComputeUnit::SQCPort::SenderState::kernId
int kernId
Definition: compute_unit.hh:616
gem5::ComputeUnit::releaseWFsFromBarrier
void releaseWFsFromBarrier(int bar_id)
Definition: compute_unit.cc:704
gem5::ComputeUnit::ITLBPort
Definition: compute_unit.hh:719
gem5::ComputeUnit::ComputeUnitStats::activeLanesPerGMemInstrDist
statistics::Distribution activeLanesPerGMemInstrDist
Definition: compute_unit.hh:1067
gem5::ComputeUnit::ScalarDTLBPort::ScalarDTLBPort
ScalarDTLBPort(const std::string &_name, ComputeUnit *_cu)
Definition: compute_unit.hh:694
gem5::Event
Definition: eventq.hh:251
gem5::ComputeUnit::scalarMemUnit
WaitClass scalarMemUnit
Definition: compute_unit.hh:241
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::ComputeUnit::initiateFetch
void initiateFetch(Wavefront *wavefront)
gem5::ComputeUnit::execStage
ExecStage execStage
Definition: compute_unit.hh:283
gem5::ComputeUnit::ScalarDataPort::MemReqEvent::description
const char * description() const
Return a C string describing the event.
Definition: compute_unit.cc:1594
gem5::ComputeUnit::ComputeUnitStats::vALUInsts
statistics::Scalar vALUInsts
Definition: compute_unit.hh:947
gem5::ComputeUnit::ComputeUnitStats::instCyclesVALU
statistics::Scalar instCyclesVALU
Definition: compute_unit.hh:951
gem5::ComputeUnit::ComputeUnitStats::numVecOpsExecutedMAC64
statistics::Scalar numVecOpsExecutedMAC64
Definition: compute_unit.hh:1052
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
statistics.hh
gem5::ComputeUnit::handleMemPacket
void handleMemPacket(PacketPtr pkt, int memport_index)
gem5::ComputeUnit::LDSPort::SenderState::_gpuDynInst
GPUDynInstPtr _gpuDynInst
Definition: compute_unit.hh:787
gem5::ComputeUnit::DTLBPort::unstallPort
void unstallPort()
Definition: compute_unit.hh:654
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::ComputeUnit::tickEvent
EventFunctionWrapper tickEvent
Definition: compute_unit.hh:288
gem5::WaitClass
Definition: misc.hh:67
gem5::ComputeUnit::scheduleToExecute
ScheduleToExecute scheduleToExecute
Definition: compute_unit.hh:923
gem5::RR
@ RR
Definition: compute_unit.hh:75
gem5::ComputeUnit::globalMemoryPipe
GlobalMemPipeline globalMemoryPipe
Definition: compute_unit.hh:284
gem5::ComputeUnit::resetRegisterPool
void resetRegisterPool()
Definition: compute_unit.cc:410
gem5::ComputeUnit::ScalarDTLBPort::computeUnit
ComputeUnit * computeUnit
Definition: compute_unit.hh:715
gem5::ComputeUnit::registerManager
RegisterManager * registerManager
Definition: compute_unit.hh:278
gem5::ComputeUnit::ComputeUnitStats::numInstrExecuted
statistics::Scalar numInstrExecuted
Definition: compute_unit.hh:1033
gem5::WFBarrier::WFBarrier
WFBarrier()
Definition: compute_unit.hh:93
gem5::TLB_MISS_CACHE_MISS
@ TLB_MISS_CACHE_MISS
Definition: compute_unit.hh:80
gem5::ComputeUnit::ScalarDataPort::recvTimingResp
bool recvTimingResp(PacketPtr pkt) override
Receive a timing response from the peer.
Definition: compute_unit.cc:902
gem5::ComputeUnit::ITLBPort::recvReqRetry
virtual void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: compute_unit.cc:1773
gem5::ComputeUnit::ScalarDTLBPort::stallPort
void stallPort()
Definition: compute_unit.hh:709
gem5::ComputeUnit::ComputeUnitStats::numCASOps
statistics::Scalar numCASOps
Definition: compute_unit.hh:1075
port.hh
gem5::ComputeUnit::DataPort::createMemReqEvent
EventFunctionWrapper * createMemReqEvent(PacketPtr pkt)
Definition: compute_unit.cc:1555
gem5::ComputeUnit::ComputeUnitStats::vectorMemInstsPerKiloInst
statistics::Formula vectorMemInstsPerKiloInst
Definition: compute_unit.hh:972
gem5::EXEC_POLICY
EXEC_POLICY
Definition: compute_unit.hh:72
gem5::ComputeUnit::~ComputeUnit
~ComputeUnit()
Definition: compute_unit.cc:218
gem5::ComputeUnit::DTLBPort::retries
std::deque< PacketPtr > retries
here we queue all the translation requests that were not successfully sent.
Definition: compute_unit.hh:660
gem5::ComputeUnit::DataPort
Data access Port.
Definition: compute_unit.hh:508
gem5::ComputeUnit::ComputeUnitStats::ldsBankAccesses
statistics::Scalar ldsBankAccesses
Definition: compute_unit.hh:1016
gem5::ComputeUnit::SQCPort
Definition: compute_unit.hh:603
gem5::ComputeUnit::vrf_lm_bus_latency
Cycles vrf_lm_bus_latency
Definition: compute_unit.hh:320
gem5::ComputeUnit::GMTokenPort
Definition: compute_unit.hh:487
gem5::ComputeUnit::ScalarDTLBPort::stalled
bool stalled
Definition: compute_unit.hh:716
gem5::ComputeUnit::spBypassPipeLength
int spBypassPipeLength
Definition: compute_unit.hh:304
gem5::ComputeUnit::DTLBPort::SenderState::_gpuDynInst
GPUDynInstPtr _gpuDynInst
Definition: compute_unit.hh:668
gem5::ComputeUnit::activeWaves
int activeWaves
Definition: compute_unit.hh:941
gem5::ComputeUnit::ComputeUnitStats::numTimesWgBlockedDueVgprAlloc
statistics::Scalar numTimesWgBlockedDueVgprAlloc
Definition: compute_unit.hh:1072
gem5::ComputeUnit::processFetchReturn
void processFetchReturn(PacketPtr pkt)
gem5::ComputeUnit::DataPort::getDeviceAddressRanges
virtual void getDeviceAddressRanges(AddrRangeList &resp, bool &snoop)
Definition: compute_unit.hh:547
gem5::ComputeUnit::ITLBPort::recvAtomic
virtual Tick recvAtomic(PacketPtr pkt)
Definition: compute_unit.hh:752
compiler.hh
gem5::LdsChunk
this represents a slice of the overall LDS, intended to be associated with an individual workgroup
Definition: lds_state.hh:56
gem5::ComputeUnit::cacheLineSize
int cacheLineSize() const
Definition: compute_unit.hh:411
gem5::ComputeUnit::ITLBPort::recvRangeChange
virtual void recvRangeChange()
Called to receive an address range change from the peer response port.
Definition: compute_unit.hh:754
gem5::ComputeUnit::mapWaveToScalarMem
int mapWaveToScalarMem(Wavefront *w) const
Definition: compute_unit.cc:287
gem5::ComputeUnit::mapWaveToGlobalMem
int mapWaveToGlobalMem(Wavefront *w) const
Definition: compute_unit.cc:271
gem5::ComputeUnit::deleteFromPipeMap
void deleteFromPipeMap(Wavefront *w)
Definition: compute_unit.cc:507
gem5::ComputeUnit::SQCPort::recvAtomic
virtual Tick recvAtomic(PacketPtr pkt)
Definition: compute_unit.hh:630
gem5::ComputeUnit::LDSPort
the port intended to communicate between the CU and its LDS
Definition: compute_unit.hh:761
gem5::ComputeUnit::doFlush
void doFlush(GPUDynInstPtr gpuDynInst)
trigger flush operation in the cu
Definition: compute_unit.cc:402
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::ComputeUnit::DataPort::SenderState::port_index
PortID port_index
Definition: compute_unit.hh:519
gem5::ComputeUnit::init
virtual void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: compute_unit.cc:752
gem5::ComputeUnit::scalarALUs
std::vector< WaitClass > scalarALUs
Definition: compute_unit.hh:249
gem5::ComputeUnit::DataPort::SenderState::_gpuDynInst
GPUDynInstPtr _gpuDynInst
Definition: compute_unit.hh:518
gem5::ComputeUnit::dpBypassLength
int dpBypassLength() const
Definition: compute_unit.hh:390
gem5::ComputeUnit::memPort
std::vector< DataPort > memPort
The memory port for SIMD data accesses.
Definition: compute_unit.hh:845
gem5::OLDEST
@ OLDEST
Definition: compute_unit.hh:74
gem5::ComputeUnit::ComputeUnitStats::scalarMemReadsPerKiloInst
statistics::Formula scalarMemReadsPerKiloInst
Definition: compute_unit.hh:973
gem5::Packet::SenderState
A virtual base opaque structure used to hold state associated with the packet (e.g....
Definition: packet.hh:457
gem5::ComputeUnit::ComputeUnitStats::vectorMemReadsPerKiloInst
statistics::Formula vectorMemReadsPerKiloInst
Definition: compute_unit.hh:970
gem5::ComputeUnit::DTLBPort::SenderState::portIndex
PortID portIndex
Definition: compute_unit.hh:672
gem5::ComputeUnit::perLaneTLB
bool perLaneTLB
Definition: compute_unit.hh:329
local_memory_pipeline.hh
gem5::ComputeUnit::instExecPerSimd
std::vector< uint64_t > instExecPerSimd
Definition: compute_unit.hh:326
gem5::ComputeUnit::lastMemUnit
int lastMemUnit() const
Definition: compute_unit.cc:246
gem5::ComputeUnit::ITLBPort::SenderState::SenderState
SenderState(Wavefront *_wavefront)
Definition: compute_unit.hh:744
gem5::ComputeUnit::ScalarDTLBPort::unstallPort
void unstallPort()
Definition: compute_unit.hh:710
gem5::ComputeUnit::lastVaddrWF
std::vector< std::vector< std::vector< Addr > > > lastVaddrWF
Definition: compute_unit.hh:337
gem5::ComputeUnit::ScalarDTLBPort::SenderState::_gpuDynInst
GPUDynInstPtr _gpuDynInst
Definition: compute_unit.hh:702
gem5::ComputeUnit::ComputeUnitStats::groupWrites
statistics::Scalar groupWrites
Definition: compute_unit.hh:993
gem5::ComputeUnit::LDSPort::LDSPort
LDSPort(const std::string &_name, ComputeUnit *_cu)
Definition: compute_unit.hh:764
gem5::ComputeUnit::numBarrierSlots
int numBarrierSlots() const
Definition: compute_unit.hh:444
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ComputeUnit::ComputeUnitStats::globalWrites
statistics::Scalar globalWrites
Definition: compute_unit.hh:984
gem5::ComputeUnit::ComputeUnitStats::vALUInstsPerWF
statistics::Formula vALUInstsPerWF
Definition: compute_unit.hh:948
gem5::ComputeUnit::getTokenManager
TokenManager * getTokenManager()
Definition: compute_unit.hh:837
gem5::ComputeUnit::ScalarDataPort::MemReqEvent::MemReqEvent
MemReqEvent(ScalarDataPort &_scalar_data_port, PacketPtr _pkt)
Definition: compute_unit.hh:586
gem5::ComputeUnit::ComputeUnitStats::numTimesWgBlockedDueSgprAlloc
statistics::Scalar numTimesWgBlockedDueSgprAlloc
Definition: compute_unit.hh:1074
gem5::ComputeUnit::ComputeUnitStats::numVecOpsExecutedF16
statistics::Scalar numVecOpsExecutedF16
Definition: compute_unit.hh:1040
gem5::ComputeUnit::barrierSlot
WFBarrier & barrierSlot(int bar_id)
Definition: compute_unit.hh:418
scalar_memory_pipeline.hh
gem5::ComputeUnit::exitCallback
void exitCallback()
Definition: compute_unit.cc:1922
gem5::ComputeUnit::SQCPort::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Definition: compute_unit.cc:979
gem5::ComputeUnit::ComputeUnitStats::privMemInsts
statistics::Formula privMemInsts
Definition: compute_unit.hh:997
gem5::ComputeUnit::mapWaveToScalarAlu
int mapWaveToScalarAlu(Wavefront *w) const
Definition: compute_unit.cc:253
schedule_stage.hh
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:49
gem5::ComputeUnit::hasDispResources
bool hasDispResources(HSAQueueEntry *task, int &num_wfs_in_wg)
Definition: compute_unit.cc:519
gem5::ComputeUnit::DataPort::computeUnit
ComputeUnit * computeUnit
Definition: compute_unit.hh:538
gem5::ComputeUnit::getFreeBarrierId
int getFreeBarrierId()
Definition: compute_unit.hh:425
gem5::ComputeUnit::wfSize
int wfSize() const
Definition: compute_unit.hh:394
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::ComputeUnit::pipeMap
std::unordered_set< uint64_t > pipeMap
Definition: compute_unit.hh:276
gem5::ComputeUnit::SQCPort::snoopRangeSent
bool snoopRangeSent
Definition: compute_unit.hh:609
gem5::TLB_HIT_CACHE_HIT
@ TLB_HIT_CACHE_HIT
Definition: compute_unit.hh:83
gem5::ComputeUnit::LDSPort::recvReqRetry
virtual void recvReqRetry()
the bus is telling the port that there is now space so retrying stalled requests should work now this...
Definition: compute_unit.cc:2079
gem5::ComputeUnit::DataPort::recvFunctional
virtual void recvFunctional(PacketPtr pkt)
Definition: compute_unit.hh:542
gem5::ComputeUnit::SQCPort::SenderState::saved
Packet::SenderState * saved
Definition: compute_unit.hh:614
gem5::ComputeUnit::DataPort::retries
std::deque< std::pair< PacketPtr, GPUDynInstPtr > > retries
Definition: compute_unit.hh:535
gem5::ComputeUnit::SQCPort::getDeviceAddressRanges
virtual void getDeviceAddressRanges(AddrRangeList &resp, bool &snoop)
Definition: compute_unit.hh:636
gem5::ComputeUnit::SQCPort::SenderState::SenderState
SenderState(Wavefront *_wavefront, Packet::SenderState *sender_state=nullptr, int _kernId=-1)
Definition: compute_unit.hh:618
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::ComputeUnit::updateInstStats
void updateInstStats(GPUDynInstPtr gpuDynInst)
Definition: compute_unit.cc:1803
gem5::ComputeUnit::ComputeUnitStats::numALUInstsExecuted
statistics::Formula numALUInstsExecuted
Definition: compute_unit.hh:1070
gem5::ComputeUnit::ComputeUnitStats::instCyclesLdsPerSimd
statistics::Vector instCyclesLdsPerSimd
Definition: compute_unit.hh:981
register_manager.hh
gem5::ComputeUnit::ComputeUnitStats::argReads
statistics::Scalar argReads
Definition: compute_unit.hh:986
gem5::ComputeUnit::getCacheLineBits
int getCacheLineBits() const
Definition: compute_unit.hh:412
gem5::ComputeUnit::pageDataStruct
std::unordered_map< Addr, std::pair< int, int > > pageDataStruct
Definition: compute_unit.hh:482
gem5::ComputeUnit::ComputeUnitStats::globalMemInsts
statistics::Formula globalMemInsts
Definition: compute_unit.hh:985
gem5::ComputeUnit::ComputeUnitStats::wgBlockedDueLdsAllocation
statistics::Scalar wgBlockedDueLdsAllocation
Definition: compute_unit.hh:1029
gem5::ComputeUnit::LDSPort::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
get the result of packets sent to the LDS when they return
Definition: compute_unit.cc:2015
gem5::ComputeUnit::operandNetworkLength
int operandNetworkLength
Definition: compute_unit.hh:311
gem5::ComputeUnit::numVectorGlobalMemUnits
int numVectorGlobalMemUnits
Definition: compute_unit.hh:219
gem5::ComputeUnit::prefetchStride
int prefetchStride
Definition: compute_unit.hh:333
gem5::ComputeUnit::Params
ComputeUnitParams Params
Definition: compute_unit.hh:290
gem5::ComputeUnit::ComputeUnitStats::numVecOpsExecutedMAD16
statistics::Scalar numVecOpsExecutedMAD16
Definition: compute_unit.hh:1054
gem5::ComputeUnit::ComputeUnitStats::ipc
statistics::Formula ipc
Definition: compute_unit.hh:1065
gem5::ComputeUnit::localMemBarrier
bool localMemBarrier
Definition: compute_unit.hh:346
gem5::ComputeUnit::updatePageDivergenceDist
void updatePageDivergenceDist(Addr addr)
Definition: compute_unit.cc:1911
gem5::ScoreboardCheckToSchedule
Communication interface between ScoreboardCheck and Schedule stages.
Definition: comm.hh:62
gem5::ComputeUnit::vectorRegsReserved
std::vector< int > vectorRegsReserved
Definition: compute_unit.hh:367
gem5::ComputeUnit::ComputeUnitStats::readonlyWrites
statistics::Scalar readonlyWrites
Definition: compute_unit.hh:999
gem5::ComputeUnit::ComputeUnitStats::numVecOpsExecutedMAC16
statistics::Scalar numVecOpsExecutedMAC16
Definition: compute_unit.hh:1050
gem5::ComputeUnit::ComputeUnitStats::waveLevelParallelism
statistics::Distribution waveLevelParallelism
Definition: compute_unit.hh:1005
gem5::ComputeUnit::ComputeUnitStats::scalarMemWrites
statistics::Scalar scalarMemWrites
Definition: compute_unit.hh:965
gem5::ComputeUnit::ITLBPort::unstallPort
void unstallPort()
Definition: compute_unit.hh:728
gem5::ComputeUnit::vrf_gm_bus_latency
Cycles vrf_gm_bus_latency
Definition: compute_unit.hh:316
gem5::ComputeUnit::vrfToCoalescerBusWidth
int vrfToCoalescerBusWidth
Definition: compute_unit.hh:268
gem5::ComputeUnit::ComputeUnitStats::controlFlowDivergenceDist
statistics::Distribution controlFlowDivergenceDist
Definition: compute_unit.hh:1066
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::ComputeUnit::ComputeUnitStats::vectorMemWrites
statistics::Scalar vectorMemWrites
Definition: compute_unit.hh:961
gem5::ComputeUnit::insertInPipeMap
void insertInPipeMap(Wavefront *w)
Definition: compute_unit.cc:498
gem5::GlobalMemPipeline
Definition: global_memory_pipeline.hh:59
types.hh
gem5::ComputeUnit::LDSPort::stallPort
void stallPort()
Definition: compute_unit.hh:770
gem5::WFBarrier::_numAtBarrier
int _numAtBarrier
The number of WFs in the WG that have reached the barrier.
Definition: compute_unit.hh:189
gem5::ComputeUnit::ScalarDTLBPort::SenderState
Definition: compute_unit.hh:699
gem5::ComputeUnit::mapWaveToLocalMem
int mapWaveToLocalMem(Wavefront *w) const
Definition: compute_unit.cc:279
gem5::ComputeUnit::LDSPort::recvRangeChange
virtual void recvRangeChange()
Called to receive an address range change from the peer response port.
Definition: compute_unit.hh:823
gem5::ComputeUnit::ldsPort
LDSPort ldsPort
The port to access the Local Data Store Can be connected to a LDS object.
Definition: compute_unit.hh:834
gem5::ComputeUnit::LDSPort::computeUnit
ComputeUnit * computeUnit
Definition: compute_unit.hh:809
gem5::ComputeUnit::ComputeUnitStats::numVecOpsExecutedFMA64
statistics::Scalar numVecOpsExecutedFMA64
Definition: compute_unit.hh:1048
clocked_object.hh
gem5::ComputeUnit::ComputeUnitStats::flatLDSInstsPerWF
statistics::Formula flatLDSInstsPerWF
Definition: compute_unit.hh:960
std::deque
STL deque class.
Definition: stl.hh:44
gem5::WFBarrier
WF barrier slots.
Definition: compute_unit.hh:90
gem5::ComputeUnit::DataPort::SenderState::saved
Packet::SenderState * saved
Definition: compute_unit.hh:520
gem5::ComputeUnit::isDone
bool isDone() const
Definition: compute_unit.cc:1939
gem5::ComputeUnit::LDSPort::SenderState::getMemInst
GPUDynInstPtr getMemInst() const
Definition: compute_unit.hh:796
gem5::ComputeUnit::ComputeUnitStats::hitsPerTLBLevel
statistics::Vector hitsPerTLBLevel
Definition: compute_unit.hh:1014
token_port.hh
gem5::ComputeUnit::maxBarrierCnt
int maxBarrierCnt(int bar_id)
Definition: compute_unit.cc:675
gem5::ComputeUnit::scalarRegsReserved
std::vector< int > scalarRegsReserved
Definition: compute_unit.hh:369
gem5::ComputeUnit::fillKernelState
void fillKernelState(Wavefront *w, HSAQueueEntry *task)
Definition: compute_unit.cc:295
gem5::ComputeUnit::lds
LdsState & lds
Definition: compute_unit.hh:468
gem5::ComputeUnit::LDSPort::recvFunctional
virtual void recvFunctional(PacketPtr pkt)
Definition: compute_unit.hh:818
gem5::ComputeUnit::DTLBPort::SenderState
SenderState is information carried along with the packet throughout the TLB hierarchy.
Definition: compute_unit.hh:665
gem5::ComputeUnit::SQCPort::SQCPort
SQCPort(const std::string &_name, ComputeUnit *_cu)
Definition: compute_unit.hh:606
gem5::ComputeUnit::vrfToLocalMemPipeBus
WaitClass vrfToLocalMemPipeBus
Definition: compute_unit.hh:231
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::ComputeUnit::ComputeUnitStats::execRateDist
statistics::Distribution execRateDist
Definition: compute_unit.hh:1036
gem5::ComputeUnit::tlbPort
std::vector< DTLBPort > tlbPort
Definition: compute_unit.hh:847
gem5::ComputeUnit::ComputeUnitStats::numVecOpsExecutedF32
statistics::Scalar numVecOpsExecutedF32
Definition: compute_unit.hh:1042
gem5::ComputeUnit::isVectorAluIdle
bool isVectorAluIdle(uint32_t simdId) const
Definition: compute_unit.cc:1976
gem5::ComputeUnit::numScalarRegsPerSimd
int numScalarRegsPerSimd
Definition: compute_unit.hh:373
gem5::ComputeUnit::vectorALUs
std::vector< WaitClass > vectorALUs
Definition: compute_unit.hh:245
gem5::WFBarrier::allAtBarrier
bool allAtBarrier() const
Have all WFs participating in this barrier reached the barrier? If so, then the barrier is satisfied ...
Definition: compute_unit.hh:146
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::ComputeUnit::sendScalarRequest
void sendScalarRequest(GPUDynInstPtr gpuDynInst, PacketPtr pkt)
Definition: compute_unit.cc:1202
gem5::ComputeUnit::LDSPort::isStalled
bool isStalled() const
Definition: compute_unit.hh:769
gem5::ComputeUnit::countPages
bool countPages
Definition: compute_unit.hh:351
gem5::ComputeUnit::_cacheLineSize
const int _cacheLineSize
Definition: compute_unit.hh:884
gem5::ComputeUnit::freeBarrierIds
std::unordered_set< int > freeBarrierIds
A set used to easily retrieve a free barrier ID.
Definition: compute_unit.hh:932
gem5::ComputeUnit::ComputeUnitStats::ComputeUnitStats
ComputeUnitStats(statistics::Group *parent, int n_wf)
Definition: compute_unit.cc:2110
gem5::RegisterManager
Definition: register_manager.hh:57
gem5::ComputeUnit::LDSPort::retries
std::queue< PacketPtr > retries
here we queue all the requests that were not successfully sent.
Definition: compute_unit.hh:777
gem5::ComputeUnit::scalarMemToSrfBus
WaitClass scalarMemToSrfBus
Definition: compute_unit.hh:237
gem5::ComputeUnit::scalarDTLBPort
ScalarDTLBPort scalarDTLBPort
Definition: compute_unit.hh:851
gem5::LocalMemPipeline
Definition: local_memory_pipeline.hh:57
gem5::ComputeUnit::ComputeUnitStats::pageDivergenceDist
statistics::Distribution pageDivergenceDist
Definition: compute_unit.hh:1021
gem5::ComputeUnit::DataPort::recvRangeChange
virtual void recvRangeChange()
Called to receive an address range change from the peer response port.
Definition: compute_unit.hh:543
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
gem5::WFBarrier::setMaxBarrierCnt
void setMaxBarrierCnt(int max_barrier_cnt)
Set the maximum barrier count (i.e., the number of WFs that are participating in the barrier).
Definition: compute_unit.hh:125
gem5::statistics::VectorDistribution
A vector of distributions.
Definition: statistics.hh:2245
gem5::ComputeUnit::ScalarDataPort::MemReqEvent
Definition: compute_unit.hh:579
gem5::ComputeUnit::ScalarDataPort::ScalarDataPort
ScalarDataPort(const std::string &_name, ComputeUnit *_cu)
Definition: compute_unit.hh:559
gem5::ComputeUnit::ComputeUnitStats::argWrites
statistics::Scalar argWrites
Definition: compute_unit.hh:987
gem5::ComputeUnit::GMTokenPort::~GMTokenPort
~GMTokenPort()
Definition: compute_unit.hh:494
gem5::WFBarrier::reset
void reset()
Reset the barrier.
Definition: compute_unit.hh:178
gem5::ComputeUnit::ComputeUnitStats::vpc_f32
statistics::Formula vpc_f32
Definition: compute_unit.hh:1063
gem5::WFBarrier::incNumAtBarrier
void incNumAtBarrier()
Mark that a WF has reached the barrier.
Definition: compute_unit.hh:134
std::list< AddrRange >
gem5::WFBarrier::maxBarrierCnt
int maxBarrierCnt() const
Definition: compute_unit.hh:115
gem5::ComputeUnit::sendToLds
bool sendToLds(GPUDynInstPtr gpuDynInst)
send a general request to the LDS make sure to look at the return value here as your request might be...
Definition: compute_unit.cc:1995
gem5::ComputeUnit::ComputeUnitStats::dynamicLMemInstrCnt
statistics::Scalar dynamicLMemInstrCnt
Definition: compute_unit.hh:1026
gem5::RequestPort::owner
SimObject & owner
Definition: port.hh:86
gem5::ComputeUnit::ComputeUnitStats::numFailedCASOps
statistics::Scalar numFailedCASOps
Definition: compute_unit.hh:1076
gem5::ComputeUnit::ITLBPort::stalled
bool stalled
Definition: compute_unit.hh:749
gem5::ComputeUnit::scalarMemoryPipe
ScalarMemPipeline scalarMemoryPipe
Definition: compute_unit.hh:286
gem5::ComputeUnit::ITLBPort::recvFunctional
virtual void recvFunctional(PacketPtr pkt)
Definition: compute_unit.hh:753
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::ComputeUnit::DataPort::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Definition: compute_unit.cc:801
gem5::ComputeUnit::vectorGlobalMemUnit
WaitClass vectorGlobalMemUnit
Definition: compute_unit.hh:225
gem5::ComputeUnit::simdUnitWidth
int simdUnitWidth() const
Definition: compute_unit.hh:388
gem5::ComputeUnit::ComputeUnitStats::readonlyMemInsts
statistics::Formula readonlyMemInsts
Definition: compute_unit.hh:1000
gem5::ComputeUnit::ScalarDataPort::recvReqRetry
void recvReqRetry() override
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: compute_unit.cc:940
gem5::ComputeUnit::ComputeUnitStats::scalarMemReads
statistics::Scalar scalarMemReads
Definition: compute_unit.hh:967
gem5::ComputeUnit::ComputeUnitStats::totalCycles
statistics::Scalar totalCycles
Definition: compute_unit.hh:1060
gem5::ComputeUnit::dispWorkgroup
void dispWorkgroup(HSAQueueEntry *task, int num_wfs_in_wg)
Definition: compute_unit.cc:420
gem5::ComputeUnit::prefetchType
enums::PrefetchType prefetchType
Definition: compute_unit.hh:338
exec_stage.hh
gem5::ComputeUnit::ComputeUnitStats::tlbCycles
statistics::Scalar tlbCycles
Definition: compute_unit.hh:1010
gem5::ComputeUnit::mapWaveToScalarAluGlobalIdx
int mapWaveToScalarAluGlobalIdx(Wavefront *w) const
Definition: compute_unit.cc:264
gem5::ComputeUnit::gmTokenPort
GMTokenPort gmTokenPort
Definition: compute_unit.hh:505
gem5::ComputeUnit::getPort
Port & getPort(const std::string &if_name, PortID idx) override
Get a port with a given name and index.
Definition: compute_unit.hh:858
gem5::ComputeUnit::scalarPipeStages
int scalarPipeStages
Definition: compute_unit.hh:309
gem5::ComputeUnit::DataPort::recvReqRetry
virtual void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: compute_unit.cc:952
gem5::ComputeUnit::DTLBPort::stalled
bool stalled
Definition: compute_unit.hh:682
gem5::ComputeUnit::doInvalidate
void doInvalidate(RequestPtr req, int kernId)
trigger invalidate operation in the cu
Definition: compute_unit.cc:383
gem5::ComputeUnit::sqcPort
SQCPort sqcPort
Definition: compute_unit.hh:853
gem5::ComputeUnit::ComputeUnitStats::spillReads
statistics::Scalar spillReads
Definition: compute_unit.hh:989
gem5::ComputeUnit::ITLBPort::ITLBPort
ITLBPort(const std::string &_name, ComputeUnit *_cu)
Definition: compute_unit.hh:722
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Definition: compute_unit.cc:654
gem5::ComputeUnit::numWfsToSched
std::vector< int > numWfsToSched
Number of WFs to schedule to each SIMD.
Definition: compute_unit.hh:364
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statistics::Formula ldsNoFlatInstsPerWF
Definition: compute_unit.hh:956
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Definition: lds_state.hh:120
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SenderState(GPUDynInstPtr gpuDynInst)
Definition: compute_unit.hh:701
gem5::ComputeUnit::srf_scm_bus_latency
Cycles srf_scm_bus_latency
Definition: compute_unit.hh:318
callback.hh
gem5::ComputeUnit::ScalarDataPort
Definition: compute_unit.hh:556
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statistics::Scalar numVecOpsExecutedFMA16
Definition: compute_unit.hh:1046
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Definition: compute_unit.hh:516
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const std::string _name
Definition: named.hh:41
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DTLBPort(const std::string &_name, ComputeUnit *_cu, PortID id)
Definition: compute_unit.hh:647
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Definition: compute_unit.hh:567
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ScheduleStage scheduleStage
Definition: compute_unit.hh:282
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const int _numBarrierSlots
Definition: compute_unit.hh:885
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Definition: compute_unit.hh:569
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Definition: compute_unit.cc:1563
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Definition: compute_unit.hh:460
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Bitfield< 3 > addr
Definition: types.hh:84
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statistics::Formula scalarMemInstsPerKiloInst
Definition: compute_unit.hh:975
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statistics::Formula vectorMemWritesPerKiloInst
Definition: compute_unit.hh:971
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Definition: token_port.hh:44
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Definition: compute_unit.cc:231
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Definition: shader.hh:82
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Definition: compute_unit.hh:221

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