gem5 v24.0.0.0
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gpu_exec_context.hh
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1/*
2 * Copyright (c) 2015-2018 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#ifndef __GPU_EXEC_CONTEXT_HH__
33#define __GPU_EXEC_CONTEXT_HH__
34
35#include "arch/gpu_isa.hh"
36#include "base/types.hh"
37#include "config/the_gpu_isa.hh"
38
39namespace gem5
40{
41
42class ComputeUnit;
43class Wavefront;
44
46{
47 public:
51
52 template<typename T> T
53 readConstVal(int opIdx) const
54 {
55 return gpuISA->readConstVal<T>(opIdx);
56 }
57
58 RegVal readMiscReg(int opIdx) const;
59 void writeMiscReg(int opIdx, RegVal operandVal);
60
61 protected:
64 TheGpuISA::GPUISA *gpuISA;
65};
66
67} // namespace gem5
68
69#endif // __GPU_EXEC_CONTEXT_HH__
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
void writeMiscReg(int opIdx, RegVal operandVal)
TheGpuISA::GPUISA * gpuISA
ComputeUnit * computeUnit()
RegVal readMiscReg(int opIdx) const
T readConstVal(int opIdx) const
GPUExecContext(ComputeUnit *_cu, Wavefront *_wf)
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint64_t RegVal
Definition types.hh:173

Generated on Tue Jun 18 2024 16:24:04 for gem5 by doxygen 1.11.0