gem5  v22.1.0.0
gpu_exec_context.hh
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31 
32 #ifndef __GPU_EXEC_CONTEXT_HH__
33 #define __GPU_EXEC_CONTEXT_HH__
34 
35 #include "arch/gpu_isa.hh"
36 #include "base/types.hh"
37 #include "config/the_gpu_isa.hh"
38 
39 namespace gem5
40 {
41 
42 class ComputeUnit;
43 class Wavefront;
44 
46 {
47  public:
51 
52  template<typename T> T
53  readConstVal(int opIdx) const
54  {
55  return gpuISA->readConstVal<T>(opIdx);
56  }
57 
58  RegVal readMiscReg(int opIdx) const;
59  void writeMiscReg(int opIdx, RegVal operandVal);
60 
61  protected:
64  TheGpuISA::GPUISA *gpuISA;
65 };
66 
67 } // namespace gem5
68 
69 #endif // __GPU_EXEC_CONTEXT_HH__
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
void writeMiscReg(int opIdx, RegVal operandVal)
TheGpuISA::GPUISA * gpuISA
ComputeUnit * computeUnit()
RegVal readMiscReg(int opIdx) const
T readConstVal(int opIdx) const
GPUExecContext(ComputeUnit *_cu, Wavefront *_wf)
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint64_t RegVal
Definition: types.hh:173

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