gem5  v22.0.0.1
gpu_exec_context.hh
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31 
32 #ifndef __GPU_EXEC_CONTEXT_HH__
33 #define __GPU_EXEC_CONTEXT_HH__
34 
35 #include "arch/gpu_isa.hh"
36 #include "base/types.hh"
37 #include "config/the_gpu_isa.hh"
38 
39 namespace gem5
40 {
41 
42 class ComputeUnit;
43 class Wavefront;
44 
46 {
47  public:
51 
52  template<typename T> T
53  readConstVal(int opIdx) const
54  {
55  return gpuISA->readConstVal<T>(opIdx);
56  }
57 
58  RegVal readMiscReg(int opIdx) const;
59  void writeMiscReg(int opIdx, RegVal operandVal);
60 
61  protected:
64  TheGpuISA::GPUISA *gpuISA;
65 };
66 
67 } // namespace gem5
68 
69 #endif // __GPU_EXEC_CONTEXT_HH__
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::GPUExecContext::readConstVal
T readConstVal(int opIdx) const
Definition: gpu_exec_context.hh:53
gem5::GPUExecContext::writeMiscReg
void writeMiscReg(int opIdx, RegVal operandVal)
Definition: gpu_exec_context.cc:63
gem5::Wavefront
Definition: wavefront.hh:60
gem5::GPUExecContext::wf
Wavefront * wf
Definition: gpu_exec_context.hh:63
gem5::GPUExecContext::gpuISA
TheGpuISA::GPUISA * gpuISA
Definition: gpu_exec_context.hh:64
gem5::GPUExecContext::computeUnit
ComputeUnit * computeUnit()
Definition: gpu_exec_context.cc:44
gem5::ComputeUnit
Definition: compute_unit.hh:201
gem5::GPUExecContext::GPUExecContext
GPUExecContext(ComputeUnit *_cu, Wavefront *_wf)
Definition: gpu_exec_context.cc:38
gem5::GPUExecContext::readMiscReg
RegVal readMiscReg(int opIdx) const
Definition: gpu_exec_context.cc:56
gem5::GPUExecContext::wavefront
Wavefront * wavefront()
Definition: gpu_exec_context.cc:50
gem5::GPUExecContext
Definition: gpu_exec_context.hh:45
types.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::GPUExecContext::cu
ComputeUnit * cu
Definition: gpu_exec_context.hh:62

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