indirect_memory.hh

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#ifndef __MEM_CACHE_PREFETCH_INDIRECT_MEMORY_HH__
#define __MEM_CACHE_PREFETCH_INDIRECT_MEMORY_HH__
 
#include <vector>
 
#include "base/sat_counter.hh"
#include "mem/cache/prefetch/associative_set.hh"
#include "mem/cache/prefetch/queued.hh"
 
namespace gem5
{
 
struct IndirectMemoryPrefetcherParams;
 
namespace prefetch
{
 
class IndirectMemory : public Queued
{
    const unsigned int maxPrefetchDistance;
    const std::vector<int> shiftValues;
    const unsigned int prefetchThreshold;
    const int streamCounterThreshold;
    const int streamingDistance;
 
    struct PrefetchTableEntry : public TaggedEntry
    {
        /* Stream table fields */
 
        Addr address;
        bool secure;
        unsigned int streamCounter;
 
        /* Indirect table fields */
 
        bool enabled;
        int64_t index;
        Addr baseAddr;
        int shift;
        SatCounter8 indirectCounter;
        bool increasedIndirectCounter;
 
        PrefetchTableEntry(unsigned indirect_counter_bits)
            : TaggedEntry(), address(0), secure(false), streamCounter(0),
              enabled(false), index(0), baseAddr(0), shift(0),
              indirectCounter(indirect_counter_bits),
              increasedIndirectCounter(false)
        {}
 
        void
        invalidate() override
        {
            TaggedEntry::invalidate();
            address = 0;
            secure = false;
            streamCounter = 0;
            enabled = false;
            index = 0;
            baseAddr = 0;
            shift = 0;
            indirectCounter.reset();
            increasedIndirectCounter = false;
        }
    };
    AssociativeCache<PrefetchTableEntry> prefetchTable;
 
    struct IndirectPatternDetectorEntry : public TaggedEntry
    {
        int64_t idx1;
        int64_t idx2;
        bool secondIndexSet;
        int numMisses;
        std::vector<std::vector<Addr>> baseAddr;
 
        IndirectPatternDetectorEntry(unsigned int num_addresses,
                                     unsigned int num_shifts)
          : TaggedEntry(), idx1(0), idx2(0), secondIndexSet(false),
            numMisses(0),
            baseAddr(num_addresses, std::vector<Addr>(num_shifts))
        {
        }
 
        void
        invalidate() override
        {
            TaggedEntry::invalidate();
            idx1 = 0;
            idx2 = 0;
            secondIndexSet = false;
            numMisses = 0;
        }
    };
    AssociativeCache<IndirectPatternDetectorEntry> ipd;
 
    IndirectPatternDetectorEntry *ipdEntryTrackingMisses;
 
    const ByteOrder byteOrder;
 
    void allocateOrUpdateIPDEntry(const PrefetchTableEntry *pt_entry,
                                  int64_t index);
    void trackMissIndex1(Addr miss_addr);
 
    void trackMissIndex2(Addr miss_addr);
 
    void checkAccessMatchOnActiveEntries(Addr addr);
 
  public:
    IndirectMemory(const IndirectMemoryPrefetcherParams &p);
    ~IndirectMemory() = default;
 
    void calculatePrefetch(const PrefetchInfo &pfi,
                           std::vector<AddrPriority> &addresses,
                           const CacheAccessor &cache) override;
};
 
} // namespace prefetch
} // namespace gem5
 
#endif//__MEM_CACHE_PREFETCH_INDIRECT_MEMORY_HH__