gem5 v24.1.0.1
|
#include <list>
#include <map>
#include <queue>
#include <vector>
#include "base/statistics.hh"
#include "base/types.hh"
#include "cpu/inst_seq.hh"
#include "cpu/o3/comm.hh"
#include "cpu/o3/dep_graph.hh"
#include "cpu/o3/dyn_inst_ptr.hh"
#include "cpu/o3/limits.hh"
#include "cpu/o3/mem_dep_unit.hh"
#include "cpu/o3/store_set.hh"
#include "cpu/op_class.hh"
#include "cpu/timebuf.hh"
#include "enums/SMTQueuePolicy.hh"
#include "sim/eventq.hh"
Go to the source code of this file.
Classes | |
class | gem5::o3::InstructionQueue |
A standard instruction queue class. More... | |
class | gem5::o3::InstructionQueue::FUCompletion |
FU completion event class. More... | |
struct | gem5::o3::InstructionQueue::PqCompare |
Struct for comparing entries to be added to the priority queue. More... | |
struct | gem5::o3::InstructionQueue::ListOrderEntry |
Entry for the list age ordering by op class. More... | |
struct | gem5::o3::InstructionQueue::IQStats |
struct | gem5::o3::InstructionQueue::IQIOStats |
Namespaces | |
namespace | gem5 |
Copyright (c) 2024 Arm Limited All rights reserved. | |
namespace | gem5::memory |
namespace | gem5::o3 |