gem5  v21.1.0.2
mem_dep_unit.hh
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40 
41 #ifndef __CPU_O3_MEM_DEP_UNIT_HH__
42 #define __CPU_O3_MEM_DEP_UNIT_HH__
43 
44 #include <list>
45 #include <memory>
46 #include <set>
47 #include <unordered_map>
48 #include <unordered_set>
49 
50 #include "base/statistics.hh"
51 #include "cpu/inst_seq.hh"
52 #include "cpu/o3/dyn_inst_ptr.hh"
53 #include "cpu/o3/limits.hh"
54 #include "cpu/o3/store_set.hh"
55 #include "debug/MemDepUnit.hh"
56 
57 namespace gem5
58 {
59 
60 struct SNHash
61 {
62  size_t
63  operator()(const InstSeqNum &seq_num) const
64  {
65  unsigned a = (unsigned)seq_num;
66  unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
67  return hash;
68  }
69 };
70 
71 struct O3CPUParams;
72 
73 namespace o3
74 {
75 
76 class CPU;
77 class InstructionQueue;
78 
91 {
92  protected:
93  std::string _name;
94 
95  public:
97  MemDepUnit();
98 
100  MemDepUnit(const O3CPUParams &params);
101 
103  ~MemDepUnit();
104 
106  std::string name() const { return _name; }
107 
109  void init(const O3CPUParams &params, ThreadID tid, CPU *cpu);
110 
112  bool isDrained() const;
113 
115  void drainSanityCheck() const;
116 
118  void takeOverFrom();
119 
121  void setIQ(InstructionQueue *iq_ptr);
122 
124  void insert(const DynInstPtr &inst);
125 
127  void insertNonSpec(const DynInstPtr &inst);
128 
130  void insertBarrier(const DynInstPtr &barr_inst);
131 
133  void regsReady(const DynInstPtr &inst);
134 
136  void nonSpecInstReady(const DynInstPtr &inst);
137 
139  void reschedule(const DynInstPtr &inst);
140 
144  void replay();
145 
147  void completeInst(const DynInstPtr &inst);
148 
152  void squash(const InstSeqNum &squashed_num, ThreadID tid);
153 
155  void violation(const DynInstPtr &store_inst,
156  const DynInstPtr &violating_load);
157 
159  void issue(const DynInstPtr &inst);
160 
162  void dumpLists();
163 
164  private:
165 
167  void completed(const DynInstPtr &inst);
168 
170  void wakeDependents(const DynInstPtr &inst);
171 
173 
174  class MemDepEntry;
175 
176  typedef std::shared_ptr<MemDepEntry> MemDepEntryPtr;
177 
183  {
184  public:
186  MemDepEntry(const DynInstPtr &new_inst);
187 
189  ~MemDepEntry();
190 
192  std::string name() const { return "memdepentry"; }
193 
196 
199 
202 
204  bool regsReady = false;
206  int memDeps = 0;
208  bool completed = false;
210  bool squashed = false;
211 
213 #ifdef DEBUG
214  static int memdep_count;
215  static int memdep_insert;
216  static int memdep_erase;
217 #endif
218  };
219 
222 
224  void moveToReady(MemDepEntryPtr &ready_inst_entry);
225 
226  typedef std::unordered_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash;
227 
228  typedef typename MemDepHash::iterator MemDepHashIt;
229 
232 
235 
238 
245 
247  std::unordered_set<InstSeqNum> loadBarrierSNs;
248 
250  std::unordered_set<InstSeqNum> storeBarrierSNs;
251 
253  bool hasLoadBarrier() const { return !loadBarrierSNs.empty(); }
254 
256  bool hasStoreBarrier() const { return !storeBarrierSNs.empty(); }
257 
259  void insertBarrierSN(const DynInstPtr &barr_inst);
260 
263 
265  int id;
267  {
279  } stats;
280 };
281 
282 } // namespace o3
283 } // namespace gem5
284 
285 #endif // __CPU_O3_MEM_DEP_UNIT_HH__
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1927
gem5::o3::MemDepUnit::insertBarrierSN
void insertBarrierSN(const DynInstPtr &barr_inst)
Inserts the SN of a barrier inst.
Definition: mem_dep_unit.cc:158
gem5::o3::MemDepUnit::MemDepEntry::memDeps
int memDeps
Number of memory dependencies that need to be satisfied.
Definition: mem_dep_unit.hh:206
gem5::o3::MemDepUnit::hasStoreBarrier
bool hasStoreBarrier() const
Is there an outstanding store barrier that loads must wait on.
Definition: mem_dep_unit.hh:256
gem5::o3::MemDepUnit::MemDepEntry::~MemDepEntry
~MemDepEntry()
Frees any pointers.
Definition: mem_dep_unit.cc:506
gem5::o3::MemDepUnit::iqPtr
InstructionQueue * iqPtr
Pointer to the IQ.
Definition: mem_dep_unit.hh:262
gem5::o3::MemDepUnit::MemDepEntry
Memory dependence entries that track memory operations, marking when the instruction is ready to exec...
Definition: mem_dep_unit.hh:182
gem5::o3::MemDepUnit::insertBarrier
void insertBarrier(const DynInstPtr &barr_inst)
Inserts a barrier instruction.
Definition: mem_dep_unit.cc:323
gem5::o3::MemDepUnit::MemDepEntry::squashed
bool squashed
If the instruction is squashed.
Definition: mem_dep_unit.hh:210
gem5::o3::MemDepUnit::MemDepUnitStats::MemDepUnitStats
MemDepUnitStats(statistics::Group *parent)
Definition: mem_dep_unit.cc:106
gem5::o3::InstructionQueue
A standard instruction queue class.
Definition: inst_queue.hh:98
gem5::SNHash
Definition: mem_dep_unit.hh:60
gem5::o3::MemDepUnit::~MemDepUnit
~MemDepUnit()
Frees up any memory allocated.
Definition: mem_dep_unit.cc:67
gem5::o3::MemDepUnit::completeInst
void completeInst(const DynInstPtr &inst)
Notifies completion of an instruction.
Definition: mem_dep_unit.cc:428
gem5::o3::MemDepUnit::squash
void squash(const InstSeqNum &squashed_num, ThreadID tid)
Squashes all instructions up until a given sequence number for a specific thread.
Definition: mem_dep_unit.cc:521
gem5::o3::MemDepUnit::MemDepUnitStats::conflictingStores
statistics::Scalar conflictingStores
Stat for number of conflicting stores that had to wait for a store.
Definition: mem_dep_unit.hh:278
gem5::o3::MemDepUnit::instList
std::list< DynInstPtr > instList[MaxThreads]
A list of all instructions in the memory dependence unit.
Definition: mem_dep_unit.hh:234
gem5::ArmISA::a
Bitfield< 8 > a
Definition: misc_types.hh:65
std::vector< MemDepEntryPtr >
gem5::o3::MemDepUnit::hasLoadBarrier
bool hasLoadBarrier() const
Is there an outstanding load barrier that loads must wait on.
Definition: mem_dep_unit.hh:253
gem5::o3::MemDepUnit::instsToReplay
std::list< DynInstPtr > instsToReplay
A list of all instructions that are going to be replayed.
Definition: mem_dep_unit.hh:237
gem5::o3::MemDepUnit
Memory dependency unit class.
Definition: mem_dep_unit.hh:90
gem5::o3::MemDepUnit::MemDepUnitStats::insertedLoads
statistics::Scalar insertedLoads
Stat for number of inserted loads.
Definition: mem_dep_unit.hh:270
gem5::o3::MemDepUnit::MemDepUnitStats
Definition: mem_dep_unit.hh:266
gem5::o3::MemDepUnit::storeBarrierSNs
std::unordered_set< InstSeqNum > storeBarrierSNs
Sequence numbers of outstanding store barriers.
Definition: mem_dep_unit.hh:250
gem5::o3::MemDepUnit::MemDepEntry::dependInsts
std::vector< MemDepEntryPtr > dependInsts
A vector of any dependent instructions.
Definition: mem_dep_unit.hh:201
gem5::RefCountingPtr< DynInst >
gem5::o3::MemDepUnit::issue
void issue(const DynInstPtr &inst)
Issues the given instruction.
Definition: mem_dep_unit.cc:582
store_set.hh
gem5::o3::MemDepUnit::id
int id
The thread id of this memory dependence unit.
Definition: mem_dep_unit.hh:265
gem5::o3::MemDepUnit::MemDepEntry::completed
bool completed
If the instruction is completed.
Definition: mem_dep_unit.hh:208
gem5::o3::StoreSet
Implements a store set predictor for determining if memory instructions are dependent upon each other...
Definition: store_set.hh:62
gem5::o3::MemDepUnit::stats
gem5::o3::MemDepUnit::MemDepUnitStats stats
gem5::o3::MemDepUnit::replay
void replay()
Replays all instructions that have been rescheduled by moving them to the ready list.
Definition: mem_dep_unit.cc:385
inst_seq.hh
gem5::o3::CPU
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:95
gem5::o3::MemDepUnit::setIQ
void setIQ(InstructionQueue *iq_ptr)
Sets the pointer to the IQ.
Definition: mem_dep_unit.cc:152
gem5::o3::MemDepUnit::moveToReady
void moveToReady(MemDepEntryPtr &ready_inst_entry)
Moves an entry to the ready list.
Definition: mem_dep_unit.cc:601
gem5::o3::MemDepUnit::isDrained
bool isDrained() const
Determine if we are drained.
Definition: mem_dep_unit.cc:120
gem5::o3::MemDepUnit::ListIt
std::list< DynInstPtr >::iterator ListIt
Definition: mem_dep_unit.hh:172
gem5::o3::MemDepUnit::loadBarrierSNs
std::unordered_set< InstSeqNum > loadBarrierSNs
Sequence numbers of outstanding load barriers.
Definition: mem_dep_unit.hh:247
gem5::o3::MemDepUnit::MemDepEntry::inst
DynInstPtr inst
The instruction being tracked.
Definition: mem_dep_unit.hh:195
statistics.hh
gem5::o3::MemDepUnit::nonSpecInstReady
void nonSpecInstReady(const DynInstPtr &inst)
Indicate that a non-speculative instruction is ready.
Definition: mem_dep_unit.cc:367
gem5::o3::MemDepUnit::violation
void violation(const DynInstPtr &store_inst, const DynInstPtr &violating_load)
Indicates an ordering violation between a store and a younger load.
Definition: mem_dep_unit.cc:571
gem5::o3::MemDepUnit::MemDepUnitStats::conflictingLoads
statistics::Scalar conflictingLoads
Stat for number of conflicting loads that had to wait for a store.
Definition: mem_dep_unit.hh:275
gem5::o3::MemDepUnit::MemDepEntryPtr
std::shared_ptr< MemDepEntry > MemDepEntryPtr
Definition: mem_dep_unit.hh:174
gem5::SNHash::operator()
size_t operator()(const InstSeqNum &seq_num) const
Definition: mem_dep_unit.hh:63
dyn_inst_ptr.hh
gem5::o3::MemDepUnit::MemDepEntry::name
std::string name() const
Returns the name of the memory dependence entry.
Definition: mem_dep_unit.hh:192
gem5::o3::MemDepUnit::wakeDependents
void wakeDependents(const DynInstPtr &inst)
Wakes any dependents of a memory instruction.
Definition: mem_dep_unit.cc:459
gem5::o3::MemDepUnit::findInHash
MemDepEntryPtr & findInHash(const DynInstConstPtr &inst)
Finds the memory dependence entry in the hash map.
Definition: mem_dep_unit.cc:591
gem5::o3::MaxThreads
static constexpr int MaxThreads
Definition: limits.hh:38
gem5::o3::MemDepUnit::regsReady
void regsReady(const DynInstPtr &inst)
Indicate that an instruction has its registers ready.
Definition: mem_dep_unit.cc:345
gem5::o3::MemDepUnit::dumpLists
void dumpLists()
Debugging function to dump the lists of instructions.
Definition: mem_dep_unit.cc:613
gem5::o3::MemDepUnit::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: mem_dep_unit.cc:132
gem5::o3::MemDepUnit::MemDepEntry::listIt
ListIt listIt
The iterator to the instruction's location inside the list.
Definition: mem_dep_unit.hh:198
gem5::o3::MemDepUnit::completed
void completed(const DynInstPtr &inst)
Completes a memory instruction.
Definition: mem_dep_unit.cc:405
gem5::o3::MemDepUnit::insertNonSpec
void insertNonSpec(const DynInstPtr &inst)
Inserts a non-speculative memory instruction.
Definition: mem_dep_unit.cc:301
gem5::o3::MemDepUnit::name
std::string name() const
Returns the name of the memory dependence unit.
Definition: mem_dep_unit.hh:106
gem5::o3::MemDepUnit::MemDepUnitStats::insertedStores
statistics::Scalar insertedStores
Stat for number of inserted stores.
Definition: mem_dep_unit.hh:272
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::o3::MemDepUnit::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: mem_dep_unit.cc:143
gem5::o3::MemDepUnit::memDepHash
MemDepHash memDepHash
A hash map of all memory dependence entries.
Definition: mem_dep_unit.hh:231
gem5::o3::MemDepUnit::MemDepUnit
MemDepUnit()
Empty constructor.
Definition: mem_dep_unit.cc:55
std::list
STL list class.
Definition: stl.hh:51
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::o3::MemDepUnit::MemDepHash
std::unordered_map< InstSeqNum, MemDepEntryPtr, SNHash > MemDepHash
Definition: mem_dep_unit.hh:226
limits.hh
gem5::o3::MemDepUnit::depPred
StoreSet depPred
The memory dependence predictor.
Definition: mem_dep_unit.hh:244
gem5::o3::MemDepUnit::init
void init(const O3CPUParams &params, ThreadID tid, CPU *cpu)
Initializes the unit with parameters and a thread id.
Definition: mem_dep_unit.cc:92
gem5::o3::MemDepUnit::MemDepHashIt
MemDepHash::iterator MemDepHashIt
Definition: mem_dep_unit.hh:228
gem5::o3::MemDepUnit::MemDepEntry::regsReady
bool regsReady
If the registers are ready or not.
Definition: mem_dep_unit.hh:204
gem5::o3::MemDepUnit::insert
void insert(const DynInstPtr &inst)
Inserts a memory instruction.
Definition: mem_dep_unit.cc:190
gem5::o3::MemDepUnit::MemDepEntry::MemDepEntry
MemDepEntry(const DynInstPtr &new_inst)
Constructs a memory dependence entry.
Definition: mem_dep_unit.cc:494
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::o3::MemDepUnit::_name
std::string _name
Definition: mem_dep_unit.hh:93
gem5::o3::MemDepUnit::reschedule
void reschedule(const DynInstPtr &inst)
Reschedules an instruction to be re-executed.
Definition: mem_dep_unit.cc:379

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