gem5  v21.1.0.2
Classes | Public Types | Public Member Functions | Public Attributes | Private Types | Private Member Functions | Private Attributes | List of all members
gem5::o3::InstructionQueue Class Reference

A standard instruction queue class. More...

#include <inst_queue.hh>

Classes

class  FUCompletion
 FU completion event class. More...
 
struct  IQIOStats
 
struct  IQStats
 
struct  ListOrderEntry
 Entry for the list age ordering by op class. More...
 
struct  PqCompare
 Struct for comparing entries to be added to the priority queue. More...
 

Public Types

typedef std::list< DynInstPtr >::iterator ListIt
 

Public Member Functions

 InstructionQueue (CPU *cpu_ptr, IEW *iew_ptr, const O3CPUParams &params)
 Constructs an IQ. More...
 
 ~InstructionQueue ()
 Destructs the IQ. More...
 
std::string name () const
 Returns the name of the IQ. More...
 
void resetState ()
 Resets all instruction queue state. More...
 
void setActiveThreads (std::list< ThreadID > *at_ptr)
 Sets active threads list. More...
 
void setIssueToExecuteQueue (TimeBuffer< IssueStruct > *i2eQueue)
 Sets the timer buffer between issue and execute. More...
 
void setTimeBuffer (TimeBuffer< TimeStruct > *tb_ptr)
 Sets the global time buffer. More...
 
bool isDrained () const
 Determine if we are drained. More...
 
void drainSanityCheck () const
 Perform sanity checks after a drain. More...
 
void takeOverFrom ()
 Takes over execution from another CPU's thread. More...
 
int entryAmount (ThreadID num_threads)
 Number of entries needed for given amount of threads. More...
 
void resetEntries ()
 Resets max entries for all threads. More...
 
unsigned numFreeEntries ()
 Returns total number of free entries. More...
 
unsigned numFreeEntries (ThreadID tid)
 Returns number of free entries for a thread. More...
 
bool isFull ()
 Returns whether or not the IQ is full. More...
 
bool isFull (ThreadID tid)
 Returns whether or not the IQ is full for a specific thread. More...
 
bool hasReadyInsts ()
 Returns if there are any ready instructions in the IQ. More...
 
void insert (const DynInstPtr &new_inst)
 Inserts a new instruction into the IQ. More...
 
void insertNonSpec (const DynInstPtr &new_inst)
 Inserts a new, non-speculative instruction into the IQ. More...
 
void insertBarrier (const DynInstPtr &barr_inst)
 Inserts a memory or write barrier into the IQ to make sure loads and stores are ordered properly. More...
 
DynInstPtr getInstToExecute ()
 Returns the oldest scheduled instruction, and removes it from the list of instructions waiting to execute. More...
 
DynInstPtr getDeferredMemInstToExecute ()
 Gets a memory instruction that was referred due to a delayed DTB translation if it is now ready to execute. More...
 
DynInstPtr getBlockedMemInstToExecute ()
 Gets a memory instruction that was blocked on the cache. More...
 
void recordProducer (const DynInstPtr &inst)
 Records the instruction as the producer of a register without adding it to the rest of the IQ. More...
 
void processFUCompletion (const DynInstPtr &inst, int fu_idx)
 Process FU completion event. More...
 
void scheduleReadyInsts ()
 Schedules ready instructions, adding the ready ones (oldest first) to the queue to execute. More...
 
void scheduleNonSpec (const InstSeqNum &inst)
 Schedules a single specific non-speculative instruction. More...
 
void commit (const InstSeqNum &inst, ThreadID tid=0)
 Commits all instructions up to and including the given sequence number, for a specific thread. More...
 
int wakeDependents (const DynInstPtr &completed_inst)
 Wakes all dependents of a completed instruction. More...
 
void addReadyMemInst (const DynInstPtr &ready_inst)
 Adds a ready memory instruction to the ready list. More...
 
void rescheduleMemInst (const DynInstPtr &resched_inst)
 Reschedules a memory instruction. More...
 
void replayMemInst (const DynInstPtr &replay_inst)
 Replays a memory instruction. More...
 
void deferMemInst (const DynInstPtr &deferred_inst)
 Defers a memory instruction when its DTB translation incurs a hw page table walk. More...
 
void blockMemInst (const DynInstPtr &blocked_inst)
 Defers a memory instruction when it is cache blocked. More...
 
void cacheUnblocked ()
 Notify instruction queue that a previous blockage has resolved. More...
 
void violation (const DynInstPtr &store, const DynInstPtr &faulting_load)
 Indicates an ordering violation between a store and a load. More...
 
void squash (ThreadID tid)
 Squashes instructions for a thread. More...
 
unsigned getCount (ThreadID tid)
 Returns the number of used entries for a thread. More...
 
void printInsts ()
 Debug function to print all instructions. More...
 

Public Attributes

gem5::o3::InstructionQueue::IQIOStats iqIOStats
 

Private Types

typedef std::priority_queue< DynInstPtr, std::vector< DynInstPtr >, PqCompareReadyInstQueue
 
typedef std::map< InstSeqNum, DynInstPtr >::iterator NonSpecMapIt
 
typedef std::list< ListOrderEntry >::iterator ListOrderIt
 

Private Member Functions

void doSquash (ThreadID tid)
 Does the actual squashing. More...
 
void addToOrderList (OpClass op_class)
 Add an op class to the age order list. More...
 
void moveToYoungerInst (ListOrderIt age_order_it)
 Called when the oldest instruction has been removed from a ready queue; this places that ready queue into the proper spot in the age order list. More...
 
bool addToDependents (const DynInstPtr &new_inst)
 Adds an instruction to the dependency graph, as a consumer. More...
 
void addToProducers (const DynInstPtr &new_inst)
 Adds an instruction to the dependency graph, as a producer. More...
 
void addIfReady (const DynInstPtr &inst)
 Moves an instruction to the ready queue if it is ready. More...
 
int countInsts ()
 Debugging function to count how many entries are in the IQ. More...
 
void dumpLists ()
 Debugging function to dump all the list sizes, as well as print out the list of nonspeculative instructions. More...
 
void dumpInsts ()
 Debugging function to dump out all instructions that are in the IQ. More...
 

Private Attributes

CPUcpu
 Pointer to the CPU. More...
 
memory::MemInterfacedcacheInterface
 Cache interface. More...
 
IEWiewStage
 Pointer to IEW stage. More...
 
MemDepUnit memDepUnit [MaxThreads]
 The memory dependence unit, which tracks/predicts memory dependences between instructions. More...
 
TimeBuffer< IssueStruct > * issueToExecuteQueue
 The queue to the execute stage. More...
 
TimeBuffer< TimeStruct > * timeBuffer
 The backwards time buffer. More...
 
TimeBuffer< TimeStruct >::wire fromCommit
 Wire to read information from timebuffer. More...
 
FUPoolfuPool
 Function unit pool. More...
 
std::list< DynInstPtrinstList [MaxThreads]
 List of all the instructions in the IQ (some of which may be issued). More...
 
std::list< DynInstPtrinstsToExecute
 List of instructions that are ready to be executed. More...
 
std::list< DynInstPtrdeferredMemInsts
 List of instructions waiting for their DTB translation to complete (hw page table walk in progress). More...
 
std::list< DynInstPtrblockedMemInsts
 List of instructions that have been cache blocked. More...
 
std::list< DynInstPtrretryMemInsts
 List of instructions that were cache blocked, but a retry has been seen since, so they can now be retried. More...
 
ReadyInstQueue readyInsts [Num_OpClasses]
 List of ready instructions, per op class. More...
 
std::map< InstSeqNum, DynInstPtrnonSpecInsts
 List of non-speculative instructions that will be scheduled once the IQ gets a signal from commit. More...
 
std::list< ListOrderEntrylistOrder
 List that contains the age order of the oldest instruction of each ready queue. More...
 
bool queueOnList [Num_OpClasses]
 Tracks if each ready queue is on the age order list. More...
 
ListOrderIt readyIt [Num_OpClasses]
 Iterators of each ready queue. More...
 
DependencyGraph< DynInstPtrdependGraph
 
SMTQueuePolicy iqPolicy
 IQ sharing policy for SMT. More...
 
ThreadID numThreads
 Number of Total Threads. More...
 
std::list< ThreadID > * activeThreads
 Pointer to list of active threads. More...
 
unsigned count [MaxThreads]
 Per Thread IQ count. More...
 
unsigned maxEntries [MaxThreads]
 Max IQ Entries Per Thread. More...
 
unsigned freeEntries
 Number of free IQ entries left. More...
 
unsigned numEntries
 The number of entries in the instruction queue. More...
 
unsigned totalWidth
 The total number of instructions that can be issued in one cycle. More...
 
unsigned numPhysRegs
 The number of physical registers in the CPU. More...
 
int wbOutstanding
 Number of instructions currently in flight to FUs. More...
 
Cycles commitToIEWDelay
 Delay between commit stage and the IQ. More...
 
InstSeqNum squashedSeqNum [MaxThreads]
 The sequence number of the squashed instruction. More...
 
std::vector< bool > regScoreboard
 A cache of the recently woken registers. More...
 
gem5::o3::InstructionQueue::IQStats iqStats
 

Detailed Description

A standard instruction queue class.

It holds ready instructions, in order, in seperate priority queues to facilitate the scheduling of instructions. The IQ uses a separate linked list to track dependencies. Similar to the rename map and the free list, it expects that floating point registers have their indices start after the integer registers (ie with 96 int and 96 fp registers, regs 0-95 are integer and 96-191 are fp). This remains true even for both logical and physical register indices. The IQ depends on the memory dependence unit to track when memory operations are ready in terms of ordering; register dependencies are tracked normally. Right now the IQ also handles the execution timing; this is mainly to allow back-to-back scheduling without requiring IEW to be able to peek into the IQ. At the end of the execution latency, the instruction is put into the queue to execute, where it will have the execute() function called on it.

Todo:
: Make IQ able to handle multiple FU pools.

Definition at line 98 of file inst_queue.hh.

Member Typedef Documentation

◆ ListIt

Definition at line 102 of file inst_queue.hh.

◆ ListOrderIt

Definition at line 385 of file inst_queue.hh.

◆ NonSpecMapIt

typedef std::map<InstSeqNum, DynInstPtr>::iterator gem5::o3::InstructionQueue::NonSpecMapIt
private

Definition at line 367 of file inst_queue.hh.

◆ ReadyInstQueue

Definition at line 351 of file inst_queue.hh.

Constructor & Destructor Documentation

◆ InstructionQueue()

gem5::o3::InstructionQueue::InstructionQueue ( CPU cpu_ptr,
IEW iew_ptr,
const O3CPUParams &  params 
)

◆ ~InstructionQueue()

gem5::o3::InstructionQueue::~InstructionQueue ( )

Destructs the IQ.

Definition at line 161 of file inst_queue.cc.

References gem5::cprintf(), and dependGraph.

Member Function Documentation

◆ addIfReady()

void gem5::o3::InstructionQueue::addIfReady ( const DynInstPtr inst)
private

Moves an instruction to the ready queue if it is ready.

Definition at line 1412 of file inst_queue.cc.

References addToOrderList(), DPRINTF, listOrder, memDepUnit, queueOnList, readyInsts, readyIt, and gem5::o3::MemDepUnit::regsReady().

Referenced by insert(), scheduleNonSpec(), and wakeDependents().

◆ addReadyMemInst()

void gem5::o3::InstructionQueue::addReadyMemInst ( const DynInstPtr ready_inst)

Adds a ready memory instruction to the ready list.

Definition at line 1063 of file inst_queue.cc.

References addToOrderList(), DPRINTF, listOrder, queueOnList, readyInsts, and readyIt.

Referenced by gem5::o3::MemDepUnit::moveToReady(), and scheduleReadyInsts().

◆ addToDependents()

bool gem5::o3::InstructionQueue::addToDependents ( const DynInstPtr new_inst)
private

Adds an instruction to the dependency graph, as a consumer.

Definition at line 1330 of file inst_queue.cc.

References gem5::PhysRegId::className(), dependGraph, DPRINTF, gem5::PhysRegId::flatIndex(), gem5::PhysRegId::index(), gem5::PhysRegId::isFixedMapping(), and regScoreboard.

Referenced by insert().

◆ addToOrderList()

void gem5::o3::InstructionQueue::addToOrderList ( OpClass  op_class)
private

◆ addToProducers()

void gem5::o3::InstructionQueue::addToProducers ( const DynInstPtr new_inst)
private

Adds an instruction to the dependency graph, as a producer.

Definition at line 1377 of file inst_queue.cc.

References gem5::PhysRegId::className(), dependGraph, gem5::PhysRegId::flatIndex(), gem5::PhysRegId::index(), gem5::PhysRegId::isFixedMapping(), panic, and regScoreboard.

Referenced by insert(), insertNonSpec(), and recordProducer().

◆ blockMemInst()

void gem5::o3::InstructionQueue::blockMemInst ( const DynInstPtr blocked_inst)

Defers a memory instruction when it is cache blocked.

Definition at line 1110 of file inst_queue.cc.

References blockedMemInsts, and DPRINTF.

Referenced by gem5::o3::IEW::blockMemInst().

◆ cacheUnblocked()

void gem5::o3::InstructionQueue::cacheUnblocked ( )

Notify instruction queue that a previous blockage has resolved.

Definition at line 1121 of file inst_queue.cc.

References blockedMemInsts, cpu, DPRINTF, retryMemInsts, and gem5::o3::CPU::wakeCPU().

Referenced by gem5::o3::IEW::cacheUnblocked().

◆ commit()

void gem5::o3::InstructionQueue::commit ( const InstSeqNum inst,
ThreadID  tid = 0 
)

Commits all instructions up to and including the given sequence number, for a specific thread.

Definition at line 945 of file inst_queue.cc.

References countInsts(), DPRINTF, freeEntries, instList, and numEntries.

Referenced by gem5::o3::IEW::tick().

◆ countInsts()

int gem5::o3::InstructionQueue::countInsts ( )
private

Debugging function to count how many entries are in the IQ.

It does a linear walk through the instructions, so do not call this function during normal execution.

Definition at line 1451 of file inst_queue.cc.

References freeEntries, and numEntries.

Referenced by commit(), insert(), and insertNonSpec().

◆ deferMemInst()

void gem5::o3::InstructionQueue::deferMemInst ( const DynInstPtr deferred_inst)

Defers a memory instruction when its DTB translation incurs a hw page table walk.

Definition at line 1104 of file inst_queue.cc.

References deferredMemInsts.

Referenced by gem5::o3::IEW::executeInsts().

◆ doSquash()

void gem5::o3::InstructionQueue::doSquash ( ThreadID  tid)
private

◆ drainSanityCheck()

void gem5::o3::InstructionQueue::drainSanityCheck ( ) const

Perform sanity checks after a drain.

Definition at line 461 of file inst_queue.cc.

References dependGraph, instsToExecute, memDepUnit, and numThreads.

Referenced by gem5::o3::IEW::drainSanityCheck().

◆ dumpInsts()

void gem5::o3::InstructionQueue::dumpInsts ( )
private

Debugging function to dump out all instructions that are in the IQ.

Definition at line 1499 of file inst_queue.cc.

References gem5::cprintf(), instList, instsToExecute, and numThreads.

◆ dumpLists()

void gem5::o3::InstructionQueue::dumpLists ( )
private

Debugging function to dump all the list sizes, as well as print out the list of nonspeculative instructions.

Should not be used in any other capacity, but it has no harmful sideaffects.

Definition at line 1457 of file inst_queue.cc.

References gem5::cprintf(), gem5::ArmISA::i, listOrder, nonSpecInsts, gem5::Num_OpClasses, and readyInsts.

◆ entryAmount()

int gem5::o3::InstructionQueue::entryAmount ( ThreadID  num_threads)

Number of entries needed for given amount of threads.

Definition at line 476 of file inst_queue.cc.

References iqPolicy, and numEntries.

◆ getBlockedMemInstToExecute()

DynInstPtr gem5::o3::InstructionQueue::getBlockedMemInstToExecute ( )

Gets a memory instruction that was blocked on the cache.

NULL if none available.

Definition at line 1145 of file inst_queue.cc.

References retryMemInsts.

Referenced by scheduleReadyInsts().

◆ getCount()

unsigned gem5::o3::InstructionQueue::getCount ( ThreadID  tid)
inline

Returns the number of used entries for a thread.

Definition at line 274 of file inst_queue.hh.

References count.

Referenced by gem5::o3::CPU::removeThread(), and gem5::o3::IEW::tick().

◆ getDeferredMemInstToExecute()

DynInstPtr gem5::o3::InstructionQueue::getDeferredMemInstToExecute ( )

Gets a memory instruction that was referred due to a delayed DTB translation if it is now ready to execute.

NULL if none available.

Definition at line 1131 of file inst_queue.cc.

References deferredMemInsts.

Referenced by scheduleReadyInsts().

◆ getInstToExecute()

DynInstPtr gem5::o3::InstructionQueue::getInstToExecute ( )

Returns the oldest scheduled instruction, and removes it from the list of instructions waiting to execute.

Definition at line 658 of file inst_queue.cc.

References gem5::o3::InstructionQueue::IQIOStats::fpInstQueueReads, instsToExecute, gem5::o3::InstructionQueue::IQIOStats::intInstQueueReads, iqIOStats, and gem5::o3::InstructionQueue::IQIOStats::vecInstQueueReads.

Referenced by gem5::o3::IEW::executeInsts().

◆ hasReadyInsts()

bool gem5::o3::InstructionQueue::hasReadyInsts ( )

Returns if there are any ready instructions in the IQ.

Definition at line 543 of file inst_queue.cc.

References gem5::ArmISA::i, listOrder, gem5::Num_OpClasses, and readyInsts.

Referenced by gem5::o3::IEW::tick(), and gem5::o3::IEW::updateStatus().

◆ insert()

void gem5::o3::InstructionQueue::insert ( const DynInstPtr new_inst)

◆ insertBarrier()

void gem5::o3::InstructionQueue::insertBarrier ( const DynInstPtr barr_inst)

Inserts a memory or write barrier into the IQ to make sure loads and stores are ordered properly.

Definition at line 650 of file inst_queue.cc.

References gem5::o3::MemDepUnit::insertBarrier(), insertNonSpec(), and memDepUnit.

Referenced by gem5::o3::IEW::dispatchInsts().

◆ insertNonSpec()

void gem5::o3::InstructionQueue::insertNonSpec ( const DynInstPtr new_inst)

◆ isDrained()

bool gem5::o3::InstructionQueue::isDrained ( ) const

Determine if we are drained.

Definition at line 449 of file inst_queue.cc.

References dependGraph, instsToExecute, memDepUnit, numThreads, and wbOutstanding.

Referenced by gem5::o3::IEW::isDrained().

◆ isFull() [1/2]

bool gem5::o3::InstructionQueue::isFull ( )

Returns whether or not the IQ is full.

Definition at line 523 of file inst_queue.cc.

References freeEntries.

Referenced by gem5::o3::IEW::checkStall(), and gem5::o3::IEW::dispatchInsts().

◆ isFull() [2/2]

bool gem5::o3::InstructionQueue::isFull ( ThreadID  tid)

Returns whether or not the IQ is full for a specific thread.

Definition at line 533 of file inst_queue.cc.

References numFreeEntries().

◆ moveToYoungerInst()

void gem5::o3::InstructionQueue::moveToYoungerInst ( ListOrderIt  age_order_it)
private

Called when the oldest instruction has been removed from a ready queue; this places that ready queue into the proper spot in the age order list.

Definition at line 700 of file inst_queue.cc.

References listOrder, gem5::o3::InstructionQueue::ListOrderEntry::oldestInst, gem5::o3::InstructionQueue::ListOrderEntry::queueType, readyInsts, and readyIt.

Referenced by scheduleReadyInsts().

◆ name()

std::string gem5::o3::InstructionQueue::name ( ) const

Returns the name of the IQ.

Definition at line 171 of file inst_queue.cc.

References cpu, and gem5::Named::name().

◆ numFreeEntries() [1/2]

unsigned gem5::o3::InstructionQueue::numFreeEntries ( )

◆ numFreeEntries() [2/2]

unsigned gem5::o3::InstructionQueue::numFreeEntries ( ThreadID  tid)

Returns number of free entries for a thread.

Definition at line 515 of file inst_queue.cc.

References count, and maxEntries.

◆ printInsts()

void gem5::o3::InstructionQueue::printInsts ( )

Debug function to print all instructions.

◆ processFUCompletion()

void gem5::o3::InstructionQueue::processFUCompletion ( const DynInstPtr inst,
int  fu_idx 
)

◆ recordProducer()

void gem5::o3::InstructionQueue::recordProducer ( const DynInstPtr inst)
inline

Records the instruction as the producer of a register without adding it to the rest of the IQ.

Definition at line 214 of file inst_queue.hh.

References addToProducers().

Referenced by gem5::o3::IEW::dispatchInsts().

◆ replayMemInst()

void gem5::o3::InstructionQueue::replayMemInst ( const DynInstPtr replay_inst)

Replays a memory instruction.

It must be rescheduled first.

Definition at line 1098 of file inst_queue.cc.

References memDepUnit, and gem5::o3::MemDepUnit::replay().

Referenced by gem5::o3::IEW::replayMemInst(), and gem5::o3::IEW::tick().

◆ rescheduleMemInst()

void gem5::o3::InstructionQueue::rescheduleMemInst ( const DynInstPtr resched_inst)

Reschedules a memory instruction.

It will be ready to issue once replayMemInst() is called.

Definition at line 1085 of file inst_queue.cc.

References DPRINTF, memDepUnit, and gem5::o3::MemDepUnit::reschedule().

Referenced by gem5::o3::IEW::rescheduleMemInst().

◆ resetEntries()

void gem5::o3::InstructionQueue::resetEntries ( )

Resets max entries for all threads.

Definition at line 487 of file inst_queue.cc.

References activeThreads, iqPolicy, maxEntries, numEntries, and numThreads.

◆ resetState()

void gem5::o3::InstructionQueue::resetState ( )

◆ scheduleNonSpec()

void gem5::o3::InstructionQueue::scheduleNonSpec ( const InstSeqNum inst)

Schedules a single specific non-speculative instruction.

Definition at line 918 of file inst_queue.cc.

References addIfReady(), DPRINTF, memDepUnit, gem5::o3::MemDepUnit::nonSpecInstReady(), and nonSpecInsts.

Referenced by gem5::o3::IEW::tick().

◆ scheduleReadyInsts()

void gem5::o3::InstructionQueue::scheduleReadyInsts ( )

Schedules ready instructions, adding the ready ones (oldest first) to the queue to execute.

Definition at line 748 of file inst_queue.cc.

References gem5::o3::CPU::activityThisCycle(), addReadyMemInst(), gem5::Clocked::clockEdge(), count, cpu, gem5::curTick(), deferredMemInsts, DPRINTF, gem5::o3::InstructionQueue::IQIOStats::fpAluAccesses, gem5::o3::InstructionQueue::IQIOStats::fpInstQueueReads, freeEntries, gem5::o3::FUPool::freeUnitNextCycle(), gem5::o3::InstructionQueue::IQStats::fuBusy, fuPool, getBlockedMemInstToExecute(), getDeferredMemInstToExecute(), gem5::o3::FUPool::getOpLatency(), gem5::o3::FUPool::getUnit(), gem5::o3::InstructionQueue::IQStats::instsIssued, instsToExecute, gem5::o3::InstructionQueue::IQIOStats::intAluAccesses, gem5::o3::InstructionQueue::IQIOStats::intInstQueueReads, iqIOStats, iqStats, gem5::o3::FUPool::isPipelined(), gem5::o3::MemDepUnit::issue(), issueToExecuteQueue, listOrder, memDepUnit, moveToYoungerInst(), gem5::o3::FUPool::NoCapableFU, gem5::o3::FUPool::NoFreeFU, gem5::o3::InstructionQueue::IQStats::numIssuedDist, queueOnList, readyInsts, readyIt, retryMemInsts, gem5::statistics::DistBase< Derived, Stor >::sample(), gem5::EventManager::schedule(), gem5::o3::InstructionQueue::FUCompletion::setFreeFU(), gem5::o3::IssueStruct::size, gem5::o3::InstructionQueue::IQStats::squashedInstsIssued, gem5::o3::InstructionQueue::IQStats::statFuBusy, gem5::o3::InstructionQueue::IQStats::statIssuedInstType, totalWidth, gem5::o3::InstructionQueue::IQIOStats::vecAluAccesses, gem5::o3::InstructionQueue::IQIOStats::vecInstQueueReads, and wbOutstanding.

Referenced by gem5::o3::IEW::tick().

◆ setActiveThreads()

void gem5::o3::InstructionQueue::setActiveThreads ( std::list< ThreadID > *  at_ptr)

Sets active threads list.

Definition at line 429 of file inst_queue.cc.

References activeThreads.

Referenced by gem5::o3::IEW::setActiveThreads().

◆ setIssueToExecuteQueue()

void gem5::o3::InstructionQueue::setIssueToExecuteQueue ( TimeBuffer< IssueStruct > *  i2eQueue)

Sets the timer buffer between issue and execute.

Definition at line 435 of file inst_queue.cc.

References issueToExecuteQueue.

Referenced by gem5::o3::IEW::IEW().

◆ setTimeBuffer()

void gem5::o3::InstructionQueue::setTimeBuffer ( TimeBuffer< TimeStruct > *  tb_ptr)

Sets the global time buffer.

Definition at line 441 of file inst_queue.cc.

References commitToIEWDelay, fromCommit, and timeBuffer.

Referenced by gem5::o3::IEW::setTimeBuffer().

◆ squash()

void gem5::o3::InstructionQueue::squash ( ThreadID  tid)

Squashes instructions for a thread.

Squashing information is obtained from the time buffer.

Definition at line 1165 of file inst_queue.cc.

References doSquash(), DPRINTF, fromCommit, memDepUnit, gem5::o3::MemDepUnit::squash(), and squashedSeqNum.

Referenced by gem5::o3::IEW::squash().

◆ takeOverFrom()

void gem5::o3::InstructionQueue::takeOverFrom ( )

Takes over execution from another CPU's thread.

Definition at line 470 of file inst_queue.cc.

References resetState().

Referenced by gem5::o3::IEW::takeOverFrom().

◆ violation()

void gem5::o3::InstructionQueue::violation ( const DynInstPtr store,
const DynInstPtr faulting_load 
)

Indicates an ordering violation between a store and a load.

Definition at line 1157 of file inst_queue.cc.

References gem5::o3::InstructionQueue::IQIOStats::intInstQueueWrites, iqIOStats, memDepUnit, and gem5::o3::MemDepUnit::violation().

Referenced by gem5::o3::IEW::executeInsts().

◆ wakeDependents()

int gem5::o3::InstructionQueue::wakeDependents ( const DynInstPtr completed_inst)

Member Data Documentation

◆ activeThreads

std::list<ThreadID>* gem5::o3::InstructionQueue::activeThreads
private

Pointer to list of active threads.

Definition at line 417 of file inst_queue.hh.

Referenced by resetEntries(), and setActiveThreads().

◆ blockedMemInsts

std::list<DynInstPtr> gem5::o3::InstructionQueue::blockedMemInsts
private

List of instructions that have been cache blocked.

Definition at line 331 of file inst_queue.hh.

Referenced by blockMemInst(), cacheUnblocked(), and resetState().

◆ commitToIEWDelay

Cycles gem5::o3::InstructionQueue::commitToIEWDelay
private

Delay between commit stage and the IQ.

Todo:
: Make there be a distinction between the delays within IEW.

Definition at line 443 of file inst_queue.hh.

Referenced by setTimeBuffer().

◆ count

unsigned gem5::o3::InstructionQueue::count[MaxThreads]
private

Per Thread IQ count.

Definition at line 420 of file inst_queue.hh.

Referenced by doSquash(), getCount(), insert(), insertNonSpec(), numFreeEntries(), resetState(), scheduleReadyInsts(), and wakeDependents().

◆ cpu

CPU* gem5::o3::InstructionQueue::cpu
private

◆ dcacheInterface

memory::MemInterface* gem5::o3::InstructionQueue::dcacheInterface
private

Cache interface.

Definition at line 291 of file inst_queue.hh.

◆ deferredMemInsts

std::list<DynInstPtr> gem5::o3::InstructionQueue::deferredMemInsts
private

List of instructions waiting for their DTB translation to complete (hw page table walk in progress).

Definition at line 328 of file inst_queue.hh.

Referenced by deferMemInst(), getDeferredMemInstToExecute(), resetState(), and scheduleReadyInsts().

◆ dependGraph

DependencyGraph<DynInstPtr> gem5::o3::InstructionQueue::dependGraph
private

◆ freeEntries

unsigned gem5::o3::InstructionQueue::freeEntries
private

Number of free IQ entries left.

Definition at line 426 of file inst_queue.hh.

Referenced by commit(), countInsts(), doSquash(), insert(), insertNonSpec(), isFull(), numFreeEntries(), resetState(), scheduleReadyInsts(), and wakeDependents().

◆ fromCommit

TimeBuffer<TimeStruct>::wire gem5::o3::InstructionQueue::fromCommit
private

Wire to read information from timebuffer.

Definition at line 310 of file inst_queue.hh.

Referenced by setTimeBuffer(), and squash().

◆ fuPool

FUPool* gem5::o3::InstructionQueue::fuPool
private

Function unit pool.

Definition at line 313 of file inst_queue.hh.

Referenced by InstructionQueue(), processFUCompletion(), and scheduleReadyInsts().

◆ iewStage

IEW* gem5::o3::InstructionQueue::iewStage
private

Pointer to IEW stage.

Definition at line 294 of file inst_queue.hh.

Referenced by processFUCompletion().

◆ instList

std::list<DynInstPtr> gem5::o3::InstructionQueue::instList[MaxThreads]
private

List of all the instructions in the IQ (some of which may be issued).

Definition at line 320 of file inst_queue.hh.

Referenced by commit(), doSquash(), dumpInsts(), insert(), insertNonSpec(), and resetState().

◆ instsToExecute

std::list<DynInstPtr> gem5::o3::InstructionQueue::instsToExecute
private

List of instructions that are ready to be executed.

Definition at line 323 of file inst_queue.hh.

Referenced by drainSanityCheck(), dumpInsts(), getInstToExecute(), isDrained(), processFUCompletion(), and scheduleReadyInsts().

◆ iqIOStats

gem5::o3::InstructionQueue::IQIOStats gem5::o3::InstructionQueue::iqIOStats

◆ iqPolicy

SMTQueuePolicy gem5::o3::InstructionQueue::iqPolicy
private

IQ sharing policy for SMT.

Definition at line 411 of file inst_queue.hh.

Referenced by entryAmount(), InstructionQueue(), and resetEntries().

◆ iqStats

gem5::o3::InstructionQueue::IQStats gem5::o3::InstructionQueue::iqStats
private

◆ issueToExecuteQueue

TimeBuffer<IssueStruct>* gem5::o3::InstructionQueue::issueToExecuteQueue
private

The queue to the execute stage.

Issued instructions will be written into it.

Definition at line 304 of file inst_queue.hh.

Referenced by processFUCompletion(), scheduleReadyInsts(), and setIssueToExecuteQueue().

◆ listOrder

std::list<ListOrderEntry> gem5::o3::InstructionQueue::listOrder
private

List that contains the age order of the oldest instruction of each ready queue.

Used to select the oldest instruction available among op classes.

Todo:
: Might be better to just move these entries around instead of creating new ones every time the position changes due to an instruction issuing. Not sure std::list supports this.

Definition at line 383 of file inst_queue.hh.

Referenced by addIfReady(), addReadyMemInst(), addToOrderList(), dumpLists(), hasReadyInsts(), moveToYoungerInst(), resetState(), and scheduleReadyInsts().

◆ maxEntries

unsigned gem5::o3::InstructionQueue::maxEntries[MaxThreads]
private

Max IQ Entries Per Thread.

Definition at line 423 of file inst_queue.hh.

Referenced by InstructionQueue(), numFreeEntries(), and resetEntries().

◆ memDepUnit

MemDepUnit gem5::o3::InstructionQueue::memDepUnit[MaxThreads]
private

The memory dependence unit, which tracks/predicts memory dependences between instructions.

Definition at line 299 of file inst_queue.hh.

Referenced by addIfReady(), drainSanityCheck(), insert(), insertBarrier(), insertNonSpec(), InstructionQueue(), isDrained(), replayMemInst(), rescheduleMemInst(), scheduleNonSpec(), scheduleReadyInsts(), squash(), violation(), and wakeDependents().

◆ nonSpecInsts

std::map<InstSeqNum, DynInstPtr> gem5::o3::InstructionQueue::nonSpecInsts
private

List of non-speculative instructions that will be scheduled once the IQ gets a signal from commit.

While it's redundant to have the key be a part of the value (the sequence number is stored inside of DynInst), when these instructions are woken up only the sequence number will be available. Thus it is most efficient to be able to search by the sequence number alone.

Definition at line 365 of file inst_queue.hh.

Referenced by doSquash(), dumpLists(), insertNonSpec(), resetState(), and scheduleNonSpec().

◆ numEntries

unsigned gem5::o3::InstructionQueue::numEntries
private

The number of entries in the instruction queue.

Definition at line 429 of file inst_queue.hh.

Referenced by commit(), countInsts(), entryAmount(), insert(), insertNonSpec(), InstructionQueue(), resetEntries(), and resetState().

◆ numPhysRegs

unsigned gem5::o3::InstructionQueue::numPhysRegs
private

The number of physical registers in the CPU.

Definition at line 435 of file inst_queue.hh.

Referenced by InstructionQueue(), and resetState().

◆ numThreads

ThreadID gem5::o3::InstructionQueue::numThreads
private

Number of Total Threads.

Definition at line 414 of file inst_queue.hh.

Referenced by drainSanityCheck(), dumpInsts(), InstructionQueue(), isDrained(), and resetEntries().

◆ queueOnList

bool gem5::o3::InstructionQueue::queueOnList[Num_OpClasses]
private

Tracks if each ready queue is on the age order list.

Definition at line 388 of file inst_queue.hh.

Referenced by addIfReady(), addReadyMemInst(), addToOrderList(), resetState(), and scheduleReadyInsts().

◆ readyInsts

ReadyInstQueue gem5::o3::InstructionQueue::readyInsts[Num_OpClasses]
private

List of ready instructions, per op class.

They are separated by op class to allow for easy mapping to FUs.

Definition at line 356 of file inst_queue.hh.

Referenced by addIfReady(), addReadyMemInst(), addToOrderList(), dumpLists(), hasReadyInsts(), moveToYoungerInst(), resetState(), and scheduleReadyInsts().

◆ readyIt

ListOrderIt gem5::o3::InstructionQueue::readyIt[Num_OpClasses]
private

Iterators of each ready queue.

Points to their spot in the age order list.

Definition at line 393 of file inst_queue.hh.

Referenced by addIfReady(), addReadyMemInst(), addToOrderList(), moveToYoungerInst(), resetState(), and scheduleReadyInsts().

◆ regScoreboard

std::vector<bool> gem5::o3::InstructionQueue::regScoreboard
private

A cache of the recently woken registers.

It is 1 if the register has been woken up recently, and 0 if the register has been added to the dependency graph and has not yet received its value. It is basically a secondary scoreboard, and should pretty much mirror the scoreboard that exists in the rename map.

Definition at line 454 of file inst_queue.hh.

Referenced by addToDependents(), addToProducers(), InstructionQueue(), resetState(), and wakeDependents().

◆ retryMemInsts

std::list<DynInstPtr> gem5::o3::InstructionQueue::retryMemInsts
private

List of instructions that were cache blocked, but a retry has been seen since, so they can now be retried.

May fail again go on the blocked list.

Definition at line 336 of file inst_queue.hh.

Referenced by cacheUnblocked(), getBlockedMemInstToExecute(), resetState(), and scheduleReadyInsts().

◆ squashedSeqNum

InstSeqNum gem5::o3::InstructionQueue::squashedSeqNum[MaxThreads]
private

The sequence number of the squashed instruction.

Definition at line 446 of file inst_queue.hh.

Referenced by doSquash(), resetState(), and squash().

◆ timeBuffer

TimeBuffer<TimeStruct>* gem5::o3::InstructionQueue::timeBuffer
private

The backwards time buffer.

Definition at line 307 of file inst_queue.hh.

Referenced by setTimeBuffer().

◆ totalWidth

unsigned gem5::o3::InstructionQueue::totalWidth
private

The total number of instructions that can be issued in one cycle.

Definition at line 432 of file inst_queue.hh.

Referenced by scheduleReadyInsts().

◆ wbOutstanding

int gem5::o3::InstructionQueue::wbOutstanding
private

Number of instructions currently in flight to FUs.

Definition at line 438 of file inst_queue.hh.

Referenced by isDrained(), processFUCompletion(), resetState(), and scheduleReadyInsts().


The documentation for this class was generated from the following files:

Generated on Tue Sep 21 2021 12:31:45 for gem5 by doxygen 1.8.17