gem5  v21.1.0.2
kernel_code.hh
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33 
34 #ifndef __GPU_COMPUTE_KERNEL_CODE_HH__
35 #define __GPU_COMPUTE_KERNEL_CODE_HH__
36 
37 #include <bitset>
38 #include <cstdint>
39 
40 namespace gem5
41 {
42 
57 {
60  QueuePtr = 2,
74 };
75 
77 {
82 };
83 
85 {
88  uint16_t amd_machine_kind;
96 
107  // the 32b below here represent the fields of
108  // the COMPUTE_PGM_RSRC1 register
111  uint32_t priority : 2;
112  uint32_t float_mode_round_32 : 2;
114  uint32_t float_mode_denorm_32 : 2;
116  uint32_t priv : 1;
117  uint32_t enable_dx10_clamp : 1;
118  uint32_t debug_mode : 1;
119  uint32_t enable_ieee_mode : 1;
120  uint32_t bulky : 1;
121  uint32_t cdbg_user : 1;
123  // end COMPUTE_PGM_RSRC1 register
124 
125  // the 32b below here represent the fields of
126  // the COMPUTE_PGM_RSRC2 register
128  uint32_t user_sgpr_count : 5;
129  uint32_t enable_trap_handler : 1;
137  uint32_t granulated_lds_size : 9;
146  // end COMPUTE_PGM_RSRC2
147 
148  // the 32b below here represent the fields of
149  // KERNEL_CODE_PROPERTIES
152  uint32_t enable_sgpr_queue_ptr : 1;
162  uint32_t private_element_size : 2;
163  uint32_t is_ptr64 : 1;
164  uint32_t is_dynamic_callstack : 1;
165  uint32_t is_debug_enabled : 1;
166  uint32_t is_xnack_enabled : 1;
168  // end KERNEL_CODE_PROPERTIES
169 
186  uint8_t wavefront_size;
188  uint8_t reserved[12];
190  uint64_t control_directives[16];
191 };
192 
193 } // namespace gem5
194 
195 #endif // __GPU_COMPUTE_KERNEL_CODE_HH__
gem5::NumVectorInitFields
@ NumVectorInitFields
Definition: kernel_code.hh:81
gem5::FlatScratchInit
@ FlatScratchInit
Definition: kernel_code.hh:63
gem5::AMDKernelCode::runtime_loader_kernel_symbol
uint64_t runtime_loader_kernel_symbol
Definition: kernel_code.hh:189
gem5::AMDKernelCode::bulky
uint32_t bulky
Definition: kernel_code.hh:120
gem5::AMDKernelCode::debug_private_segment_buffer_sgpr
uint16_t debug_private_segment_buffer_sgpr
Definition: kernel_code.hh:182
gem5::AMDKernelCode::amd_kernel_code_version_major
uint32_t amd_kernel_code_version_major
Definition: kernel_code.hh:86
gem5::AMDKernelCode::debug_wavefront_private_segment_offset_sgpr
uint16_t debug_wavefront_private_segment_offset_sgpr
Definition: kernel_code.hh:181
gem5::AMDKernelCode::compute_pgm_rsrc2_reserved
uint32_t compute_pgm_rsrc2_reserved
Definition: kernel_code.hh:145
gem5::AMDKernelCode::enable_vgpr_workitem_id
uint32_t enable_vgpr_workitem_id
Definition: kernel_code.hh:134
gem5::WorkitemIdY
@ WorkitemIdY
Definition: kernel_code.hh:79
gem5::AMDKernelCode::user_sgpr_count
uint32_t user_sgpr_count
Definition: kernel_code.hh:128
gem5::AMDKernelCode::enable_trap_handler
uint32_t enable_trap_handler
Definition: kernel_code.hh:129
gem5::AMDKernelCode::enable_sgpr_workgroup_id_x
uint32_t enable_sgpr_workgroup_id_x
Definition: kernel_code.hh:130
gem5::PrivateSegBuf
@ PrivateSegBuf
Definition: kernel_code.hh:58
gem5::AMDKernelCode::enable_sgpr_dispatch_id
uint32_t enable_sgpr_dispatch_id
Definition: kernel_code.hh:154
gem5::AMDKernelCode::workgroup_group_segment_byte_size
uint32_t workgroup_group_segment_byte_size
Definition: kernel_code.hh:171
gem5::AMDKernelCode::enable_sgpr_grid_workgroup_count_z
uint32_t enable_sgpr_grid_workgroup_count_z
Definition: kernel_code.hh:159
gem5::AMDKernelCode::enable_exception_int_divide_by_zero
uint32_t enable_exception_int_divide_by_zero
Definition: kernel_code.hh:144
gem5::AMDKernelCode::enable_sgpr_dispatch_ptr
uint32_t enable_sgpr_dispatch_ptr
Definition: kernel_code.hh:151
gem5::AMDKernelCode::enable_sgpr_private_segment_wave_byte_offset
uint32_t enable_sgpr_private_segment_wave_byte_offset
Definition: kernel_code.hh:127
gem5::AMDKernelCode::max_scratch_backing_memory_byte_size
uint64_t max_scratch_backing_memory_byte_size
Definition: kernel_code.hh:95
gem5::AMDKernelCode::enable_exception_ieee_754_fp_division_by_zero
uint32_t enable_exception_ieee_754_fp_division_by_zero
Definition: kernel_code.hh:140
gem5::AMDKernelCode::enable_sgpr_workgroup_id_z
uint32_t enable_sgpr_workgroup_id_z
Definition: kernel_code.hh:132
gem5::AMDKernelCode::group_segment_alignment
uint8_t group_segment_alignment
Definition: kernel_code.hh:184
gem5::AMDKernelCode::enable_exception_memory_violation
uint32_t enable_exception_memory_violation
Definition: kernel_code.hh:136
gem5::WorkgroupInfo
@ WorkgroupInfo
Definition: kernel_code.hh:71
gem5::AMDKernelCode::enable_sgpr_private_segment_buffer
uint32_t enable_sgpr_private_segment_buffer
Definition: kernel_code.hh:150
gem5::AMDKernelCode::float_mode_round_32
uint32_t float_mode_round_32
Definition: kernel_code.hh:112
gem5::AMDKernelCode::granulated_lds_size
uint32_t granulated_lds_size
Definition: kernel_code.hh:137
gem5::PrivSegWaveByteOffset
@ PrivSegWaveByteOffset
Definition: kernel_code.hh:72
gem5::AMDKernelCode::amd_kernel_code_version_minor
uint32_t amd_kernel_code_version_minor
Definition: kernel_code.hh:87
gem5::NumScalarInitFields
@ NumScalarInitFields
Definition: kernel_code.hh:73
gem5::AMDKernelCode::wavefront_sgpr_count
uint16_t wavefront_sgpr_count
Definition: kernel_code.hh:175
gem5::AMDKernelCode::enable_sgpr_private_segment_size
uint32_t enable_sgpr_private_segment_size
Definition: kernel_code.hh:156
gem5::VectorRegInitFields
VectorRegInitFields
Definition: kernel_code.hh:76
gem5::AMDKernelCode::enable_exception_ieee_754_fp_overflow
uint32_t enable_exception_ieee_754_fp_overflow
Definition: kernel_code.hh:141
gem5::WorkgroupIdY
@ WorkgroupIdY
Definition: kernel_code.hh:69
gem5::WorkgroupIdZ
@ WorkgroupIdZ
Definition: kernel_code.hh:70
gem5::PrivateSegSize
@ PrivateSegSize
Definition: kernel_code.hh:64
gem5::AMDKernelCode::reserved_sgpr_first
uint16_t reserved_sgpr_first
Definition: kernel_code.hh:179
gem5::AMDKernelCode::debug_mode
uint32_t debug_mode
Definition: kernel_code.hh:118
gem5::AMDKernelCode::enable_sgpr_workgroup_info
uint32_t enable_sgpr_workgroup_info
Definition: kernel_code.hh:133
gem5::AMDKernelCode::amd_machine_version_minor
uint16_t amd_machine_version_minor
Definition: kernel_code.hh:90
gem5::WorkitemIdX
@ WorkitemIdX
Definition: kernel_code.hh:78
gem5::AMDKernelCode::enable_ordered_append_gds
uint32_t enable_ordered_append_gds
Definition: kernel_code.hh:161
gem5::AMDKernelCode::wavefront_size
uint8_t wavefront_size
Definition: kernel_code.hh:186
gem5::AMDKernelCode::enable_sgpr_flat_scratch_init
uint32_t enable_sgpr_flat_scratch_init
Definition: kernel_code.hh:155
gem5::AMDKernelCode::private_element_size
uint32_t private_element_size
Definition: kernel_code.hh:162
gem5::AMDKernelCode::enable_exception_ieee_754_fp_inexact
uint32_t enable_exception_ieee_754_fp_inexact
Definition: kernel_code.hh:143
gem5::AMDKernelCode::gds_segment_byte_size
uint32_t gds_segment_byte_size
Definition: kernel_code.hh:172
gem5::KernargSegPtr
@ KernargSegPtr
Definition: kernel_code.hh:61
gem5::AMDKernelCode::granulated_workitem_vgpr_count
uint32_t granulated_workitem_vgpr_count
The fields below are used to set program settings for compute shaders.
Definition: kernel_code.hh:109
gem5::AMDKernelCode::workgroup_fbarrier_count
uint32_t workgroup_fbarrier_count
Definition: kernel_code.hh:174
gem5::DispatchId
@ DispatchId
Definition: kernel_code.hh:62
gem5::AMDKernelCode::enable_sgpr_kernarg_segment_ptr
uint32_t enable_sgpr_kernarg_segment_ptr
Definition: kernel_code.hh:153
gem5::AMDKernelCode::float_mode_denorm_16_64
uint32_t float_mode_denorm_16_64
Definition: kernel_code.hh:115
gem5::AMDKernelCode::enable_exception_ieee_754_fp_invalid_operation
uint32_t enable_exception_ieee_754_fp_invalid_operation
Definition: kernel_code.hh:138
gem5::AMDKernelCode::kernel_code_prefetch_byte_offset
int64_t kernel_code_prefetch_byte_offset
Definition: kernel_code.hh:93
gem5::AMDKernelCode::amd_machine_kind
uint16_t amd_machine_kind
Definition: kernel_code.hh:88
gem5::AMDKernelCode::private_segment_alignment
uint8_t private_segment_alignment
Definition: kernel_code.hh:185
gem5::AMDKernelCode::enable_dx10_clamp
uint32_t enable_dx10_clamp
Definition: kernel_code.hh:117
gem5::AMDKernelCode::amd_machine_version_major
uint16_t amd_machine_version_major
Definition: kernel_code.hh:89
gem5::AMDKernelCode::is_debug_enabled
uint32_t is_debug_enabled
Definition: kernel_code.hh:165
gem5::AMDKernelCode::enable_sgpr_queue_ptr
uint32_t enable_sgpr_queue_ptr
Definition: kernel_code.hh:152
gem5::AMDKernelCode::kernarg_segment_alignment
uint8_t kernarg_segment_alignment
Definition: kernel_code.hh:183
gem5::AMDKernelCode::reserved_vgpr_count
uint16_t reserved_vgpr_count
Definition: kernel_code.hh:178
gem5::AMDKernelCode::priority
uint32_t priority
Definition: kernel_code.hh:111
gem5::AMDKernelCode::float_mode_denorm_32
uint32_t float_mode_denorm_32
Definition: kernel_code.hh:114
gem5::GridWorkgroupCountX
@ GridWorkgroupCountX
Definition: kernel_code.hh:65
gem5::AMDKernelCode::enable_exception_address_watch
uint32_t enable_exception_address_watch
Definition: kernel_code.hh:135
gem5::AMDKernelCode::kernel_code_prefetch_byte_size
uint64_t kernel_code_prefetch_byte_size
Definition: kernel_code.hh:94
gem5::AMDKernelCode::compute_pgm_rsrc1_reserved
uint32_t compute_pgm_rsrc1_reserved
Definition: kernel_code.hh:122
gem5::WorkitemIdZ
@ WorkitemIdZ
Definition: kernel_code.hh:80
gem5::GridWorkgroupCountZ
@ GridWorkgroupCountZ
Definition: kernel_code.hh:67
gem5::AMDKernelCode::control_directives
uint64_t control_directives[16]
Definition: kernel_code.hh:190
gem5::AMDKernelCode::kernel_code_properties_reserved2
uint32_t kernel_code_properties_reserved2
Definition: kernel_code.hh:167
gem5::AMDKernelCode::is_xnack_enabled
uint32_t is_xnack_enabled
Definition: kernel_code.hh:166
gem5::AMDKernelCode::enable_exception_ieee_754_fp_underflow
uint32_t enable_exception_ieee_754_fp_underflow
Definition: kernel_code.hh:142
gem5::AMDKernelCode::workitem_vgpr_count
uint16_t workitem_vgpr_count
Definition: kernel_code.hh:176
gem5::AMDKernelCode::enable_sgpr_workgroup_id_y
uint32_t enable_sgpr_workgroup_id_y
Definition: kernel_code.hh:131
gem5::AMDKernelCode::is_ptr64
uint32_t is_ptr64
Definition: kernel_code.hh:163
gem5::QueuePtr
@ QueuePtr
Definition: kernel_code.hh:60
gem5::AMDKernelCode::is_dynamic_callstack
uint32_t is_dynamic_callstack
Definition: kernel_code.hh:164
gem5::AMDKernelCode::float_mode_round_16_64
uint32_t float_mode_round_16_64
Definition: kernel_code.hh:113
gem5::WorkgroupIdX
@ WorkgroupIdX
Definition: kernel_code.hh:68
gem5::AMDKernelCode::priv
uint32_t priv
Definition: kernel_code.hh:116
gem5::AMDKernelCode::enable_exception_fp_denormal_source
uint32_t enable_exception_fp_denormal_source
Definition: kernel_code.hh:139
gem5::GridWorkgroupCountY
@ GridWorkgroupCountY
Definition: kernel_code.hh:66
gem5::DispatchPtr
@ DispatchPtr
Definition: kernel_code.hh:59
gem5::AMDKernelCode::reserved
uint8_t reserved[12]
Definition: kernel_code.hh:188
gem5::AMDKernelCode::granulated_wavefront_sgpr_count
uint32_t granulated_wavefront_sgpr_count
Definition: kernel_code.hh:110
gem5::AMDKernelCode::enable_ieee_mode
uint32_t enable_ieee_mode
Definition: kernel_code.hh:119
gem5::AMDKernelCode::enable_sgpr_grid_workgroup_count_y
uint32_t enable_sgpr_grid_workgroup_count_y
Definition: kernel_code.hh:158
gem5::AMDKernelCode::cdbg_user
uint32_t cdbg_user
Definition: kernel_code.hh:121
gem5::AMDKernelCode::reserved_vgpr_first
uint16_t reserved_vgpr_first
Definition: kernel_code.hh:177
gem5::AMDKernelCode::kernel_code_properties_reserved1
uint32_t kernel_code_properties_reserved1
Definition: kernel_code.hh:160
gem5::AMDKernelCode::kernel_code_entry_byte_offset
int64_t kernel_code_entry_byte_offset
Definition: kernel_code.hh:92
gem5::AMDKernelCode::amd_machine_version_stepping
uint16_t amd_machine_version_stepping
Definition: kernel_code.hh:91
gem5::AMDKernelCode::reserved_sgpr_count
uint16_t reserved_sgpr_count
Definition: kernel_code.hh:180
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::AMDKernelCode::workitem_private_segment_byte_size
uint32_t workitem_private_segment_byte_size
Definition: kernel_code.hh:170
gem5::AMDKernelCode::kernarg_segment_byte_size
uint64_t kernarg_segment_byte_size
Definition: kernel_code.hh:173
gem5::AMDKernelCode::enable_sgpr_grid_workgroup_count_x
uint32_t enable_sgpr_grid_workgroup_count_x
Definition: kernel_code.hh:157
gem5::ScalarRegInitFields
ScalarRegInitFields
these enums represent the indices into the initialRegState bitfields in HsaKernelInfo.
Definition: kernel_code.hh:56
gem5::AMDKernelCode
Definition: kernel_code.hh:84
gem5::AMDKernelCode::call_convention
int32_t call_convention
Definition: kernel_code.hh:187

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