gem5  v22.0.0.1
scoreboard.hh
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37 
44 #ifndef __CPU_MINOR_SCOREBOARD_HH__
45 #define __CPU_MINOR_SCOREBOARD_HH__
46 
47 #include <vector>
48 
49 #include "base/named.hh"
50 #include "base/types.hh"
51 #include "cpu/minor/cpu.hh"
52 #include "cpu/minor/dyn_inst.hh"
53 #include "cpu/minor/trace.hh"
54 #include "cpu/reg_class.hh"
55 
56 namespace gem5
57 {
58 
60 namespace minor
61 {
62 
66 class Scoreboard : public Named
67 {
68  public:
70 
71  const unsigned intRegOffset;
72  const unsigned floatRegOffset;
73  const unsigned ccRegOffset;
74  const unsigned vecRegOffset;
75  const unsigned vecPredRegOffset;
76 
83  const unsigned numRegs;
84 
86  typedef unsigned short int Index;
87 
91 
94 
97  static constexpr int invalidFUIndex = -1;
98 
104 
108 
109  public:
110  Scoreboard(const std::string &name,
111  const BaseISA::RegClasses& reg_classes) :
112  Named(name),
113  regClasses(reg_classes),
114  intRegOffset(0),
117  vecRegOffset(ccRegOffset + reg_classes.at(CCRegClass).numRegs()),
119  reg_classes.at(VecElemClass).numRegs()),
121  numResults(numRegs, 0),
125  writingInst(numRegs, 0)
126  { }
127 
128  public:
132  bool findIndex(const RegId& reg, Index &scoreboard_index);
133 
138  void markupInstDests(MinorDynInstPtr inst, Cycles retire_time,
139  ThreadContext *thread_context, bool mark_unpredictable);
140 
143  void clearInstDests(MinorDynInstPtr inst, bool clear_unpredictable);
144 
150  ThreadContext *thread_context);
151 
154  bool canInstIssue(MinorDynInstPtr inst,
155  const std::vector<Cycles> *src_reg_relative_latencies,
156  const std::vector<bool> *cant_forward_from_fu_indices,
157  Cycles now, ThreadContext *thread_context);
158 
160  void minorTrace() const;
161 };
162 
163 } // namespace minor
164 } // namespace gem5
165 
166 #endif /* __CPU_MINOR_SCOREBOARD_HH__ */
dyn_inst.hh
gem5::minor::Scoreboard::vecRegOffset
const unsigned vecRegOffset
Definition: scoreboard.hh:74
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:63
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:65
gem5::minor::Scoreboard::markupInstDests
void markupInstDests(MinorDynInstPtr inst, Cycles retire_time, ThreadContext *thread_context, bool mark_unpredictable)
Mark up an instruction's effects by incrementing numResults counts.
Definition: scoreboard.cc:100
named.hh
gem5::minor::Scoreboard::numUnpredictableResults
std::vector< Index > numUnpredictableResults
Count of the number of results which can't be predicted.
Definition: scoreboard.hh:93
cpu.hh
gem5::minor::Scoreboard::numRegs
const unsigned numRegs
The number of registers in the Scoreboard.
Definition: scoreboard.hh:83
minor
gem5::minor::Scoreboard::canInstIssue
bool canInstIssue(MinorDynInstPtr inst, const std::vector< Cycles > *src_reg_relative_latencies, const std::vector< bool > *cant_forward_from_fu_indices, Cycles now, ThreadContext *thread_context)
Can this instruction be issued.
Definition: scoreboard.cc:207
gem5::minor::Scoreboard::intRegOffset
const unsigned intRegOffset
Definition: scoreboard.hh:71
std::vector< RegClass >
gem5::minor::Scoreboard::numResults
std::vector< Index > numResults
Count of the number of in-flight instructions that have results for each register.
Definition: scoreboard.hh:90
gem5::minor::Scoreboard::regClasses
const BaseISA::RegClasses regClasses
Definition: scoreboard.hh:69
gem5::minor::Scoreboard::Scoreboard
Scoreboard(const std::string &name, const BaseISA::RegClasses &reg_classes)
Definition: scoreboard.hh:110
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:64
gem5::RefCountingPtr< MinorDynInst >
gem5::ArmISA::at
Bitfield< 35, 32 > at
Definition: misc_types.hh:155
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::Named
Interface for things with names.
Definition: named.hh:38
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:59
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::minor::Scoreboard::minorTrace
void minorTrace() const
MinorTraceIF interface.
Definition: scoreboard.cc:280
gem5::minor::Scoreboard::fuIndices
std::vector< int > fuIndices
Index of the FU generating this result.
Definition: scoreboard.hh:96
gem5::minor::Scoreboard::clearInstDests
void clearInstDests(MinorDynInstPtr inst, bool clear_unpredictable)
Clear down the dependencies for this instruction.
Definition: scoreboard.cc:172
gem5::minor::Scoreboard::findIndex
bool findIndex(const RegId &reg, Index &scoreboard_index)
Sets scoreboard_index to the index into numResults of the given register index.
Definition: scoreboard.cc:52
gem5::minor::Scoreboard::writingInst
std::vector< InstSeqNum > writingInst
The execute sequence number of the most recent inst to generate this register value.
Definition: scoreboard.hh:107
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::minor::Scoreboard::Index
unsigned short int Index
Type to use when indexing numResults.
Definition: scoreboard.hh:86
gem5::minor::Scoreboard::ccRegOffset
const unsigned ccRegOffset
Definition: scoreboard.hh:73
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::minor::Scoreboard
A scoreboard of register dependencies including, for each register: The number of in-flight instructi...
Definition: scoreboard.hh:66
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::minor::Scoreboard::returnCycle
std::vector< Cycles > returnCycle
The estimated cycle number that the result will be presented.
Definition: scoreboard.hh:103
types.hh
gem5::minor::Scoreboard::execSeqNumToWaitFor
InstSeqNum execSeqNumToWaitFor(MinorDynInstPtr inst, ThreadContext *thread_context)
Returns the exec sequence number of the most recent inst on which the given inst depends.
Definition: scoreboard.cc:143
gem5::minor::Scoreboard::invalidFUIndex
static constexpr int invalidFUIndex
Definition: scoreboard.hh:97
reg_class.hh
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
trace.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::minor::Scoreboard::vecPredRegOffset
const unsigned vecPredRegOffset
Definition: scoreboard.hh:75
gem5::minor::Scoreboard::floatRegOffset
const unsigned floatRegOffset
Definition: scoreboard.hh:72
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126

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