41 #include "debug/MinorScoreboard.hh"
42 #include "debug/MinorTiming.hh"
56 switch (
reg.classValue()) {
58 scoreboard_index =
reg.index();
86 panic(
"Unknown register class: %d",
reg.classValue());
100 unsigned int num_dests = staticInst->
numDestRegs();
105 for (
unsigned int dest_index = 0; dest_index < num_dests;
112 if (mark_unpredictable)
115 inst->flatDestRegIdx[dest_index] =
reg;
126 DPRINTF(MinorScoreboard,
"Marking up inst: %s"
127 " regIndex: %d final numResults: %d returnCycle: %d\n",
131 inst->flatDestRegIdx[dest_index] =
RegId();
146 unsigned int num_srcs = staticInst->
numSrcRegs();
150 for (
unsigned int src_index = 0; src_index < num_srcs; src_index++) {
152 unsigned short int index;
160 DPRINTF(MinorScoreboard,
"Inst: %s depends on execSeqNum: %d\n",
173 unsigned int num_dests = staticInst->
numDestRegs();
176 for (
unsigned int dest_index = 0; dest_index < num_dests;
179 const RegId&
reg = inst->flatDestRegIdx[dest_index];
194 DPRINTF(MinorScoreboard,
"Clearing inst: %s"
195 " regIndex: %d final numResults: %d\n",
212 unsigned int num_srcs = staticInst->
numSrcRegs();
217 unsigned int num_relative_latencies = 0;
223 if (src_reg_relative_latencies &&
224 src_reg_relative_latencies->size() != 0)
226 num_relative_latencies = src_reg_relative_latencies->size();
227 default_relative_latency = (*src_reg_relative_latencies)
228 [num_relative_latencies-1];
234 unsigned int src_index = 0;
235 while (src_index < num_srcs &&
239 unsigned short int index;
244 cant_forward_from_fu_indices &&
245 src_reg_fu < cant_forward_from_fu_indices->size() &&
246 (*cant_forward_from_fu_indices)[src_reg_fu];
249 (src_index >= num_relative_latencies ?
250 default_relative_latency :
251 (*src_reg_relative_latencies)[src_index]));
262 if (debug::MinorTiming) {
263 if (ret && num_srcs > num_relative_latencies &&
264 num_relative_latencies != 0)
266 DPRINTF(MinorTiming,
"Warning, inst: %s timing extra decode has"
267 " more src. regs: %d than relative latencies: %d\n",
268 staticInst->
disassemble(0), num_srcs, num_relative_latencies);
278 std::ostringstream result_stream;
280 bool printed_element =
false;
285 unsigned short int num_unpredictable_results =
288 if (!(num_results == 0 && num_unpredictable_results ==
Cycles(0))) {
290 result_stream <<
',';
292 result_stream <<
'(' <<
i <<
','
293 << num_results <<
'/'
294 << num_unpredictable_results <<
'/'
298 printed_element =
true;
Cycles is a wrapper class for representing cycle counts, i.e.
Register ID: describe an architectural register with its class and index.
RegId flatten(const BaseISA &isa) const
virtual const std::string & disassemble(Addr pc, const loader::SymbolTable *symtab=nullptr) const
Return string representation of disassembled instruction.
uint8_t numSrcRegs() const
Number of source registers.
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
uint8_t numDestRegs() const
Number of destination registers.
const RegId & destRegIdx(int i) const
Return logical index (architectural reg num) of i'th destination reg.
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual BaseISA * getIsaPtr() const =0
std::vector< Index > numUnpredictableResults
Count of the number of results which can't be predicted.
void clearInstDests(MinorDynInstPtr inst, bool clear_unpredictable)
Clear down the dependencies for this instruction.
std::vector< Cycles > returnCycle
The estimated cycle number that the result will be presented.
static constexpr int invalidFUIndex
const unsigned floatRegOffset
bool canInstIssue(MinorDynInstPtr inst, const std::vector< Cycles > *src_reg_relative_latencies, const std::vector< bool > *cant_forward_from_fu_indices, Cycles now, ThreadContext *thread_context)
Can this instruction be issued.
InstSeqNum execSeqNumToWaitFor(MinorDynInstPtr inst, ThreadContext *thread_context)
Returns the exec sequence number of the most recent inst on which the given inst depends.
const unsigned vecRegOffset
unsigned short int Index
Type to use when indexing numResults.
const unsigned ccRegOffset
std::vector< Index > numResults
Count of the number of in-flight instructions that have results for each register.
std::vector< int > fuIndices
Index of the FU generating this result.
const unsigned vecPredRegOffset
bool findIndex(const RegId ®, Index &scoreboard_index)
Sets scoreboard_index to the index into numResults of the given register index.
void markupInstDests(MinorDynInstPtr inst, Cycles retire_time, ThreadContext *thread_context, bool mark_unpredictable)
Mark up an instruction's effects by incrementing numResults counts.
std::vector< InstSeqNum > writingInst
The execute sequence number of the most recent inst to generate this register value.
void minorTrace() const
MinorTraceIF interface.
const unsigned numRegs
The number of registers in the Scoreboard.
#define panic(...)
This implements a cprintf based panic() function.
A simple instruction scoreboard for tracking dependencies in Execute.
void minorTrace(const char *fmt, Args ...args)
DPRINTFN for MinorTrace reporting.
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
@ FloatRegClass
Floating-point register.
@ CCRegClass
Condition-code register.
@ VecRegClass
Vector Register.
@ IntRegClass
Integer register.
@ MiscRegClass
Control (misc) register.
@ VecElemClass
Vector Register Native Elem lane.
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
Minor contains all the definitions within the MinorCPU apart from the CPU class itself.