gem5  v21.1.0.2
scoreboard.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2013-2014, 2016-2017 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions are
16  * met: redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer;
18  * redistributions in binary form must reproduce the above copyright
19  * notice, this list of conditions and the following disclaimer in the
20  * documentation and/or other materials provided with the distribution;
21  * neither the name of the copyright holders nor the names of its
22  * contributors may be used to endorse or promote products derived from
23  * this software without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 #include "cpu/minor/scoreboard.hh"
39 
40 #include "cpu/reg_class.hh"
41 #include "debug/MinorScoreboard.hh"
42 #include "debug/MinorTiming.hh"
43 
44 namespace gem5
45 {
46 
48 namespace minor
49 {
50 
51 bool
52 Scoreboard::findIndex(const RegId& reg, Index &scoreboard_index)
53 {
54  bool ret = false;
55 
56  switch (reg.classValue()) {
57  case IntRegClass:
58  if (reg.index() == zeroReg) {
59  /* Don't bother with the zero register */
60  ret = false;
61  } else {
62  scoreboard_index = reg.index();
63  ret = true;
64  }
65  break;
66  case FloatRegClass:
67  scoreboard_index = floatRegOffset + reg.index();
68  ret = true;
69  break;
70  case VecRegClass:
71  case VecElemClass:
72  scoreboard_index = vecRegOffset + reg.index();
73  ret = true;
74  break;
75  case VecPredRegClass:
76  scoreboard_index = vecPredRegOffset + reg.index();
77  ret = true;
78  break;
79  case CCRegClass:
80  scoreboard_index = ccRegOffset + reg.index();
81  ret = true;
82  break;
83  case MiscRegClass:
84  /* Don't bother with Misc registers */
85  ret = false;
86  break;
87  default:
88  panic("Unknown register class: %d", reg.classValue());
89  }
90 
91  return ret;
92 }
93 
95 static RegId
96 flattenRegIndex(const RegId& reg, ThreadContext *thread_context)
97 {
98  return thread_context->flattenRegId(reg);
99 }
100 
101 void
103  ThreadContext *thread_context, bool mark_unpredictable)
104 {
105  if (inst->isFault())
106  return;
107 
108  StaticInstPtr staticInst = inst->staticInst;
109  unsigned int num_dests = staticInst->numDestRegs();
110 
112  for (unsigned int dest_index = 0; dest_index < num_dests;
113  dest_index++)
114  {
116  staticInst->destRegIdx(dest_index), thread_context);
117  Index index;
118 
119  if (findIndex(reg, index)) {
120  if (mark_unpredictable)
122 
123  inst->flatDestRegIdx[dest_index] = reg;
124 
125  numResults[index]++;
126  returnCycle[index] = retire_time;
127  /* We should be able to rely on only being given accending
128  * execSeqNums, but sanity check */
129  if (inst->id.execSeqNum > writingInst[index]) {
130  writingInst[index] = inst->id.execSeqNum;
131  fuIndices[index] = inst->fuIndex;
132  }
133 
134  DPRINTF(MinorScoreboard, "Marking up inst: %s"
135  " regIndex: %d final numResults: %d returnCycle: %d\n",
136  *inst, index, numResults[index], returnCycle[index]);
137  } else {
138  /* Use zeroReg to mark invalid/untracked dests */
139  inst->flatDestRegIdx[dest_index] = RegId(IntRegClass, zeroReg);
140  }
141  }
142 }
143 
146  ThreadContext *thread_context)
147 {
148  InstSeqNum ret = 0;
149 
150  if (inst->isFault())
151  return ret;
152 
153  StaticInstPtr staticInst = inst->staticInst;
154  unsigned int num_srcs = staticInst->numSrcRegs();
155 
156  for (unsigned int src_index = 0; src_index < num_srcs; src_index++) {
157  RegId reg = flattenRegIndex(staticInst->srcRegIdx(src_index),
158  thread_context);
159  unsigned short int index;
160 
161  if (findIndex(reg, index)) {
162  if (writingInst[index] > ret)
163  ret = writingInst[index];
164  }
165  }
166 
167  DPRINTF(MinorScoreboard, "Inst: %s depends on execSeqNum: %d\n",
168  *inst, ret);
169 
170  return ret;
171 }
172 
173 void
174 Scoreboard::clearInstDests(MinorDynInstPtr inst, bool clear_unpredictable)
175 {
176  if (inst->isFault())
177  return;
178 
179  StaticInstPtr staticInst = inst->staticInst;
180  unsigned int num_dests = staticInst->numDestRegs();
181 
183  for (unsigned int dest_index = 0; dest_index < num_dests;
184  dest_index++)
185  {
186  const RegId& reg = inst->flatDestRegIdx[dest_index];
187  Index index;
188 
189  if (findIndex(reg, index)) {
190  if (clear_unpredictable && numUnpredictableResults[index] != 0)
192 
193  numResults[index] --;
194 
195  if (numResults[index] == 0) {
196  returnCycle[index] = Cycles(0);
197  writingInst[index] = 0;
198  fuIndices[index] = -1;
199  }
200 
201  DPRINTF(MinorScoreboard, "Clearing inst: %s"
202  " regIndex: %d final numResults: %d\n",
203  *inst, index, numResults[index]);
204  }
205  }
206 }
207 
208 bool
210  const std::vector<Cycles> *src_reg_relative_latencies,
211  const std::vector<bool> *cant_forward_from_fu_indices,
212  Cycles now, ThreadContext *thread_context)
213 {
214  /* Always allow fault to be issued */
215  if (inst->isFault())
216  return true;
217 
218  StaticInstPtr staticInst = inst->staticInst;
219  unsigned int num_srcs = staticInst->numSrcRegs();
220 
221  /* Default to saying you can issue */
222  bool ret = true;
223 
224  unsigned int num_relative_latencies = 0;
225  Cycles default_relative_latency = Cycles(0);
226 
227  /* Where relative latencies are given, the default is the last
228  * one as that allows the rel. lat. list to be shorted than the
229  * number of src. regs */
230  if (src_reg_relative_latencies &&
231  src_reg_relative_latencies->size() != 0)
232  {
233  num_relative_latencies = src_reg_relative_latencies->size();
234  default_relative_latency = (*src_reg_relative_latencies)
235  [num_relative_latencies-1];
236  }
237 
238  /* For each source register, find the latest result */
239  unsigned int src_index = 0;
240  while (src_index < num_srcs && /* More registers */
241  ret /* Still possible */)
242  {
243  RegId reg = flattenRegIndex(staticInst->srcRegIdx(src_index),
244  thread_context);
245  unsigned short int index;
246 
247  if (findIndex(reg, index)) {
248  bool cant_forward = fuIndices[index] != 1 &&
249  cant_forward_from_fu_indices &&
250  index < cant_forward_from_fu_indices->size() &&
251  (*cant_forward_from_fu_indices)[index];
252 
253  Cycles relative_latency = (cant_forward ? Cycles(0) :
254  (src_index >= num_relative_latencies ?
255  default_relative_latency :
256  (*src_reg_relative_latencies)[src_index]));
257 
258  if (returnCycle[index] > (now + relative_latency) ||
260  {
261  ret = false;
262  }
263  }
264  src_index++;
265  }
266 
267  if (debug::MinorTiming) {
268  if (ret && num_srcs > num_relative_latencies &&
269  num_relative_latencies != 0)
270  {
271  DPRINTF(MinorTiming, "Warning, inst: %s timing extra decode has"
272  " more src. regs: %d than relative latencies: %d\n",
273  staticInst->disassemble(0), num_srcs, num_relative_latencies);
274  }
275  }
276 
277  return ret;
278 }
279 
280 void
282 {
283  std::ostringstream result_stream;
284 
285  bool printed_element = false;
286 
287  unsigned int i = 0;
288  while (i < numRegs) {
289  unsigned short int num_results = numResults[i];
290  unsigned short int num_unpredictable_results =
292 
293  if (!(num_results == 0 && num_unpredictable_results == Cycles(0))) {
294  if (printed_element)
295  result_stream << ',';
296 
297  result_stream << '(' << i << ','
298  << num_results << '/'
299  << num_unpredictable_results << '/'
300  << returnCycle[i] << '/'
301  << writingInst[i] << ')';
302 
303  printed_element = true;
304  }
305 
306  i++;
307  }
308 
309  minor::minorTrace("busy=%s\n", result_stream.str());
310 }
311 
312 } // namespace minor
313 } // namespace gem5
gem5::minor::Scoreboard::vecRegOffset
const unsigned vecRegOffset
Definition: scoreboard.hh:74
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:62
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:64
scoreboard.hh
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::minor::Scoreboard::markupInstDests
void markupInstDests(MinorDynInstPtr inst, Cycles retire_time, ThreadContext *thread_context, bool mark_unpredictable)
Mark up an instruction's effects by incrementing numResults counts.
Definition: scoreboard.cc:102
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:58
gem5::minor::Scoreboard::numUnpredictableResults
std::vector< Index > numUnpredictableResults
Count of the number of results which can't be predicted.
Definition: scoreboard.hh:95
gem5::minor::Scoreboard::numRegs
const unsigned numRegs
The number of registers in the Scoreboard.
Definition: scoreboard.hh:83
minor
gem5::minor::Scoreboard::canInstIssue
bool canInstIssue(MinorDynInstPtr inst, const std::vector< Cycles > *src_reg_relative_latencies, const std::vector< bool > *cant_forward_from_fu_indices, Cycles now, ThreadContext *thread_context)
Can this instruction be issued.
Definition: scoreboard.cc:209
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:65
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:63
gem5::StaticInst::numSrcRegs
int8_t numSrcRegs() const
Number of source registers.
Definition: static_inst.hh:139
std::vector
STL vector class.
Definition: stl.hh:37
gem5::minor::Scoreboard::numResults
std::vector< Index > numResults
Count of the number of in-flight instructions that have results for each register.
Definition: scoreboard.hh:92
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::minor::Scoreboard::zeroReg
const RegIndex zeroReg
Definition: scoreboard.hh:85
gem5::StaticInst::destRegIdx
const RegId & destRegIdx(int i) const
Return logical index (architectural reg num) of i'th destination reg.
Definition: static_inst.hh:237
gem5::RefCountingPtr< MinorDynInst >
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::ThreadContext::flattenRegId
virtual RegId flattenRegId(const RegId &reg_id) const =0
gem5::StaticInst::srcRegIdx
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
Definition: static_inst.hh:247
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::minor::flattenRegIndex
static RegId flattenRegIndex(const RegId &reg, ThreadContext *thread_context)
Flatten a RegId, irrespective of what reg type it's pointing to.
Definition: scoreboard.cc:96
gem5::minor::Scoreboard::minorTrace
void minorTrace() const
MinorTraceIF interface.
Definition: scoreboard.cc:281
gem5::minor::Scoreboard::fuIndices
std::vector< int > fuIndices
Index of the FU generating this result.
Definition: scoreboard.hh:98
gem5::minor::Scoreboard::clearInstDests
void clearInstDests(MinorDynInstPtr inst, bool clear_unpredictable)
Clear down the dependencies for this instruction.
Definition: scoreboard.cc:174
gem5::minor::Scoreboard::findIndex
bool findIndex(const RegId &reg, Index &scoreboard_index)
Sets scoreboard_index to the index into numResults of the given register index.
Definition: scoreboard.cc:52
gem5::minor::Scoreboard::writingInst
std::vector< InstSeqNum > writingInst
The execute sequence number of the most recent inst to generate this register value.
Definition: scoreboard.hh:108
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::minor::minorTrace
void minorTrace(const char *fmt, Args ...args)
DPRINTFN for MinorTrace reporting.
Definition: trace.hh:67
gem5::minor::Scoreboard::Index
unsigned short int Index
Type to use when indexing numResults.
Definition: scoreboard.hh:88
gem5::minor::Scoreboard::ccRegOffset
const unsigned ccRegOffset
Definition: scoreboard.hh:73
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:60
gem5::minor::Scoreboard::returnCycle
std::vector< Cycles > returnCycle
The estimated cycle number that the result will be presented.
Definition: scoreboard.hh:104
gem5::StaticInst::disassemble
virtual const std::string & disassemble(Addr pc, const loader::SymbolTable *symtab=nullptr) const
Return string representation of disassembled instruction.
Definition: static_inst.cc:75
gem5::minor::Scoreboard::execSeqNumToWaitFor
InstSeqNum execSeqNumToWaitFor(MinorDynInstPtr inst, ThreadContext *thread_context)
Returns the exec sequence number of the most recent inst on which the given inst depends.
Definition: scoreboard.cc:145
reg_class.hh
gem5::StaticInst::numDestRegs
int8_t numDestRegs() const
Number of destination registers.
Definition: static_inst.hh:141
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::minor::Scoreboard::vecPredRegOffset
const unsigned vecPredRegOffset
Definition: scoreboard.hh:75
gem5::minor::Scoreboard::floatRegOffset
const unsigned floatRegOffset
Definition: scoreboard.hh:72
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177

Generated on Tue Sep 21 2021 12:25:01 for gem5 by doxygen 1.8.17