gem5  v21.1.0.2
unknown.hh
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29 
30 #ifndef __ARCH_RISCV_UNKNOWN_INST_HH__
31 #define __ARCH_RISCV_UNKNOWN_INST_HH__
32 
33 #include <memory>
34 #include <string>
35 
36 #include "arch/riscv/faults.hh"
39 #include "cpu/exec_context.hh"
40 #include "cpu/static_inst.hh"
41 
42 namespace gem5
43 {
44 
45 namespace RiscvISA
46 {
47 
53 class Unknown : public RiscvStaticInst
54 {
55  public:
56  Unknown(MachInst _machInst)
57  : RiscvStaticInst("unknown", _machInst, No_OpClass)
58  {}
59 
60  Fault
61  execute(ExecContext *, Trace::InstRecord *) const override
62  {
63  return std::make_shared<UnknownInstFault>(machInst);
64  }
65 
66  std::string
68  Addr pc, const loader::SymbolTable *symtab) const override
69  {
70  return csprintf("unknown opcode %#02x", OPCODE);
71  }
72 };
73 
74 } // namespace RiscvISA
75 } // namespace gem5
76 
77 #endif // __ARCH_RISCV_UNKNOWN_INST_HH__
faults.hh
gem5::RiscvISA::MachInst
uint32_t MachInst
Definition: types.hh:53
gem5::RiscvISA::Unknown
Static instruction class for unknown (illegal) instructions.
Definition: unknown.hh:53
gem5::RiscvISA::RiscvStaticInst
Base class for all RISC-V static instructions.
Definition: static_inst.hh:49
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::RiscvISA::Unknown::Unknown
Unknown(MachInst _machInst)
Definition: unknown.hh:56
gem5::RiscvISA::RiscvStaticInst::machInst
ExtMachInst machInst
Definition: static_inst.hh:58
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::RiscvISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
static_inst.hh
static_inst.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::RiscvISA::Unknown::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: unknown.hh:67
gem5::RiscvISA::Unknown::execute
Fault execute(ExecContext *, Trace::InstRecord *) const override
Definition: unknown.hh:61
exec_context.hh
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::Trace::InstRecord
Definition: insttracer.hh:58
bitfields.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
OPCODE
#define OPCODE
Definition: bitfields.hh:11

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