unknown.hh

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/*
 * Copyright (c) 2015 RISC-V Foundation
 * Copyright (c) 2017 The University of Virginia
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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 */
 
#ifndef __ARCH_RISCV_UNKNOWN_INST_HH__
#define __ARCH_RISCV_UNKNOWN_INST_HH__
 
#include <memory>
#include <string>
 
#include "arch/riscv/faults.hh"
#include "arch/riscv/insts/bitfields.hh"
#include "arch/riscv/insts/static_inst.hh"
#include "cpu/exec_context.hh"
#include "cpu/static_inst.hh"
 
namespace gem5
{
 
namespace RiscvISA
{
 
class Unknown : public RiscvStaticInst
{
  public:
    Unknown(MachInst _machInst)
        : RiscvStaticInst("unknown", _machInst, No_OpClass)
    {}
 
    Fault
    execute(ExecContext *, trace::InstRecord *) const override
    {
        return std::make_shared<UnknownInstFault>(machInst);
    }
 
    std::string
    generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override
    {
        return csprintf("unknown opcode %#02x", OPCODE);
    }
};
 
} // namespace RiscvISA
} // namespace gem5
 
#endif // __ARCH_RISCV_UNKNOWN_INST_HH__