gem5 v24.0.0.0
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fs_workload.hh
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1/*
2 * Copyright (c) 2021 Huawei International
3 * All rights reserved
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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27 */
28
29#ifndef __ARCH_RISCV_LINUX_SYSTEM_HH__
30#define __ARCH_RISCV_LINUX_SYSTEM_HH__
31
32#include <string>
33
36#include "params/RiscvBootloaderKernelWorkload.hh"
37#include "params/RiscvLinux.hh"
39
40namespace gem5
41{
42
43namespace RiscvISA
44{
45
46class FsLinux : public KernelWorkload
47{
48 private:
58 public:
62 {
63 if (kernelPanicPcEvent != nullptr) {
64 delete kernelPanicPcEvent;
65 }
66 if (kernelOopsPcEvent != nullptr) {
67 delete kernelOopsPcEvent;
68 }
69 }
70
71 void initState() override;
72 void startup() override;
73
74 void
75 setSystem(System *sys) override
76 {
79 params().remote_gdb_port, system);
80 }
81
82 ByteOrder byteOrder() const override { return ByteOrder::little; }
83 RiscvSemihosting *getSemihosting() const override { return semihosting; }
84};
85
87{
88 private:
94 const std::string bootArgs;
96
103
104 private:
107 void loadBootloader();
108 void loadKernel();
109 void loadDtb();
112
113 public:
114 PARAMS(RiscvBootloaderKernelWorkload);
116 : Workload(p), entryPoint(p.entry_point), bootArgs(p.command_line),
118 {
121 }
122
124 {
125 if (kernelPanicPcEvent != nullptr) {
126 delete kernelPanicPcEvent;
127 }
128 if (kernelOopsPcEvent != nullptr) {
129 delete kernelOopsPcEvent;
130 }
131 }
132
133 void initState() override;
134 void startup() override;
135
136 void
137 setSystem(System *sys) override
138 {
141 params().remote_gdb_port, system);
142 }
143
144 Addr getEntry() const override { return entryPoint; }
145
146 ByteOrder byteOrder() const override { return ByteOrder::little; }
147
148 loader::Arch getArch() const override { return kernel->getArch(); }
149
150 RiscvSemihosting *getSemihosting() const override { return semihosting; }
151
152 const loader::SymbolTable &
153 symtab(ThreadContext *tc) override
154 {
155 return kernelSymbolTable;
156 }
157
158 bool
159 insertSymbol(const loader::Symbol &symbol) override
160 {
161 return kernelSymbolTable.insert(symbol);
162 }
163
164 void serialize(CheckpointOut &checkpoint) const override;
165 void unserialize(CheckpointIn &checkpoint) override;
166};
167
168} // namespace RiscvISA
169} // namespace gem5
170
171#endif // __ARCH_RISCV_LINUX_FS_WORKLOAD_HH__
static BaseRemoteGDB * build(ListenSocketConfig listen_config, Args... args)
PCEvent * kernelPanicPcEvent
Event to halt the simulator if the kernel calls panic() or oops_exit()
void serialize(CheckpointOut &checkpoint) const override
Serialize an object.
PARAMS(RiscvBootloaderKernelWorkload)
void unserialize(CheckpointIn &checkpoint) override
Unserialize an object.
RiscvSemihosting * getSemihosting() const override
Returns the semihosting interface if supported by the current workload.
const loader::SymbolTable & symtab(ThreadContext *tc) override
ByteOrder byteOrder() const override
void startup() override
startup() is the final initialization call before simulation.
loader::Arch getArch() const override
bool insertSymbol(const loader::Symbol &symbol) override
void setSystem(System *sys) override
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
void setSystem(System *sys) override
void startup() override
startup() is the final initialization call before simulation.
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
RiscvSemihosting * semihosting
FsLinux(const Params &p)
PCEvent * kernelPanicPcEvent
Event to halt the simulator if the kernel calls panic() or oops_exit()
RiscvSemihosting * getSemihosting() const override
Returns the semihosting interface if supported by the current workload.
ByteOrder byteOrder() const override
Semihosting for RV32 and RV64.
SimObjectParams Params
ThreadContext is the external interface to all thread state for anything outside of the CPU.
BaseRemoteGDB * gdb
Definition workload.hh:77
virtual void setSystem(System *sys)
Definition workload.hh:88
System * system
Definition workload.hh:81
bool insert(const Symbol &symbol)
Insert a new symbol in the table if it does not already exist.
Definition symtab.cc:66
const Params & params() const
Bitfield< 0 > p
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
std::ostream CheckpointOut
Definition serialize.hh:66
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147

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