scalar_register_file.hh

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/*
 * Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
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#ifndef __GPU_COMPUTE_SCALAR_REGISTER_FILE_HH__
#define __GPU_COMPUTE_SCALAR_REGISTER_FILE_HH__
 
#include "arch/gpu_isa.hh"
#include "base/statistics.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "debug/GPUSRF.hh"
#include "gpu-compute/register_file.hh"
#include "gpu-compute/wavefront.hh"
 
namespace gem5
{
 
struct ScalarRegisterFileParams;
 
// Scalar Register File
class ScalarRegisterFile : public RegisterFile
{
  public:
    using ScalarRegU32 = TheGpuISA::ScalarRegU32;
 
    ScalarRegisterFile(const ScalarRegisterFileParams &p);
    ~ScalarRegisterFile() { }
 
    virtual bool operandsReady(Wavefront *w, GPUDynInstPtr ii) const override;
    virtual void scheduleWriteOperands(Wavefront *w,
                                       GPUDynInstPtr ii) override;
    virtual void scheduleWriteOperandsFromLoad(Wavefront *w,
                                               GPUDynInstPtr ii) override;
    virtual void waveExecuteInst(Wavefront *w, GPUDynInstPtr ii) override;
 
    void
    setParent(ComputeUnit *_computeUnit) override
    {
        RegisterFile::setParent(_computeUnit);
    }
 
    // Read a register that is writeable (e.g., a DST operand)
    ScalarRegU32&
    readWriteable(int regIdx)
    {
        return regFile[regIdx];
    }
 
    // Read a register that is not writeable (e.g., src operand)
    ScalarRegU32
    read(int regIdx) const
    {
        return regFile[regIdx];
    }
 
    // Write a register
    void
    write(int regIdx, ScalarRegU32 value)
    {
        regFile[regIdx] = value;
    }
 
    void
    printReg(Wavefront *wf, int regIdx) const
    {
        DPRINTF(GPUSRF, "WF[%d][%d]: Id%d s[%d] = %#x\n", wf->simdId,
            wf->wfSlotId, wf->wfDynId, regIdx, regFile[regIdx]);
    }
 
  private:
    std::vector<ScalarRegU32> regFile;
};
 
} // namespace gem5
 
#endif // __GPU_COMPUTE_SCALAR_REGISTER_FILE_HH__