gem5  v22.0.0.1
scalar_register_file.hh
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31 
32 #ifndef __GPU_COMPUTE_SCALAR_REGISTER_FILE_HH__
33 #define __GPU_COMPUTE_SCALAR_REGISTER_FILE_HH__
34 
35 #include "arch/gpu_isa.hh"
36 #include "base/statistics.hh"
37 #include "base/trace.hh"
38 #include "base/types.hh"
39 #include "debug/GPUSRF.hh"
41 #include "gpu-compute/wavefront.hh"
42 
43 namespace gem5
44 {
45 
46 struct ScalarRegisterFileParams;
47 
48 // Scalar Register File
50 {
51  public:
53 
54  ScalarRegisterFile(const ScalarRegisterFileParams &p);
56 
57  virtual bool operandsReady(Wavefront *w, GPUDynInstPtr ii) const override;
58  virtual void scheduleWriteOperands(Wavefront *w,
59  GPUDynInstPtr ii) override;
61  GPUDynInstPtr ii) override;
62  virtual void waveExecuteInst(Wavefront *w, GPUDynInstPtr ii) override;
63 
64  void
65  setParent(ComputeUnit *_computeUnit) override
66  {
67  RegisterFile::setParent(_computeUnit);
68  }
69 
70  // Read a register that is writeable (e.g., a DST operand)
72  readWriteable(int regIdx)
73  {
74  return regFile[regIdx];
75  }
76 
77  // Read a register that is not writeable (e.g., src operand)
79  read(int regIdx) const
80  {
81  return regFile[regIdx];
82  }
83 
84  // Write a register
85  void
86  write(int regIdx, ScalarRegU32 value)
87  {
88  regFile[regIdx] = value;
89  }
90 
91  void
92  printReg(Wavefront *wf, int regIdx) const
93  {
94  DPRINTF(GPUSRF, "WF[%d][%d]: Id%d s[%d] = %#x\n", wf->simdId,
95  wf->wfSlotId, wf->wfDynId, regIdx, regFile[regIdx]);
96  }
97 
98  private:
100 };
101 
102 } // namespace gem5
103 
104 #endif // __GPU_COMPUTE_SCALAR_REGISTER_FILE_HH__
gem5::RegisterFile
Definition: register_file.hh:56
gem5::ScalarRegisterFile::ScalarRegU32
TheGpuISA::ScalarRegU32 ScalarRegU32
Definition: scalar_register_file.hh:52
gem5::ScalarRegisterFile::setParent
void setParent(ComputeUnit *_computeUnit) override
Definition: scalar_register_file.hh:65
gem5::ScalarRegisterFile::scheduleWriteOperandsFromLoad
virtual void scheduleWriteOperandsFromLoad(Wavefront *w, GPUDynInstPtr ii) override
Definition: scalar_register_file.cc:110
gem5::ScalarRegisterFile::operandsReady
virtual bool operandsReady(Wavefront *w, GPUDynInstPtr ii) const override
Definition: scalar_register_file.cc:52
gem5::Wavefront
Definition: wavefront.hh:60
gem5::ScalarRegisterFile::~ScalarRegisterFile
~ScalarRegisterFile()
Definition: scalar_register_file.hh:55
gem5::ScalarRegisterFile::write
void write(int regIdx, ScalarRegU32 value)
Definition: scalar_register_file.hh:86
gem5::VegaISA::w
Bitfield< 6 > w
Definition: pagetable.hh:59
std::vector< ScalarRegU32 >
gem5::ScalarRegisterFile::printReg
void printReg(Wavefront *wf, int regIdx) const
Definition: scalar_register_file.hh:92
wavefront.hh
gem5::ComputeUnit
Definition: compute_unit.hh:201
register_file.hh
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::ScalarRegisterFile::waveExecuteInst
virtual void waveExecuteInst(Wavefront *w, GPUDynInstPtr ii) override
Definition: scalar_register_file.cc:91
statistics.hh
gem5::Wavefront::wfSlotId
const int wfSlotId
Definition: wavefront.hh:96
gem5::ScalarRegisterFile::scheduleWriteOperands
virtual void scheduleWriteOperands(Wavefront *w, GPUDynInstPtr ii) override
Definition: scalar_register_file.cc:80
gem5::Wavefront::wfDynId
uint64_t wfDynId
Definition: wavefront.hh:226
gem5::ScalarRegisterFile::ScalarRegisterFile
ScalarRegisterFile(const ScalarRegisterFileParams &p)
Definition: scalar_register_file.cc:45
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:49
types.hh
gem5::ScalarRegisterFile::readWriteable
ScalarRegU32 & readWriteable(int regIdx)
Definition: scalar_register_file.hh:72
gem5::RegisterFile::setParent
virtual void setParent(ComputeUnit *_computeUnit)
Definition: register_file.cc:64
trace.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ScalarRegisterFile::read
ScalarRegU32 read(int regIdx) const
Definition: scalar_register_file.hh:79
gem5::ScalarRegisterFile
Definition: scalar_register_file.hh:49
gem5::ScalarRegisterFile::regFile
std::vector< ScalarRegU32 > regFile
Definition: scalar_register_file.hh:99
gem5::Gcn3ISA::ScalarRegU32
uint32_t ScalarRegU32
Definition: gpu_registers.hh:153
gem5::Wavefront::simdId
const int simdId
Definition: wavefront.hh:99

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