gem5  v21.2.1.1
scalar_register_file.cc
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31 
33 
34 #include "base/logging.hh"
35 #include "debug/GPUSRF.hh"
38 #include "gpu-compute/shader.hh"
39 #include "gpu-compute/wavefront.hh"
40 #include "params/ScalarRegisterFile.hh"
41 
42 namespace gem5
43 {
44 
45 ScalarRegisterFile::ScalarRegisterFile(const ScalarRegisterFileParams &p)
46  : RegisterFile(p)
47 {
48  regFile.resize(numRegs(), 0);
49 }
50 
51 bool
53 {
54  for (const auto& srcScalarOp : ii->srcScalarRegOperands()) {
55  for (const auto& physIdx : srcScalarOp.physIndices()) {
56  if (regBusy(physIdx)) {
57  DPRINTF(GPUSRF, "RAW stall: WV[%d]: %s: physReg[%d]\n",
58  w->wfDynId, ii->disassemble(), physIdx);
59  w->stats.numTimesBlockedDueRAWDependencies++;
60  return false;
61  }
62  }
63  }
64 
65  for (const auto& dstScalarOp : ii->dstScalarRegOperands()) {
66  for (const auto& physIdx : dstScalarOp.physIndices()) {
67  if (regBusy(physIdx)) {
68  DPRINTF(GPUSRF, "WAX stall: WV[%d]: %s: physReg[%d]\n",
69  w->wfDynId, ii->disassemble(), physIdx);
70  w->stats.numTimesBlockedDueWAXDependencies++;
71  return false;
72  }
73  }
74  }
75 
76  return true;
77 }
78 
79 void
81 {
82  for (const auto& dstScalarOp : ii->dstScalarRegOperands()) {
83  for (const auto& physIdx : dstScalarOp.physIndices()) {
84  // mark the destination scalar register as busy
85  markReg(physIdx, true);
86  }
87  }
88 }
89 
90 void
92 {
93  stats.registerReads += ii->numSrcScalarDWords();
94 
95  if (!ii->isLoad() && !(ii->isAtomic() || ii->isMemSync())) {
97  Tick tickDelay = computeUnit->cyclesToTicks(delay);
98 
99  for (const auto& dstScalarOp : ii->dstScalarRegOperands()) {
100  for (const auto& physIdx : dstScalarOp.physIndices()) {
101  enqRegFreeEvent(physIdx, tickDelay);
102  }
103  }
104 
105  stats.registerWrites += ii->numDstScalarDWords();
106  }
107 }
108 
109 void
111  GPUDynInstPtr ii)
112 {
113  assert(ii->isLoad() || ii->isAtomicRet());
114  for (const auto& dstScalarOp : ii->dstScalarRegOperands()) {
115  for (const auto& physIdx : dstScalarOp.physIndices()) {
117  }
118  }
119 
120  stats.registerWrites += ii->numDstScalarDWords();
121 }
122 
123 } // namespace gem5
gem5::RegisterFile
Definition: register_file.hh:56
gem5::MipsISA::w
Bitfield< 0 > w
Definition: pra_constants.hh:281
shader.hh
gem5::ScalarRegisterFile::scheduleWriteOperandsFromLoad
virtual void scheduleWriteOperandsFromLoad(Wavefront *w, GPUDynInstPtr ii) override
Definition: scalar_register_file.cc:110
gem5::RegisterFile::enqRegFreeEvent
virtual void enqRegFreeEvent(uint32_t regIdx, uint64_t delay)
Definition: register_file.cc:104
gem5::ScalarRegisterFile::operandsReady
virtual bool operandsReady(Wavefront *w, GPUDynInstPtr ii) const override
Definition: scalar_register_file.cc:52
gem5::Wavefront
Definition: wavefront.hh:60
compute_unit.hh
gem5::RegisterFile::stats
gem5::RegisterFile::RegisterFileStats stats
gem5::RegisterFile::markReg
virtual void markReg(int regIdx, bool value)
Definition: register_file.cc:96
gem5::ComputeUnit::scalarPipeLength
int scalarPipeLength() const
Definition: compute_unit.hh:391
gem5::RegisterFile::RegisterFileStats::registerWrites
statistics::Scalar registerWrites
Definition: register_file.hh:162
wavefront.hh
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::RegisterFile::regBusy
virtual bool regBusy(int idx) const
Definition: register_file.cc:90
gem5::RegisterFile::RegisterFileStats::registerReads
statistics::Scalar registerReads
Definition: register_file.hh:160
gem5::Clocked::cyclesToTicks
Tick cyclesToTicks(Cycles c) const
Definition: clocked_object.hh:227
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::ScalarRegisterFile::waveExecuteInst
virtual void waveExecuteInst(Wavefront *w, GPUDynInstPtr ii) override
Definition: scalar_register_file.cc:91
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::ScalarRegisterFile::scheduleWriteOperands
virtual void scheduleWriteOperands(Wavefront *w, GPUDynInstPtr ii) override
Definition: scalar_register_file.cc:80
scalar_register_file.hh
gpu_dyn_inst.hh
gem5::ScalarRegisterFile::ScalarRegisterFile
ScalarRegisterFile(const ScalarRegisterFileParams &p)
Definition: scalar_register_file.cc:45
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:49
gem5::RegisterFile::numRegs
int numRegs() const
Definition: register_file.hh:62
logging.hh
gem5::RegisterFile::computeUnit
ComputeUnit * computeUnit
Definition: register_file.hh:146
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::ScalarRegisterFile::regFile
std::vector< ScalarRegU32 > regFile
Definition: scalar_register_file.hh:99
gem5::Clocked::clockPeriod
Tick clockPeriod() const
Definition: clocked_object.hh:217

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