gem5  v21.1.0.2
scalar_register_file.cc
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33 
35 
36 #include "base/logging.hh"
37 #include "debug/GPUSRF.hh"
40 #include "gpu-compute/shader.hh"
41 #include "gpu-compute/wavefront.hh"
42 #include "params/ScalarRegisterFile.hh"
43 
44 namespace gem5
45 {
46 
47 ScalarRegisterFile::ScalarRegisterFile(const ScalarRegisterFileParams &p)
48  : RegisterFile(p)
49 {
50  regFile.resize(numRegs(), 0);
51 }
52 
53 bool
55 {
56  for (const auto& srcScalarOp : ii->srcScalarRegOperands()) {
57  for (const auto& physIdx : srcScalarOp.physIndices()) {
58  if (regBusy(physIdx)) {
59  DPRINTF(GPUSRF, "RAW stall: WV[%d]: %s: physReg[%d]\n",
60  w->wfDynId, ii->disassemble(), physIdx);
61  w->stats.numTimesBlockedDueRAWDependencies++;
62  return false;
63  }
64  }
65  }
66 
67  for (const auto& dstScalarOp : ii->dstScalarRegOperands()) {
68  for (const auto& physIdx : dstScalarOp.physIndices()) {
69  if (regBusy(physIdx)) {
70  DPRINTF(GPUSRF, "WAX stall: WV[%d]: %s: physReg[%d]\n",
71  w->wfDynId, ii->disassemble(), physIdx);
72  w->stats.numTimesBlockedDueWAXDependencies++;
73  return false;
74  }
75  }
76  }
77 
78  return true;
79 }
80 
81 void
83 {
84  for (const auto& dstScalarOp : ii->dstScalarRegOperands()) {
85  for (const auto& physIdx : dstScalarOp.physIndices()) {
86  // mark the destination scalar register as busy
87  markReg(physIdx, true);
88  }
89  }
90 }
91 
92 void
94 {
95  stats.registerReads += ii->numSrcScalarDWords();
96 
97  if (!ii->isLoad() && !(ii->isAtomic() || ii->isMemSync())) {
99  Tick tickDelay = computeUnit->cyclesToTicks(delay);
100 
101  for (const auto& dstScalarOp : ii->dstScalarRegOperands()) {
102  for (const auto& physIdx : dstScalarOp.physIndices()) {
103  enqRegFreeEvent(physIdx, tickDelay);
104  }
105  }
106 
107  stats.registerWrites += ii->numDstScalarDWords();
108  }
109 }
110 
111 void
113  GPUDynInstPtr ii)
114 {
115  assert(ii->isLoad() || ii->isAtomicRet());
116  for (const auto& dstScalarOp : ii->dstScalarRegOperands()) {
117  for (const auto& physIdx : dstScalarOp.physIndices()) {
119  }
120  }
121 
122  stats.registerWrites += ii->numDstScalarDWords();
123 }
124 
125 } // namespace gem5
gem5::RegisterFile
Definition: register_file.hh:58
gem5::MipsISA::w
Bitfield< 0 > w
Definition: pra_constants.hh:281
shader.hh
gem5::ScalarRegisterFile::scheduleWriteOperandsFromLoad
virtual void scheduleWriteOperandsFromLoad(Wavefront *w, GPUDynInstPtr ii) override
Definition: scalar_register_file.cc:112
gem5::RegisterFile::enqRegFreeEvent
virtual void enqRegFreeEvent(uint32_t regIdx, uint64_t delay)
Definition: register_file.cc:106
gem5::ScalarRegisterFile::operandsReady
virtual bool operandsReady(Wavefront *w, GPUDynInstPtr ii) const override
Definition: scalar_register_file.cc:54
gem5::Wavefront
Definition: wavefront.hh:62
compute_unit.hh
gem5::RegisterFile::stats
gem5::RegisterFile::RegisterFileStats stats
gem5::RegisterFile::markReg
virtual void markReg(int regIdx, bool value)
Definition: register_file.cc:98
gem5::ComputeUnit::scalarPipeLength
int scalarPipeLength() const
Definition: compute_unit.hh:393
gem5::RegisterFile::RegisterFileStats::registerWrites
statistics::Scalar registerWrites
Definition: register_file.hh:164
wavefront.hh
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::RegisterFile::regBusy
virtual bool regBusy(int idx) const
Definition: register_file.cc:92
gem5::RegisterFile::RegisterFileStats::registerReads
statistics::Scalar registerReads
Definition: register_file.hh:162
gem5::Clocked::cyclesToTicks
Tick cyclesToTicks(Cycles c) const
Definition: clocked_object.hh:227
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::ScalarRegisterFile::waveExecuteInst
virtual void waveExecuteInst(Wavefront *w, GPUDynInstPtr ii) override
Definition: scalar_register_file.cc:93
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::ScalarRegisterFile::scheduleWriteOperands
virtual void scheduleWriteOperands(Wavefront *w, GPUDynInstPtr ii) override
Definition: scalar_register_file.cc:82
scalar_register_file.hh
gpu_dyn_inst.hh
gem5::ScalarRegisterFile::ScalarRegisterFile
ScalarRegisterFile(const ScalarRegisterFileParams &p)
Definition: scalar_register_file.cc:47
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:51
gem5::RegisterFile::numRegs
int numRegs() const
Definition: register_file.hh:64
logging.hh
gem5::RegisterFile::computeUnit
ComputeUnit * computeUnit
Definition: register_file.hh:148
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ScalarRegisterFile::regFile
std::vector< ScalarRegU32 > regFile
Definition: scalar_register_file.hh:101
gem5::Clocked::clockPeriod
Tick clockPeriod() const
Definition: clocked_object.hh:217

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