gem5  v21.2.0.0
register_file.cc
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31 
33 
34 #include <sstream>
35 #include <string>
36 
37 #include "base/intmath.hh"
38 #include "base/logging.hh"
39 #include "debug/GPURF.hh"
42 #include "gpu-compute/shader.hh"
43 #include "gpu-compute/wavefront.hh"
44 #include "params/RegisterFile.hh"
45 
46 namespace gem5
47 {
48 
49 RegisterFile::RegisterFile(const RegisterFileParams &p)
50  : SimObject(p), simdId(p.simd_id), _numRegs(p.num_regs), stats(this)
51 {
52  fatal_if((_numRegs % 2) != 0, "VRF size is illegal\n");
53  fatal_if(simdId < 0, "Illegal SIMD id for VRF");
54 
55  busy.clear();
56  busy.resize(_numRegs, 0);
57 }
58 
60 {
61 }
62 
63 void
65 {
66  computeUnit = _computeUnit;
67 }
68 
69 std::string
71 {
72  std::stringstream ss;
73  ss << "Busy: ";
74  for (int i = 0; i < busy.size(); i++) {
75  ss << (int)busy[i];
76  }
77  ss << "\n";
78  return ss.str();
79 }
80 
81 // Scoreboard functions
82 
83 bool
85 {
86  return true;
87 }
88 
89 bool
90 RegisterFile::regBusy(int idx) const
91 {
92  return busy.at(idx);
93 }
94 
95 void
96 RegisterFile::markReg(int regIdx, bool value)
97 {
98  DPRINTF(GPURF, "SIMD[%d] markReg(): physReg[%d] = %d\n",
99  simdId, regIdx, (int)value);
100  busy.at(regIdx) = value;
101 }
102 
103 void
104 RegisterFile::enqRegFreeEvent(uint32_t regIdx, uint64_t delay)
105 {
106  DPRINTF(GPURF, "SIMD[%d] enqRegFreeEvent physReg[%d] at %llu\n",
107  simdId, regIdx, curTick() + delay);
108  schedule(new MarkRegFreeScbEvent(this, regIdx),
109  curTick() + delay);
110 }
111 
112 void
113 RegisterFile::enqRegBusyEvent(uint32_t regIdx, uint64_t delay)
114 {
115  DPRINTF(GPURF, "SIMD[%d] enqRegBusyEvent physReg[%d] at %llu\n",
116  simdId, regIdx, curTick() + delay);
117  schedule(new MarkRegBusyScbEvent(this, regIdx),
118  curTick() + delay);
119 }
120 
121 // Schedule functions
122 bool
124 {
125  return true;
126 }
127 
128 void
130 {
131 }
132 
133 bool
135 {
136  return true;
137 }
138 
139 void
141 {
142 }
143 
144 bool
146 {
147  return true;
148 }
149 
150 void
152 {
153 }
154 
155 bool
157 {
158  return true;
159 }
160 
161 // Exec functions
162 void
164 {
165 }
166 
167 void
169 {
170 }
171 
172 // Events
173 
174 // Mark a register as free in the scoreboard/busy vector
175 void
177 {
178  rf->markReg(regIdx, false);
179 }
180 
181 // Mark a register as busy in the scoreboard/busy vector
182 void
184 {
185  rf->markReg(regIdx, true);
186 }
187 
188 void
190 {
191 }
192 
194  : statistics::Group(parent),
195  ADD_STAT(registerReads,
196  "Total number of DWORDs read from register file"),
197  ADD_STAT(registerWrites,
198  "Total number of DWORDS written to register file"),
199  ADD_STAT(sramReads,
200  "Total number of register file bank SRAM activations for reads"),
201  ADD_STAT(sramWrites,
202  "Total number of register file bank SRAM activations for writes")
203 {
204 }
205 
206 } // namespace gem5
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::RegisterFile::MarkRegBusyScbEvent::process
void process()
Definition: register_file.cc:183
gem5::RegisterFile::busy
std::vector< bool > busy
Definition: register_file.hh:150
gem5::MipsISA::w
Bitfield< 0 > w
Definition: pra_constants.hh:281
gem5::RegisterFile::enqRegBusyEvent
virtual void enqRegBusyEvent(uint32_t regIdx, uint64_t delay)
Definition: register_file.cc:113
shader.hh
gem5::RegisterFile::MarkRegFreeScbEvent::process
void process()
Definition: register_file.cc:176
gem5::RegisterFile::enqRegFreeEvent
virtual void enqRegFreeEvent(uint32_t regIdx, uint64_t delay)
Definition: register_file.cc:104
gem5::Wavefront
Definition: wavefront.hh:60
compute_unit.hh
gem5::RegisterFile::RegisterFileStats::RegisterFileStats
RegisterFileStats(statistics::Group *parent)
Definition: register_file.cc:193
gem5::RegisterFile::canScheduleReadOperands
virtual bool canScheduleReadOperands(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:123
gem5::RegisterFile::dispatchInstruction
virtual void dispatchInstruction(GPUDynInstPtr ii)
Definition: register_file.cc:189
gem5::RegisterFile::markReg
virtual void markReg(int regIdx, bool value)
Definition: register_file.cc:96
gem5::EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1019
gem5::X86ISA::rf
Bitfield< 16 > rf
Definition: misc.hh:569
gem5::RegisterFile::waveExecuteInst
virtual void waveExecuteInst(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:168
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::RegisterFile::canScheduleWriteOperands
virtual bool canScheduleWriteOperands(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:134
wavefront.hh
gem5::RegisterFile::RegisterEvent::rf
RegisterFile * rf
Definition: register_file.hh:75
gem5::ComputeUnit
Definition: compute_unit.hh:201
register_file.hh
gem5::RegisterFile::regBusy
virtual bool regBusy(int idx) const
Definition: register_file.cc:90
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::RegisterFile::MarkRegBusyScbEvent
Definition: register_file.hh:93
gem5::RegisterFile::_numRegs
int _numRegs
Definition: register_file.hh:153
gpu_dyn_inst.hh
ss
std::stringstream ss
Definition: trace.test.cc:45
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::RegisterFile::RegisterFile
RegisterFile(const RegisterFileParams &p)
Definition: register_file.cc:49
gem5::RegisterFile::exec
virtual void exec()
Definition: register_file.cc:163
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:49
gem5::RegisterFile::RegisterEvent::regIdx
int regIdx
Definition: register_file.hh:76
gem5::RegisterFile::scheduleWriteOperands
virtual void scheduleWriteOperands(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:140
gem5::RegisterFile::scheduleReadOperands
virtual void scheduleReadOperands(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:129
gem5::RegisterFile::dump
virtual std::string dump() const
Definition: register_file.cc:70
gem5::RegisterFile::canScheduleWriteOperandsFromLoad
virtual bool canScheduleWriteOperandsFromLoad(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:145
gem5::RegisterFile::operandReadComplete
virtual bool operandReadComplete(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:156
gem5::RegisterFile::scheduleWriteOperandsFromLoad
virtual void scheduleWriteOperandsFromLoad(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:151
logging.hh
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::RegisterFile::setParent
virtual void setParent(ComputeUnit *_computeUnit)
Definition: register_file.cc:64
gem5::RegisterFile::computeUnit
ComputeUnit * computeUnit
Definition: register_file.hh:146
gem5::RegisterFile::simdId
int simdId
Definition: register_file.hh:147
intmath.hh
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:226
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::RegisterFile::MarkRegFreeScbEvent
Definition: register_file.hh:84
gem5::RegisterFile::~RegisterFile
virtual ~RegisterFile()
Definition: register_file.cc:59
gem5::RegisterFile::operandsReady
virtual bool operandsReady(Wavefront *w, GPUDynInstPtr ii) const
Definition: register_file.cc:84

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