gem5  v21.1.0.2
register_file.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
3  * All rights reserved.
4  *
5  * For use for simulation and test purposes only
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright notice,
11  * this list of conditions and the following disclaimer.
12  *
13  * 2. Redistributions in binary form must reproduce the above copyright notice,
14  * this list of conditions and the following disclaimer in the documentation
15  * and/or other materials provided with the distribution.
16  *
17  * 3. Neither the name of the copyright holder nor the names of its
18  * contributors may be used to endorse or promote products derived from this
19  * software without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  * POSSIBILITY OF SUCH DAMAGE.
32  */
33 
35 
36 #include <sstream>
37 #include <string>
38 
39 #include "base/intmath.hh"
40 #include "base/logging.hh"
41 #include "debug/GPURF.hh"
44 #include "gpu-compute/shader.hh"
45 #include "gpu-compute/wavefront.hh"
46 #include "params/RegisterFile.hh"
47 
48 namespace gem5
49 {
50 
51 RegisterFile::RegisterFile(const RegisterFileParams &p)
52  : SimObject(p), simdId(p.simd_id), _numRegs(p.num_regs), stats(this)
53 {
54  fatal_if((_numRegs % 2) != 0, "VRF size is illegal\n");
55  fatal_if(simdId < 0, "Illegal SIMD id for VRF");
56 
57  busy.clear();
58  busy.resize(_numRegs, 0);
59 }
60 
62 {
63 }
64 
65 void
67 {
68  computeUnit = _computeUnit;
69 }
70 
71 std::string
73 {
74  std::stringstream ss;
75  ss << "Busy: ";
76  for (int i = 0; i < busy.size(); i++) {
77  ss << (int)busy[i];
78  }
79  ss << "\n";
80  return ss.str();
81 }
82 
83 // Scoreboard functions
84 
85 bool
87 {
88  return true;
89 }
90 
91 bool
92 RegisterFile::regBusy(int idx) const
93 {
94  return busy.at(idx);
95 }
96 
97 void
98 RegisterFile::markReg(int regIdx, bool value)
99 {
100  DPRINTF(GPURF, "SIMD[%d] markReg(): physReg[%d] = %d\n",
101  simdId, regIdx, (int)value);
102  busy.at(regIdx) = value;
103 }
104 
105 void
106 RegisterFile::enqRegFreeEvent(uint32_t regIdx, uint64_t delay)
107 {
108  DPRINTF(GPURF, "SIMD[%d] enqRegFreeEvent physReg[%d] at %llu\n",
109  simdId, regIdx, curTick() + delay);
110  schedule(new MarkRegFreeScbEvent(this, regIdx),
111  curTick() + delay);
112 }
113 
114 void
115 RegisterFile::enqRegBusyEvent(uint32_t regIdx, uint64_t delay)
116 {
117  DPRINTF(GPURF, "SIMD[%d] enqRegBusyEvent physReg[%d] at %llu\n",
118  simdId, regIdx, curTick() + delay);
119  schedule(new MarkRegBusyScbEvent(this, regIdx),
120  curTick() + delay);
121 }
122 
123 // Schedule functions
124 bool
126 {
127  return true;
128 }
129 
130 void
132 {
133 }
134 
135 bool
137 {
138  return true;
139 }
140 
141 void
143 {
144 }
145 
146 bool
148 {
149  return true;
150 }
151 
152 void
154 {
155 }
156 
157 bool
159 {
160  return true;
161 }
162 
163 // Exec functions
164 void
166 {
167 }
168 
169 void
171 {
172 }
173 
174 // Events
175 
176 // Mark a register as free in the scoreboard/busy vector
177 void
179 {
180  rf->markReg(regIdx, false);
181 }
182 
183 // Mark a register as busy in the scoreboard/busy vector
184 void
186 {
187  rf->markReg(regIdx, true);
188 }
189 
190 void
192 {
193 }
194 
196  : statistics::Group(parent),
197  ADD_STAT(registerReads,
198  "Total number of DWORDs read from register file"),
199  ADD_STAT(registerWrites,
200  "Total number of DWORDS written to register file"),
201  ADD_STAT(sramReads,
202  "Total number of register file bank SRAM activations for reads"),
203  ADD_STAT(sramWrites,
204  "Total number of register file bank SRAM activations for writes")
205 {
206 }
207 
208 } // namespace gem5
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::RegisterFile::MarkRegBusyScbEvent::process
void process()
Definition: register_file.cc:185
gem5::RegisterFile::busy
std::vector< bool > busy
Definition: register_file.hh:152
gem5::MipsISA::w
Bitfield< 0 > w
Definition: pra_constants.hh:281
gem5::RegisterFile::enqRegBusyEvent
virtual void enqRegBusyEvent(uint32_t regIdx, uint64_t delay)
Definition: register_file.cc:115
shader.hh
gem5::RegisterFile::MarkRegFreeScbEvent::process
void process()
Definition: register_file.cc:178
gem5::RegisterFile::enqRegFreeEvent
virtual void enqRegFreeEvent(uint32_t regIdx, uint64_t delay)
Definition: register_file.cc:106
gem5::Wavefront
Definition: wavefront.hh:62
compute_unit.hh
gem5::RegisterFile::RegisterFileStats::RegisterFileStats
RegisterFileStats(statistics::Group *parent)
Definition: register_file.cc:195
gem5::RegisterFile::canScheduleReadOperands
virtual bool canScheduleReadOperands(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:125
gem5::RegisterFile::dispatchInstruction
virtual void dispatchInstruction(GPUDynInstPtr ii)
Definition: register_file.cc:191
gem5::RegisterFile::markReg
virtual void markReg(int regIdx, bool value)
Definition: register_file.cc:98
gem5::EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1019
gem5::X86ISA::rf
Bitfield< 16 > rf
Definition: misc.hh:569
gem5::RegisterFile::waveExecuteInst
virtual void waveExecuteInst(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:170
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::RegisterFile::canScheduleWriteOperands
virtual bool canScheduleWriteOperands(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:136
wavefront.hh
gem5::RegisterFile::RegisterEvent::rf
RegisterFile * rf
Definition: register_file.hh:77
gem5::ComputeUnit
Definition: compute_unit.hh:203
register_file.hh
gem5::RegisterFile::regBusy
virtual bool regBusy(int idx) const
Definition: register_file.cc:92
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::RegisterFile::MarkRegBusyScbEvent
Definition: register_file.hh:95
gem5::RegisterFile::_numRegs
int _numRegs
Definition: register_file.hh:155
gpu_dyn_inst.hh
ss
std::stringstream ss
Definition: trace.test.cc:45
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::RegisterFile::RegisterFile
RegisterFile(const RegisterFileParams &p)
Definition: register_file.cc:51
gem5::RegisterFile::exec
virtual void exec()
Definition: register_file.cc:165
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:51
gem5::RegisterFile::RegisterEvent::regIdx
int regIdx
Definition: register_file.hh:78
gem5::RegisterFile::scheduleWriteOperands
virtual void scheduleWriteOperands(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:142
gem5::RegisterFile::scheduleReadOperands
virtual void scheduleReadOperands(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:131
gem5::RegisterFile::dump
virtual std::string dump() const
Definition: register_file.cc:72
gem5::RegisterFile::canScheduleWriteOperandsFromLoad
virtual bool canScheduleWriteOperandsFromLoad(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:147
gem5::RegisterFile::operandReadComplete
virtual bool operandReadComplete(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:158
gem5::RegisterFile::scheduleWriteOperandsFromLoad
virtual void scheduleWriteOperandsFromLoad(Wavefront *w, GPUDynInstPtr ii)
Definition: register_file.cc:153
logging.hh
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::RegisterFile::setParent
virtual void setParent(ComputeUnit *_computeUnit)
Definition: register_file.cc:66
gem5::RegisterFile::computeUnit
ComputeUnit * computeUnit
Definition: register_file.hh:148
gem5::RegisterFile::simdId
int simdId
Definition: register_file.hh:149
intmath.hh
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:225
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::RegisterFile::MarkRegFreeScbEvent
Definition: register_file.hh:86
gem5::RegisterFile::~RegisterFile
virtual ~RegisterFile()
Definition: register_file.cc:61
gem5::RegisterFile::operandsReady
virtual bool operandsReady(Wavefront *w, GPUDynInstPtr ii) const
Definition: register_file.cc:86

Generated on Tue Sep 21 2021 12:25:25 for gem5 by doxygen 1.8.17