gem5  v22.0.0.1
schedule_stage.hh
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31 
32 #ifndef __SCHEDULE_STAGE_HH__
33 #define __SCHEDULE_STAGE_HH__
34 
35 #include <deque>
36 #include <unordered_map>
37 #include <unordered_set>
38 #include <utility>
39 #include <vector>
40 
41 #include "base/statistics.hh"
42 #include "base/stats/group.hh"
44 #include "gpu-compute/misc.hh"
45 #include "gpu-compute/scheduler.hh"
46 
47 namespace gem5
48 {
49 
50 // Schedule or execution arbitration stage.
51 // From the pool of ready waves in the ready list,
52 // one wave is selected for each execution resource.
53 // The selection is made based on a scheduling policy
54 
55 class ComputeUnit;
56 class ScheduleToExecute;
57 class ScoreboardCheckToSchedule;
58 class Wavefront;
59 
60 struct ComputeUnitParams;
61 
63 {
64  public:
65  ScheduleStage(const ComputeUnitParams &p, ComputeUnit &cu,
66  ScoreboardCheckToSchedule &from_scoreboard_check,
67  ScheduleToExecute &to_execute);
69  void init();
70  void exec();
71 
72  // Stats related variables and methods
73  const std::string& name() const { return _name; }
75  {
96  };
98  {
103  };
105  {
112  };
113 
114  // Called by ExecStage to inform SCH of instruction execution
115  void deleteFromSch(Wavefront *w);
116 
117  // Schedule List status
119  {
120  RFBUSY = 0, // RF busy reading operands
121  RFREADY, // ready for exec
122  };
123 
124  private:
128 
129  // Each execution resource will have its own
130  // scheduler and a dispatch list
132 
133  const std::string _name;
134 
135  // called by exec() to add a wave to schList if the RFs can support it
136  bool addToSchList(int exeType, const GPUDynInstPtr &gpu_dyn_inst);
137  // re-insert a wave to schList if wave lost arbitration
138  // wave is inserted such that age order (oldest to youngest) is preserved
139  void reinsertToSchList(int exeType, const GPUDynInstPtr &gpu_dyn_inst);
140  // check waves in schList to see if RF reads complete
142  // check execution resources for readiness
151  // check status of memory pipes and RF to Mem buses
152  void checkMemResources();
153  // resource ready check called by fillDispatchList
154  bool dispatchReady(const GPUDynInstPtr &gpu_dyn_inst);
155  // pick waves from schList and populate dispatchList with one wave
156  // per EXE resource type
157  void fillDispatchList();
158  // arbitrate Shared Mem Pipe VRF/LDS bus for waves in dispatchList
159  void arbitrateVrfToLdsBus();
160  // schedule destination operand writes to register files for waves in
161  // dispatchList
162  void scheduleRfDestOperands();
163  // invoked by scheduleRfDestOperands to schedule RF writes for a wave
164  bool schedRfWrites(int exeType, const GPUDynInstPtr &gpu_dyn_inst);
165  // reserve resources for waves surviving arbitration in dispatchList
166  void reserveResources();
167 
168  void doDispatchListTransition(int unitId, DISPATCH_STATUS s,
169  const GPUDynInstPtr &gpu_dyn_inst);
170  void doDispatchListTransition(int unitId, DISPATCH_STATUS s);
171 
172  // Set tracking wfDynId for each wave present in schedule stage
173  // Used to allow only one instruction per wave in schedule
174  std::unordered_set<uint64_t> wavesInSch;
175 
176  // List of waves (one list per exe resource) that are in schedule
177  // stage. Waves are added to this list after selected by scheduler
178  // from readyList. Waves are removed from this list and placed on
179  // dispatchList when status reaches SCHREADY.
180  // Waves are kept ordered by age for each resource, always favoring
181  // forward progress for the oldest wave.
182  // The maximum number of waves per resource can be determined by either
183  // the VRF/SRF availability or limits imposed by paremeters (to be added)
184  // of the SCH stage or CU.
186 
187  protected:
189  {
190  ScheduleStageStats(statistics::Group *parent, int num_exec_units);
191 
192  // Number of cycles with empty (or not empty) readyList, per execution
193  // resource, when the CU is active (not sleeping)
196 
197  // Number of cycles, per execution resource, when at least one wave
198  // was on the readyList and picked by scheduler, but was unable to be
199  // added to the schList, when the CU is active (not sleeping)
201 
202  // Number of cycles, per execution resource, when a wave is selected
203  // as candidate for dispatchList from schList
204  // Note: may be arbitrated off dispatchList (e.g., LDS arbitration)
206 
207  // Per execution resource stat, incremented once per cycle if no wave
208  // was selected as candidate for dispatch and moved to dispatchList
210 
211  // Number of times a wave is selected by the scheduler but cannot
212  // be added to the schList due to register files not being able to
213  // support reads or writes of operands. RF_ACCESS_NRDY condition is
214  // always incremented if at least one read/write not supported, other
215  // conditions are incremented independently from each other.
217 
218  // Number of times a wave is executing FLAT instruction and
219  // forces another wave occupying its required local memory resource
220  // to be deselected for execution, and placed back on schList
222 
223  // Count of times VRF and/or SRF blocks waves on schList from
224  // performing RFBUSY->RFREADY transition
226 
227  // Count of times resource required for dispatch is not ready and
228  // blocks wave in RFREADY state on schList from potentially moving
229  // to dispatchList
231  } stats;
232 };
233 
234 } // namespace gem5
235 
236 #endif // __SCHEDULE_STAGE_HH__
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1930
gem5::ScheduleStage::wavesInSch
std::unordered_set< uint64_t > wavesInSch
Definition: schedule_stage.hh:174
gem5::VegaISA::s
Bitfield< 1 > s
Definition: pagetable.hh:64
gem5::ScheduleStage::fromScoreboardCheck
ScoreboardCheckToSchedule & fromScoreboardCheck
Definition: schedule_stage.hh:126
gem5::ScheduleStage::scheduleRfDestOperands
void scheduleRfDestOperands()
Definition: schedule_stage.cc:262
gem5::ScheduleStage::reinsertToSchList
void reinsertToSchList(int exeType, const GPUDynInstPtr &gpu_dyn_inst)
Definition: schedule_stage.cc:362
gem5::ScheduleStage::ScheduleStageStats::addToSchListStalls
statistics::Vector addToSchListStalls
Definition: schedule_stage.hh:200
gem5::ScheduleStage::ScheduleStageStats::ldsBusArbStalls
statistics::Scalar ldsBusArbStalls
Definition: schedule_stage.hh:221
gem5::ScheduleStage::SCH_FLAT_MEM_FIFO_NRDY
@ SCH_FLAT_MEM_FIFO_NRDY
Definition: schedule_stage.hh:93
group.hh
gem5::ScheduleStage::SCH_NRDY_CONDITIONS
@ SCH_NRDY_CONDITIONS
Definition: schedule_stage.hh:95
gem5::ScheduleStage::RFREADY
@ RFREADY
Definition: schedule_stage.hh:121
gem5::ScheduleStage::SCH_SRF_RD_ACCESS_NRDY
@ SCH_SRF_RD_ACCESS_NRDY
Definition: schedule_stage.hh:108
gem5::ScheduleStage::SCH_RF_ACCESS_NRDY
@ SCH_RF_ACCESS_NRDY
Definition: schedule_stage.hh:110
gem5::ScheduleToExecute
Communication interface between Schedule and Execute stages.
Definition: comm.hh:98
gem5::ScheduleStage::SCH_RDY
@ SCH_RDY
Definition: schedule_stage.hh:94
gem5::ScheduleStage::scheduler
std::vector< Scheduler > scheduler
Definition: schedule_stage.hh:131
gem5::ScheduleStage::SchNonRdyType
SchNonRdyType
Definition: schedule_stage.hh:74
gem5::Wavefront
Definition: wavefront.hh:60
gem5::ScheduleStage::scalarMemIssueRdy
bool scalarMemIssueRdy
Definition: schedule_stage.hh:146
gem5::ScheduleStage::reserveResources
void reserveResources()
Definition: schedule_stage.cc:722
gem5::ScheduleStage::schList
std::vector< std::deque< std::pair< GPUDynInstPtr, SCH_STATUS > > > schList
Definition: schedule_stage.hh:185
gem5::ScheduleStage::SCH_FLAT_MEM_REQS_NRDY
@ SCH_FLAT_MEM_REQS_NRDY
Definition: schedule_stage.hh:92
gem5::ScheduleStage::locMemIssueRdy
bool locMemIssueRdy
Definition: schedule_stage.hh:150
gem5::ScheduleStage::SCH_VECTOR_ALU_NRDY
@ SCH_VECTOR_ALU_NRDY
Definition: schedule_stage.hh:77
misc.hh
gem5::ScheduleStage::ScheduleStageStats::rfAccessStalls
statistics::Vector rfAccessStalls
Definition: schedule_stage.hh:216
gem5::ScheduleStage::schopdnonrdytype_e
schopdnonrdytype_e
Definition: schedule_stage.hh:97
gem5::statistics::Vector
A vector of scalar stats.
Definition: statistics.hh:2006
gem5::VegaISA::w
Bitfield< 6 > w
Definition: pagetable.hh:59
std::vector
STL vector class.
Definition: stl.hh:37
gem5::ScheduleStage::dispatchReady
bool dispatchReady(const GPUDynInstPtr &gpu_dyn_inst)
Definition: schedule_stage.cc:416
gem5::ScheduleStage::SCH_FLAT_MEM_ISSUE_NRDY
@ SCH_FLAT_MEM_ISSUE_NRDY
Definition: schedule_stage.hh:89
gem5::ScheduleStage::vectorAluRdy
bool vectorAluRdy
Definition: schedule_stage.hh:143
gem5::ScheduleStage
Definition: schedule_stage.hh:62
gem5::ScheduleStage::scalarMemBusRdy
bool scalarMemBusRdy
Definition: schedule_stage.hh:145
gem5::ScheduleStage::scalarAluRdy
bool scalarAluRdy
Definition: schedule_stage.hh:144
gem5::ScheduleStage::~ScheduleStage
~ScheduleStage()
Definition: schedule_stage.cc:68
gem5::ScheduleStage::SCH_LOCAL_MEM_FIFO_NRDY
@ SCH_LOCAL_MEM_FIFO_NRDY
Definition: schedule_stage.hh:88
gem5::ScheduleStage::ScheduleStageStats::rdyListEmpty
statistics::Vector rdyListEmpty
Definition: schedule_stage.hh:194
gem5::ScheduleStage::toExecute
ScheduleToExecute & toExecute
Definition: schedule_stage.hh:127
gem5::ComputeUnit
Definition: compute_unit.hh:201
gem5::ScheduleStage::fillDispatchList
void fillDispatchList()
Definition: schedule_stage.cc:556
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::ScheduleStage::SCH_RF_OPD_NRDY_CONDITIONS
@ SCH_RF_OPD_NRDY_CONDITIONS
Definition: schedule_stage.hh:102
gem5::ScheduleStage::init
void init()
Definition: schedule_stage.cc:76
gem5::ScheduleStage::ScheduleStageStats::schListToDispList
statistics::Vector schListToDispList
Definition: schedule_stage.hh:205
gem5::ScheduleStage::schrfaccessnonrdytype_e
schrfaccessnonrdytype_e
Definition: schedule_stage.hh:104
gem5::ScheduleStage::SCH_RF_OPD_NRDY
@ SCH_RF_OPD_NRDY
Definition: schedule_stage.hh:101
statistics.hh
gem5::ScheduleStage::addToSchList
bool addToSchList(int exeType, const GPUDynInstPtr &gpu_dyn_inst)
Definition: schedule_stage.cc:294
gem5::ScheduleStage::SCH_VECTOR_MEM_ISSUE_NRDY
@ SCH_VECTOR_MEM_ISSUE_NRDY
Definition: schedule_stage.hh:78
gem5::ScheduleStage::ScheduleStage
ScheduleStage(const ComputeUnitParams &p, ComputeUnit &cu, ScoreboardCheckToSchedule &from_scoreboard_check, ScheduleToExecute &to_execute)
Definition: schedule_stage.cc:48
gem5::ScheduleStage::SCH_CEDE_SIMD_NRDY
@ SCH_CEDE_SIMD_NRDY
Definition: schedule_stage.hh:82
gem5::ScheduleStage::arbitrateVrfToLdsBus
void arbitrateVrfToLdsBus()
Definition: schedule_stage.cc:625
gem5::ScheduleStage::deleteFromSch
void deleteFromSch(Wavefront *w)
Definition: schedule_stage.cc:788
gem5::ScheduleStage::checkRfOperandReadComplete
void checkRfOperandReadComplete()
Definition: schedule_stage.cc:666
gem5::ScheduleStage::SCH_FLAT_MEM_BUS_BUSY_NRDY
@ SCH_FLAT_MEM_BUS_BUSY_NRDY
Definition: schedule_stage.hh:90
gem5::ScheduleStage::ScheduleStageStats::ScheduleStageStats
ScheduleStageStats(statistics::Group *parent, int num_exec_units)
Definition: schedule_stage.cc:793
gem5::ScheduleStage::ScheduleStageStats::schListToDispListStalls
statistics::Vector schListToDispListStalls
Definition: schedule_stage.hh:209
gem5::ScheduleStage::ScheduleStageStats::rdyListNotEmpty
statistics::Vector rdyListNotEmpty
Definition: schedule_stage.hh:195
gem5::ScheduleStage::ScheduleStageStats::opdNrdyStalls
statistics::Vector opdNrdyStalls
Definition: schedule_stage.hh:225
gem5::ScheduleStage::_name
const std::string _name
Definition: schedule_stage.hh:133
gem5::DISPATCH_STATUS
DISPATCH_STATUS
Definition: exec_stage.hh:59
scheduler.hh
gem5::ScheduleStage::SCH_VECTOR_MEM_REQS_NRDY
@ SCH_VECTOR_MEM_REQS_NRDY
Definition: schedule_stage.hh:81
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:49
gem5::ScheduleStage::SCH_LOCAL_MEM_BUS_BUSY_NRDY
@ SCH_LOCAL_MEM_BUS_BUSY_NRDY
Definition: schedule_stage.hh:87
gem5::ScheduleStage::SCH_SCALAR_MEM_ISSUE_NRDY
@ SCH_SCALAR_MEM_ISSUE_NRDY
Definition: schedule_stage.hh:83
gem5::ScheduleStage::SCH_LOCAL_MEM_ISSUE_NRDY
@ SCH_LOCAL_MEM_ISSUE_NRDY
Definition: schedule_stage.hh:86
gem5::ScheduleStage::SCH_VRF_WR_ACCESS_NRDY
@ SCH_VRF_WR_ACCESS_NRDY
Definition: schedule_stage.hh:107
gem5::ScheduleStage::checkMemResources
void checkMemResources()
Definition: schedule_stage.cc:378
gem5::ScheduleStage::SCH_SCALAR_MEM_FIFO_NRDY
@ SCH_SCALAR_MEM_FIFO_NRDY
Definition: schedule_stage.hh:85
gem5::ScoreboardCheckToSchedule
Communication interface between ScoreboardCheck and Schedule stages.
Definition: comm.hh:62
gem5::ScheduleStage::stats
gem5::ScheduleStage::ScheduleStageStats stats
gem5::ScheduleStage::computeUnit
ComputeUnit & computeUnit
Definition: schedule_stage.hh:125
gem5::ScheduleStage::glbMemBusRdy
bool glbMemBusRdy
Definition: schedule_stage.hh:147
gem5::ScheduleStage::SCH_SRF_OPD_NRDY
@ SCH_SRF_OPD_NRDY
Definition: schedule_stage.hh:100
gem5::ScheduleStage::exec
void exec()
Definition: schedule_stage.cc:90
gem5::ScheduleStage::RFBUSY
@ RFBUSY
Definition: schedule_stage.hh:120
gem5::ScheduleStage::ScheduleStageStats::dispNrdyStalls
statistics::Vector dispNrdyStalls
Definition: schedule_stage.hh:230
gem5::ScheduleStage::SCH_SRF_WR_ACCESS_NRDY
@ SCH_SRF_WR_ACCESS_NRDY
Definition: schedule_stage.hh:109
gem5::ScheduleStage::SCH_VRF_OPD_NRDY
@ SCH_VRF_OPD_NRDY
Definition: schedule_stage.hh:99
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::ScheduleStage::glbMemIssueRdy
bool glbMemIssueRdy
Definition: schedule_stage.hh:148
gem5::ScheduleStage::SCH_STATUS
SCH_STATUS
Definition: schedule_stage.hh:118
gem5::ScheduleStage::SCH_VRF_RD_ACCESS_NRDY
@ SCH_VRF_RD_ACCESS_NRDY
Definition: schedule_stage.hh:106
gem5::ScheduleStage::SCH_VECTOR_MEM_BUS_BUSY_NRDY
@ SCH_VECTOR_MEM_BUS_BUSY_NRDY
Definition: schedule_stage.hh:79
gem5::ScheduleStage::SCH_VECTOR_MEM_COALESCER_NRDY
@ SCH_VECTOR_MEM_COALESCER_NRDY
Definition: schedule_stage.hh:80
gem5::ScheduleStage::SCH_RF_ACCESS_NRDY_CONDITIONS
@ SCH_RF_ACCESS_NRDY_CONDITIONS
Definition: schedule_stage.hh:111
gem5::ScheduleStage::ScheduleStageStats
Definition: schedule_stage.hh:188
gem5::ScheduleStage::SCH_SCALAR_MEM_BUS_BUSY_NRDY
@ SCH_SCALAR_MEM_BUS_BUSY_NRDY
Definition: schedule_stage.hh:84
gem5::ScheduleStage::schedRfWrites
bool schedRfWrites(int exeType, const GPUDynInstPtr &gpu_dyn_inst)
Definition: schedule_stage.cc:226
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ScheduleStage::locMemBusRdy
bool locMemBusRdy
Definition: schedule_stage.hh:149
exec_stage.hh
gem5::ScheduleStage::doDispatchListTransition
void doDispatchListTransition(int unitId, DISPATCH_STATUS s, const GPUDynInstPtr &gpu_dyn_inst)
Definition: schedule_stage.cc:213
gem5::ScheduleStage::name
const std::string & name() const
Definition: schedule_stage.hh:73
gem5::ScheduleStage::SCH_SCALAR_ALU_NRDY
@ SCH_SCALAR_ALU_NRDY
Definition: schedule_stage.hh:76
gem5::ScheduleStage::SCH_FLAT_MEM_COALESCER_NRDY
@ SCH_FLAT_MEM_COALESCER_NRDY
Definition: schedule_stage.hh:91

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