gem5  v22.1.0.0
simple_indirect.hh
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28 
29 #ifndef __CPU_PRED_INDIRECT_HH__
30 #define __CPU_PRED_INDIRECT_HH__
31 
32 #include <deque>
33 
34 #include "cpu/inst_seq.hh"
35 #include "cpu/pred/indirect.hh"
36 #include "params/SimpleIndirectPredictor.hh"
37 
38 namespace gem5
39 {
40 
41 namespace branch_prediction
42 {
43 
45 {
46  public:
47  SimpleIndirectPredictor(const SimpleIndirectPredictorParams &params);
48 
49  bool lookup(Addr br_addr, PCStateBase& br_target, ThreadID tid);
50  void recordIndirect(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num,
51  ThreadID tid);
52  void commit(InstSeqNum seq_num, ThreadID tid, void * indirect_history);
53  void squash(InstSeqNum seq_num, ThreadID tid);
54  void recordTarget(InstSeqNum seq_num, void * indirect_history,
55  const PCStateBase& target, ThreadID tid);
56  void genIndirectInfo(ThreadID tid, void* & indirect_history);
57  void updateDirectionInfo(ThreadID tid, bool actually_taken);
58  void deleteIndirectInfo(ThreadID tid, void * indirect_history);
59  void changeDirectionPrediction(ThreadID tid, void * indirect_history,
60  bool actually_taken);
61 
62  private:
63  const bool hashGHR;
64  const bool hashTargets;
65  const unsigned numSets;
66  const unsigned numWays;
67  const unsigned tagBits;
68  const unsigned pathLength;
69  const unsigned instShift;
70  const unsigned ghrNumBits;
71  const unsigned ghrMask;
72 
73  struct IPredEntry
74  {
75  Addr tag = 0;
76  std::unique_ptr<PCStateBase> target;
77  };
78 
80 
81  Addr getSetIndex(Addr br_addr, unsigned ghr, ThreadID tid);
82  Addr getTag(Addr br_addr);
83 
84  struct HistoryEntry
85  {
86  HistoryEntry(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num)
87  : pcAddr(br_addr), targetAddr(tgt_addr), seqNum(seq_num) { }
91  };
92 
93 
94  struct ThreadInfo
95  {
97  unsigned headHistEntry = 0;
98  unsigned ghr = 0;
99  };
100 
102 };
103 
104 } // namespace branch_prediction
105 } // namespace gem5
106 
107 #endif // __CPU_PRED_INDIRECT_HH__
void updateDirectionInfo(ThreadID tid, bool actually_taken)
std::vector< std::vector< IPredEntry > > targetCache
bool lookup(Addr br_addr, PCStateBase &br_target, ThreadID tid)
void genIndirectInfo(ThreadID tid, void *&indirect_history)
void commit(InstSeqNum seq_num, ThreadID tid, void *indirect_history)
void squash(InstSeqNum seq_num, ThreadID tid)
void changeDirectionPrediction(ThreadID tid, void *indirect_history, bool actually_taken)
SimpleIndirectPredictor(const SimpleIndirectPredictorParams &params)
void recordTarget(InstSeqNum seq_num, void *indirect_history, const PCStateBase &target, ThreadID tid)
Addr getSetIndex(Addr br_addr, unsigned ghr, ThreadID tid)
void recordIndirect(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num, ThreadID tid)
void deleteIndirectInfo(ThreadID tid, void *indirect_history)
STL deque class.
Definition: stl.hh:44
STL vector class.
Definition: stl.hh:37
const Params & params() const
Definition: sim_object.hh:176
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:235
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
uint64_t InstSeqNum
Definition: inst_seq.hh:40
HistoryEntry(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num)

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