gem5  v21.1.0.2
simple_indirect.hh
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28 
29 #ifndef __CPU_PRED_INDIRECT_HH__
30 #define __CPU_PRED_INDIRECT_HH__
31 
32 #include <deque>
33 
34 #include "config/the_isa.hh"
35 #include "cpu/inst_seq.hh"
36 #include "cpu/pred/indirect.hh"
37 #include "params/SimpleIndirectPredictor.hh"
38 
39 namespace gem5
40 {
41 
42 namespace branch_prediction
43 {
44 
46 {
47  public:
48  SimpleIndirectPredictor(const SimpleIndirectPredictorParams &params);
49 
50  bool lookup(Addr br_addr, TheISA::PCState& br_target, ThreadID tid);
51  void recordIndirect(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num,
52  ThreadID tid);
53  void commit(InstSeqNum seq_num, ThreadID tid, void * indirect_history);
54  void squash(InstSeqNum seq_num, ThreadID tid);
55  void recordTarget(InstSeqNum seq_num, void * indirect_history,
56  const TheISA::PCState& target, ThreadID tid);
57  void genIndirectInfo(ThreadID tid, void* & indirect_history);
58  void updateDirectionInfo(ThreadID tid, bool actually_taken);
59  void deleteIndirectInfo(ThreadID tid, void * indirect_history);
60  void changeDirectionPrediction(ThreadID tid, void * indirect_history,
61  bool actually_taken);
62 
63  private:
64  const bool hashGHR;
65  const bool hashTargets;
66  const unsigned numSets;
67  const unsigned numWays;
68  const unsigned tagBits;
69  const unsigned pathLength;
70  const unsigned instShift;
71  const unsigned ghrNumBits;
72  const unsigned ghrMask;
73 
74  struct IPredEntry
75  {
76  IPredEntry() : tag(0), target(0) { }
79  };
80 
82 
83  Addr getSetIndex(Addr br_addr, unsigned ghr, ThreadID tid);
84  Addr getTag(Addr br_addr);
85 
86  struct HistoryEntry
87  {
88  HistoryEntry(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num)
89  : pcAddr(br_addr), targetAddr(tgt_addr), seqNum(seq_num) { }
93  };
94 
95 
96  struct ThreadInfo
97  {
98  ThreadInfo() : headHistEntry(0), ghr(0) { }
99 
101  unsigned headHistEntry;
102  unsigned ghr;
103  };
104 
106 };
107 
108 } // namespace branch_prediction
109 } // namespace gem5
110 
111 #endif // __CPU_PRED_INDIRECT_HH__
gem5::branch_prediction::SimpleIndirectPredictor::numSets
const unsigned numSets
Definition: simple_indirect.hh:66
gem5::branch_prediction::SimpleIndirectPredictor::ThreadInfo::ThreadInfo
ThreadInfo()
Definition: simple_indirect.hh:98
gem5::branch_prediction::SimpleIndirectPredictor::getTag
Addr getTag(Addr br_addr)
Definition: simple_indirect.cc:238
gem5::branch_prediction::SimpleIndirectPredictor::updateDirectionInfo
void updateDirectionInfo(ThreadID tid, bool actually_taken)
Definition: simple_indirect.cc:78
gem5::branch_prediction::SimpleIndirectPredictor::instShift
const unsigned instShift
Definition: simple_indirect.hh:70
gem5::branch_prediction::SimpleIndirectPredictor::hashTargets
const bool hashTargets
Definition: simple_indirect.hh:65
gem5::branch_prediction::SimpleIndirectPredictor::HistoryEntry::seqNum
InstSeqNum seqNum
Definition: simple_indirect.hh:92
gem5::branch_prediction::SimpleIndirectPredictor::genIndirectInfo
void genIndirectInfo(ThreadID tid, void *&indirect_history)
Definition: simple_indirect.cc:68
gem5::branch_prediction::SimpleIndirectPredictor::hashGHR
const bool hashGHR
Definition: simple_indirect.hh:64
std::vector
STL vector class.
Definition: stl.hh:37
gem5::branch_prediction::SimpleIndirectPredictor::ghrMask
const unsigned ghrMask
Definition: simple_indirect.hh:72
gem5::branch_prediction::SimpleIndirectPredictor::HistoryEntry
Definition: simple_indirect.hh:86
inst_seq.hh
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::branch_prediction::SimpleIndirectPredictor::deleteIndirectInfo
void deleteIndirectInfo(ThreadID tid, void *indirect_history)
Definition: simple_indirect.cc:169
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::branch_prediction::SimpleIndirectPredictor::changeDirectionPrediction
void changeDirectionPrediction(ThreadID tid, void *indirect_history, bool actually_taken)
Definition: simple_indirect.cc:87
gem5::branch_prediction::SimpleIndirectPredictor::ThreadInfo
Definition: simple_indirect.hh:96
gem5::branch_prediction::SimpleIndirectPredictor::numWays
const unsigned numWays
Definition: simple_indirect.hh:67
gem5::branch_prediction::SimpleIndirectPredictor::ThreadInfo::ghr
unsigned ghr
Definition: simple_indirect.hh:102
indirect.hh
gem5::branch_prediction::SimpleIndirectPredictor::IPredEntry::target
TheISA::PCState target
Definition: simple_indirect.hh:78
gem5::branch_prediction::SimpleIndirectPredictor::targetCache
std::vector< std::vector< IPredEntry > > targetCache
Definition: simple_indirect.hh:81
gem5::branch_prediction::SimpleIndirectPredictor::getSetIndex
Addr getSetIndex(Addr br_addr, unsigned ghr, ThreadID tid)
Definition: simple_indirect.cc:218
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::branch_prediction::SimpleIndirectPredictor::IPredEntry
Definition: simple_indirect.hh:74
gem5::branch_prediction::SimpleIndirectPredictor::commit
void commit(InstSeqNum seq_num, ThreadID tid, void *indirect_history)
Definition: simple_indirect.cc:127
gem5::branch_prediction::SimpleIndirectPredictor::HistoryEntry::HistoryEntry
HistoryEntry(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num)
Definition: simple_indirect.hh:88
gem5::branch_prediction::SimpleIndirectPredictor::pathLength
const unsigned pathLength
Definition: simple_indirect.hh:69
gem5::branch_prediction::SimpleIndirectPredictor::squash
void squash(InstSeqNum seq_num, ThreadID tid)
Definition: simple_indirect.cc:150
gem5::branch_prediction::SimpleIndirectPredictor::ThreadInfo::pathHist
std::deque< HistoryEntry > pathHist
Definition: simple_indirect.hh:100
gem5::branch_prediction::SimpleIndirectPredictor::HistoryEntry::pcAddr
Addr pcAddr
Definition: simple_indirect.hh:90
gem5::branch_prediction::SimpleIndirectPredictor::ThreadInfo::headHistEntry
unsigned headHistEntry
Definition: simple_indirect.hh:101
gem5::branch_prediction::IndirectPredictor
Definition: indirect.hh:44
gem5::branch_prediction::SimpleIndirectPredictor::tagBits
const unsigned tagBits
Definition: simple_indirect.hh:68
std::deque
STL deque class.
Definition: stl.hh:44
gem5::branch_prediction::SimpleIndirectPredictor::IPredEntry::tag
Addr tag
Definition: simple_indirect.hh:77
gem5::branch_prediction::SimpleIndirectPredictor
Definition: simple_indirect.hh:45
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::branch_prediction::SimpleIndirectPredictor::recordTarget
void recordTarget(InstSeqNum seq_num, void *indirect_history, const TheISA::PCState &target, ThreadID tid)
Definition: simple_indirect.cc:179
gem5::branch_prediction::SimpleIndirectPredictor::threadInfo
std::vector< ThreadInfo > threadInfo
Definition: simple_indirect.hh:105
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::branch_prediction::SimpleIndirectPredictor::recordIndirect
void recordIndirect(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num, ThreadID tid)
Definition: simple_indirect.cc:118
gem5::branch_prediction::SimpleIndirectPredictor::lookup
bool lookup(Addr br_addr, TheISA::PCState &br_target, ThreadID tid)
Definition: simple_indirect.cc:96
gem5::branch_prediction::SimpleIndirectPredictor::HistoryEntry::targetAddr
Addr targetAddr
Definition: simple_indirect.hh:91
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::branch_prediction::SimpleIndirectPredictor::ghrNumBits
const unsigned ghrNumBits
Definition: simple_indirect.hh:71
gem5::branch_prediction::SimpleIndirectPredictor::IPredEntry::IPredEntry
IPredEntry()
Definition: simple_indirect.hh:76
gem5::branch_prediction::SimpleIndirectPredictor::SimpleIndirectPredictor
SimpleIndirectPredictor(const SimpleIndirectPredictorParams &params)
Definition: simple_indirect.cc:40

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