gem5::ArmISA::MMU::CachedState Struct Reference

#include <mmu.hh>

Public Member Functions
	CachedState (MMU *_mmu, bool stage2)
CachedState &	operator= (const CachedState &rhs)
void	updateMiscReg (ThreadContext *tc, ArmTranslationType tran_type)
vmid_t	getVMID (ThreadContext *tc) const
	Returns the current VMID (information stored in the VTTBR_EL2 register)

Public Attributes
MMU *	mmu
bool	isStage2 = false
CPSR	cpsr = 0
bool	aarch64 = false
ExceptionLevel	exceptionLevel = EL0
TranslationRegime	currRegime = TranslationRegime::EL10
SCTLR	sctlr = 0
SCR	scr = 0
bool	isPriv = false
bool	isSecure = false
TTBCR	ttbcr = 0
uint16_t	asid = 0
vmid_t	vmid = 0
PRRR	prrr = 0
NMRR	nmrr = 0
HCR	hcr = 0
uint32_t	dacr = 0
bool	miscRegValid = false
ArmTranslationType	curTranType = NormalTran
bool	stage2Req = false
bool	stage2DescReq = false
bool	directToStage2 = false
Memoizer< int, ThreadContext *, bool, bool, TCR, ExceptionLevel >	computeAddrTop

Detailed Description

Definition at line 134 of file mmu.hh.

Constructor & Destructor Documentation

CachedState()

gem5::ArmISA::MMU::CachedState::CachedState ( MMU * _mmu, bool stage2 )

inline

Definition at line 136 of file mmu.hh.

Member Function Documentation

getVMID()

vmid_t gem5::MMU::CachedState::getVMID

(

ThreadContext *

tc

)

const

Returns the current VMID (information stored in the VTTBR_EL2 register)

Definition at line 1140 of file mmu.cc.

References gem5::bits(), gem5::ArmISA::EL2, gem5::ArmISA::ELIs64(), gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1, gem5::ArmISA::MISCREG_VTCR_EL2, gem5::ArmISA::MISCREG_VTTBR_EL2, panic, gem5::ThreadContext::readMiscReg(), and vmid.

operator=()

CachedState & gem5::ArmISA::MMU::CachedState::operator= ( const CachedState & rhs )

inline

Definition at line 142 of file mmu.hh.

References aarch64, asid, computeAddrTop, cpsr, currRegime, curTranType, dacr, directToStage2, exceptionLevel, hcr, isPriv, isSecure, isStage2, miscRegValid, nmrr, prrr, scr, sctlr, stage2DescReq, stage2Req, ttbcr, and vmid.

updateMiscReg()

void gem5::MMU::CachedState::updateMiscReg	(	ThreadContext *	tc,
		ArmTranslationType	tran_type )

Definition at line 1209 of file mmu.cc.

References gem5::ArmISA::aarch64, gem5::ArmISA::asid, gem5::bits(), gem5::ArmISA::EL0, gem5::ArmISA::EL10, gem5::ArmISA::EL2, gem5::ArmISA::EL20, gem5::ArmISA::EL2Enabled(), gem5::ArmISA::EL3, gem5::ArmISA::ELIs64(), gem5::ArmISA::HaveExt(), gem5::ArmISA::MMU::HypMode, gem5::ArmISA::isSecure(), gem5::ArmISA::longDescFormatInUse(), gem5::ArmISA::MISCREG_CONTEXTIDR, gem5::ArmISA::MISCREG_CPSR, gem5::ArmISA::MISCREG_DACR, gem5::ArmISA::MISCREG_HCR_EL2, gem5::ArmISA::MISCREG_HSCTLR, gem5::ArmISA::MISCREG_NMRR, gem5::ArmISA::MISCREG_PRRR, gem5::ArmISA::MISCREG_SCR_EL3, gem5::ArmISA::MISCREG_SCTLR, gem5::ArmISA::MISCREG_SCTLR_EL1, gem5::ArmISA::MISCREG_SCTLR_EL2, gem5::ArmISA::MISCREG_SCTLR_EL3, gem5::ArmISA::MISCREG_TCR_EL1, gem5::ArmISA::MISCREG_TCR_EL2, gem5::ArmISA::MISCREG_TCR_EL3, gem5::ArmISA::MISCREG_TTBCR, gem5::ArmISA::MISCREG_TTBR0, gem5::ArmISA::MISCREG_TTBR0_EL1, gem5::ArmISA::MISCREG_TTBR0_EL2, gem5::ArmISA::MISCREG_TTBR1, gem5::ArmISA::MISCREG_TTBR1_EL1, gem5::ArmISA::MISCREG_TTBR1_EL2, gem5::ArmISA::MISCREG_VTTBR, gem5::ArmISA::MODE_USER, gem5::ThreadContext::readMiscReg(), gem5::ArmISA::MMU::S1CTran, gem5::ArmISA::MMU::S1E1Tran, gem5::ArmISA::MMU::S1S2NsTran, gem5::ArmISA::snsBankedIndex(), gem5::ArmISA::translationEl(), gem5::ArmISA::translationRegime(), gem5::ArmISA::MMU::tranTypeEL(), and gem5::ArmISA::vm.

Referenced by gem5::ArmISA::MMU::updateMiscReg().

Member Data Documentation

aarch64

bool gem5::ArmISA::MMU::CachedState::aarch64 = false

Definition at line 181 of file mmu.hh.

Referenced by operator=().

asid

uint16_t gem5::ArmISA::MMU::CachedState::asid = 0

Definition at line 189 of file mmu.hh.

Referenced by operator=().

computeAddrTop

Memoizer<int, ThreadContext*, bool, bool, TCR, ExceptionLevel> gem5::ArmISA::MMU::CachedState::computeAddrTop

Definition at line 212 of file mmu.hh.

Referenced by gem5::ArmISA::MMU::invalidateMiscReg(), and operator=().

cpsr

CPSR gem5::ArmISA::MMU::CachedState::cpsr = 0

Definition at line 180 of file mmu.hh.

Referenced by operator=().

currRegime

TranslationRegime gem5::ArmISA::MMU::CachedState::currRegime = TranslationRegime::EL10

Definition at line 183 of file mmu.hh.

Referenced by operator=().

curTranType

ArmTranslationType gem5::ArmISA::MMU::CachedState::curTranType = NormalTran

Definition at line 196 of file mmu.hh.

Referenced by operator=().

dacr

uint32_t gem5::ArmISA::MMU::CachedState::dacr = 0

Definition at line 194 of file mmu.hh.

Referenced by operator=().

directToStage2

bool gem5::ArmISA::MMU::CachedState::directToStage2 = false

Definition at line 209 of file mmu.hh.

Referenced by operator=().

exceptionLevel

ExceptionLevel gem5::ArmISA::MMU::CachedState::exceptionLevel = EL0

Definition at line 182 of file mmu.hh.

Referenced by operator=().

hcr

HCR gem5::ArmISA::MMU::CachedState::hcr = 0

Definition at line 193 of file mmu.hh.

Referenced by operator=().

isPriv

bool gem5::ArmISA::MMU::CachedState::isPriv = false

Definition at line 186 of file mmu.hh.

Referenced by operator=().

isSecure

bool gem5::ArmISA::MMU::CachedState::isSecure = false

Definition at line 187 of file mmu.hh.

Referenced by operator=().

isStage2

bool gem5::ArmISA::MMU::CachedState::isStage2 = false

Definition at line 179 of file mmu.hh.

Referenced by operator=().

miscRegValid

bool gem5::ArmISA::MMU::CachedState::miscRegValid = false

Definition at line 195 of file mmu.hh.

Referenced by gem5::ArmISA::MMU::drainResume(), gem5::ArmISA::MMU::invalidateMiscReg(), and operator=().

mmu

MMU* gem5::ArmISA::MMU::CachedState::mmu

Definition at line 178 of file mmu.hh.

nmrr

NMRR gem5::ArmISA::MMU::CachedState::nmrr = 0

Definition at line 192 of file mmu.hh.

Referenced by operator=().

prrr

PRRR gem5::ArmISA::MMU::CachedState::prrr = 0

Definition at line 191 of file mmu.hh.

Referenced by operator=().

scr

SCR gem5::ArmISA::MMU::CachedState::scr = 0

Definition at line 185 of file mmu.hh.

Referenced by operator=().

sctlr

SCTLR gem5::ArmISA::MMU::CachedState::sctlr = 0

Definition at line 184 of file mmu.hh.

Referenced by operator=().

stage2DescReq

bool gem5::ArmISA::MMU::CachedState::stage2DescReq = false

Definition at line 205 of file mmu.hh.

Referenced by operator=().

stage2Req

bool gem5::ArmISA::MMU::CachedState::stage2Req = false

Definition at line 199 of file mmu.hh.

Referenced by operator=().

ttbcr

TTBCR gem5::ArmISA::MMU::CachedState::ttbcr = 0

Definition at line 188 of file mmu.hh.

Referenced by operator=().

vmid

vmid_t gem5::ArmISA::MMU::CachedState::vmid = 0

Definition at line 190 of file mmu.hh.

Referenced by getVMID(), and operator=().

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The documentation for this struct was generated from the following files:

• arch/arm/mmu.hh
• arch/arm/mmu.cc