gem5  v22.1.0.0
misc.cc
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1 /*
2  * Copyright (c) 2010-2013, 2015-2022 Arm Limited
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37 
38 #include "arch/arm/regs/misc.hh"
39 
40 #include <tuple>
41 
42 #include "arch/arm/insts/misc64.hh"
43 #include "arch/arm/isa.hh"
44 #include "base/logging.hh"
45 #include "cpu/thread_context.hh"
47 #include "sim/full_system.hh"
48 
49 namespace gem5
50 {
51 
52 namespace ArmISA
53 {
54 
55 namespace
56 {
57 
58 std::unordered_map<MiscRegNum32, MiscRegIndex> miscRegNum32ToIdx{
59  // MCR/MRC regs
60  { MiscRegNum32(14, 0, 0, 0, 0), MISCREG_DBGDIDR },
61  { MiscRegNum32(14, 0, 0, 0, 2), MISCREG_DBGDTRRXext },
62  { MiscRegNum32(14, 0, 0, 0, 4), MISCREG_DBGBVR0 },
63  { MiscRegNum32(14, 0, 0, 0, 5), MISCREG_DBGBCR0 },
64  { MiscRegNum32(14, 0, 0, 0, 6), MISCREG_DBGWVR0 },
65  { MiscRegNum32(14, 0, 0, 0, 7), MISCREG_DBGWCR0 },
66  { MiscRegNum32(14, 0, 0, 1, 0), MISCREG_DBGDSCRint },
67  { MiscRegNum32(14, 0, 0, 1, 4), MISCREG_DBGBVR1 },
68  { MiscRegNum32(14, 0, 0, 1, 5), MISCREG_DBGBCR1 },
69  { MiscRegNum32(14, 0, 0, 1, 6), MISCREG_DBGWVR1 },
70  { MiscRegNum32(14, 0, 0, 1, 7), MISCREG_DBGWCR1 },
71  { MiscRegNum32(14, 0, 0, 2, 2), MISCREG_DBGDSCRext },
72  { MiscRegNum32(14, 0, 0, 2, 4), MISCREG_DBGBVR2 },
73  { MiscRegNum32(14, 0, 0, 2, 5), MISCREG_DBGBCR2 },
74  { MiscRegNum32(14, 0, 0, 2, 6), MISCREG_DBGWVR2 },
75  { MiscRegNum32(14, 0, 0, 2, 7), MISCREG_DBGWCR2 },
76  { MiscRegNum32(14, 0, 0, 3, 2), MISCREG_DBGDTRTXext },
77  { MiscRegNum32(14, 0, 0, 3, 4), MISCREG_DBGBVR3 },
78  { MiscRegNum32(14, 0, 0, 3, 5), MISCREG_DBGBCR3 },
79  { MiscRegNum32(14, 0, 0, 3, 6), MISCREG_DBGWVR3 },
80  { MiscRegNum32(14, 0, 0, 3, 7), MISCREG_DBGWCR3 },
81  { MiscRegNum32(14, 0, 0, 4, 4), MISCREG_DBGBVR4 },
82  { MiscRegNum32(14, 0, 0, 4, 5), MISCREG_DBGBCR4 },
83  { MiscRegNum32(14, 0, 0, 4, 6), MISCREG_DBGWVR4 },
84  { MiscRegNum32(14, 0, 0, 4, 7), MISCREG_DBGWCR4 },
85  { MiscRegNum32(14, 0, 0, 5, 4), MISCREG_DBGBVR5 },
86  { MiscRegNum32(14, 0, 0, 5, 5), MISCREG_DBGBCR5 },
87  { MiscRegNum32(14, 0, 0, 5, 6), MISCREG_DBGWVR5 },
88  { MiscRegNum32(14, 0, 0, 5, 7), MISCREG_DBGWCR5 },
89  { MiscRegNum32(14, 0, 0, 6, 2), MISCREG_DBGOSECCR },
90  { MiscRegNum32(14, 0, 0, 6, 4), MISCREG_DBGBVR6 },
91  { MiscRegNum32(14, 0, 0, 6, 5), MISCREG_DBGBCR6 },
92  { MiscRegNum32(14, 0, 0, 6, 6), MISCREG_DBGWVR6 },
93  { MiscRegNum32(14, 0, 0, 6, 7), MISCREG_DBGWCR6 },
94  { MiscRegNum32(14, 0, 0, 7, 0), MISCREG_DBGVCR },
95  { MiscRegNum32(14, 0, 0, 7, 4), MISCREG_DBGBVR7 },
96  { MiscRegNum32(14, 0, 0, 7, 5), MISCREG_DBGBCR7 },
97  { MiscRegNum32(14, 0, 0, 7, 6), MISCREG_DBGWVR7 },
98  { MiscRegNum32(14, 0, 0, 7, 7), MISCREG_DBGWCR7 },
99  { MiscRegNum32(14, 0, 0, 8, 4), MISCREG_DBGBVR8 },
100  { MiscRegNum32(14, 0, 0, 8, 5), MISCREG_DBGBCR8 },
101  { MiscRegNum32(14, 0, 0, 8, 6), MISCREG_DBGWVR8 },
102  { MiscRegNum32(14, 0, 0, 8, 7), MISCREG_DBGWCR8 },
103  { MiscRegNum32(14, 0, 0, 9, 4), MISCREG_DBGBVR9 },
104  { MiscRegNum32(14, 0, 0, 9, 5), MISCREG_DBGBCR9 },
105  { MiscRegNum32(14, 0, 0, 9, 6), MISCREG_DBGWVR9 },
106  { MiscRegNum32(14, 0, 0, 9, 7), MISCREG_DBGWCR9 },
107  { MiscRegNum32(14, 0, 0, 10, 4), MISCREG_DBGBVR10 },
108  { MiscRegNum32(14, 0, 0, 10, 5), MISCREG_DBGBCR10 },
109  { MiscRegNum32(14, 0, 0, 10, 6), MISCREG_DBGWVR10 },
110  { MiscRegNum32(14, 0, 0, 10, 7), MISCREG_DBGWCR10 },
111  { MiscRegNum32(14, 0, 0, 11, 4), MISCREG_DBGBVR11 },
112  { MiscRegNum32(14, 0, 0, 11, 5), MISCREG_DBGBCR11 },
113  { MiscRegNum32(14, 0, 0, 11, 6), MISCREG_DBGWVR11 },
114  { MiscRegNum32(14, 0, 0, 11, 7), MISCREG_DBGWCR11 },
115  { MiscRegNum32(14, 0, 0, 12, 4), MISCREG_DBGBVR12 },
116  { MiscRegNum32(14, 0, 0, 12, 5), MISCREG_DBGBCR12 },
117  { MiscRegNum32(14, 0, 0, 12, 6), MISCREG_DBGWVR12 },
118  { MiscRegNum32(14, 0, 0, 12, 7), MISCREG_DBGWCR12 },
119  { MiscRegNum32(14, 0, 0, 13, 4), MISCREG_DBGBVR13 },
120  { MiscRegNum32(14, 0, 0, 13, 5), MISCREG_DBGBCR13 },
121  { MiscRegNum32(14, 0, 0, 13, 6), MISCREG_DBGWVR13 },
122  { MiscRegNum32(14, 0, 0, 13, 7), MISCREG_DBGWCR13 },
123  { MiscRegNum32(14, 0, 0, 14, 4), MISCREG_DBGBVR14 },
124  { MiscRegNum32(14, 0, 0, 14, 5), MISCREG_DBGBCR14 },
125  { MiscRegNum32(14, 0, 0, 14, 6), MISCREG_DBGWVR14 },
126  { MiscRegNum32(14, 0, 0, 14, 7), MISCREG_DBGWCR14 },
127  { MiscRegNum32(14, 0, 0, 15, 4), MISCREG_DBGBVR15 },
128  { MiscRegNum32(14, 0, 0, 15, 5), MISCREG_DBGBCR15 },
129  { MiscRegNum32(14, 0, 0, 15, 6), MISCREG_DBGWVR15 },
130  { MiscRegNum32(14, 0, 0, 15, 7), MISCREG_DBGWCR15 },
131  { MiscRegNum32(14, 0, 1, 0, 1), MISCREG_DBGBXVR0 },
132  { MiscRegNum32(14, 0, 1, 0, 4), MISCREG_DBGOSLAR },
133  { MiscRegNum32(14, 0, 1, 1, 1), MISCREG_DBGBXVR1 },
134  { MiscRegNum32(14, 0, 1, 1, 4), MISCREG_DBGOSLSR },
135  { MiscRegNum32(14, 0, 1, 2, 1), MISCREG_DBGBXVR2 },
136  { MiscRegNum32(14, 0, 1, 3, 1), MISCREG_DBGBXVR3 },
137  { MiscRegNum32(14, 0, 1, 3, 4), MISCREG_DBGOSDLR },
138  { MiscRegNum32(14, 0, 1, 4, 1), MISCREG_DBGBXVR4 },
139  { MiscRegNum32(14, 0, 1, 4, 4), MISCREG_DBGPRCR },
140  { MiscRegNum32(14, 0, 1, 5, 1), MISCREG_DBGBXVR5 },
141  { MiscRegNum32(14, 0, 1, 6, 1), MISCREG_DBGBXVR6 },
142  { MiscRegNum32(14, 0, 1, 7, 1), MISCREG_DBGBXVR7 },
143  { MiscRegNum32(14, 0, 1, 8, 1), MISCREG_DBGBXVR8 },
144  { MiscRegNum32(14, 0, 1, 9, 1), MISCREG_DBGBXVR9 },
145  { MiscRegNum32(14, 0, 1, 10, 1), MISCREG_DBGBXVR10 },
146  { MiscRegNum32(14, 0, 1, 11, 1), MISCREG_DBGBXVR11 },
147  { MiscRegNum32(14, 0, 1, 12, 1), MISCREG_DBGBXVR12 },
148  { MiscRegNum32(14, 0, 1, 13, 1), MISCREG_DBGBXVR13 },
149  { MiscRegNum32(14, 0, 1, 14, 1), MISCREG_DBGBXVR14 },
150  { MiscRegNum32(14, 0, 1, 15, 1), MISCREG_DBGBXVR15 },
151  { MiscRegNum32(14, 6, 1, 0, 0), MISCREG_TEEHBR },
152  { MiscRegNum32(14, 7, 0, 0, 0), MISCREG_JIDR },
153  { MiscRegNum32(14, 7, 1, 0, 0), MISCREG_JOSCR },
154  { MiscRegNum32(14, 7, 2, 0, 0), MISCREG_JMCR },
155  { MiscRegNum32(15, 0, 0, 0, 0), MISCREG_MIDR },
156  { MiscRegNum32(15, 0, 0, 0, 1), MISCREG_CTR },
157  { MiscRegNum32(15, 0, 0, 0, 2), MISCREG_TCMTR },
158  { MiscRegNum32(15, 0, 0, 0, 3), MISCREG_TLBTR },
159  { MiscRegNum32(15, 0, 0, 0, 4), MISCREG_MIDR },
160  { MiscRegNum32(15, 0, 0, 0, 5), MISCREG_MPIDR },
161  { MiscRegNum32(15, 0, 0, 0, 6), MISCREG_REVIDR },
162  { MiscRegNum32(15, 0, 0, 0, 7), MISCREG_MIDR },
163  { MiscRegNum32(15, 0, 0, 1, 0), MISCREG_ID_PFR0 },
164  { MiscRegNum32(15, 0, 0, 1, 1), MISCREG_ID_PFR1 },
165  { MiscRegNum32(15, 0, 0, 1, 2), MISCREG_ID_DFR0 },
166  { MiscRegNum32(15, 0, 0, 1, 3), MISCREG_ID_AFR0 },
167  { MiscRegNum32(15, 0, 0, 1, 4), MISCREG_ID_MMFR0 },
168  { MiscRegNum32(15, 0, 0, 1, 5), MISCREG_ID_MMFR1 },
169  { MiscRegNum32(15, 0, 0, 1, 6), MISCREG_ID_MMFR2 },
170  { MiscRegNum32(15, 0, 0, 1, 7), MISCREG_ID_MMFR3 },
171  { MiscRegNum32(15, 0, 0, 2, 0), MISCREG_ID_ISAR0 },
172  { MiscRegNum32(15, 0, 0, 2, 1), MISCREG_ID_ISAR1 },
173  { MiscRegNum32(15, 0, 0, 2, 2), MISCREG_ID_ISAR2 },
174  { MiscRegNum32(15, 0, 0, 2, 3), MISCREG_ID_ISAR3 },
175  { MiscRegNum32(15, 0, 0, 2, 4), MISCREG_ID_ISAR4 },
176  { MiscRegNum32(15, 0, 0, 2, 5), MISCREG_ID_ISAR5 },
177  { MiscRegNum32(15, 0, 0, 2, 6), MISCREG_ID_MMFR4 },
178  { MiscRegNum32(15, 0, 0, 2, 7), MISCREG_ID_ISAR6 },
179  { MiscRegNum32(15, 0, 0, 3, 0), MISCREG_RAZ },
180  { MiscRegNum32(15, 0, 0, 3, 1), MISCREG_RAZ },
181  { MiscRegNum32(15, 0, 0, 3, 2), MISCREG_RAZ },
182  { MiscRegNum32(15, 0, 0, 3, 3), MISCREG_RAZ },
183  { MiscRegNum32(15, 0, 0, 3, 4), MISCREG_RAZ },
184  { MiscRegNum32(15, 0, 0, 3, 5), MISCREG_RAZ },
185  { MiscRegNum32(15, 0, 0, 3, 6), MISCREG_RAZ },
186  { MiscRegNum32(15, 0, 0, 3, 7), MISCREG_RAZ },
187  { MiscRegNum32(15, 0, 0, 4, 0), MISCREG_RAZ },
188  { MiscRegNum32(15, 0, 0, 4, 1), MISCREG_RAZ },
189  { MiscRegNum32(15, 0, 0, 4, 2), MISCREG_RAZ },
190  { MiscRegNum32(15, 0, 0, 4, 3), MISCREG_RAZ },
191  { MiscRegNum32(15, 0, 0, 4, 4), MISCREG_RAZ },
192  { MiscRegNum32(15, 0, 0, 4, 5), MISCREG_RAZ },
193  { MiscRegNum32(15, 0, 0, 4, 6), MISCREG_RAZ },
194  { MiscRegNum32(15, 0, 0, 4, 7), MISCREG_RAZ },
195  { MiscRegNum32(15, 0, 0, 5, 0), MISCREG_RAZ },
196  { MiscRegNum32(15, 0, 0, 5, 1), MISCREG_RAZ },
197  { MiscRegNum32(15, 0, 0, 5, 2), MISCREG_RAZ },
198  { MiscRegNum32(15, 0, 0, 5, 3), MISCREG_RAZ },
199  { MiscRegNum32(15, 0, 0, 5, 4), MISCREG_RAZ },
200  { MiscRegNum32(15, 0, 0, 5, 5), MISCREG_RAZ },
201  { MiscRegNum32(15, 0, 0, 5, 6), MISCREG_RAZ },
202  { MiscRegNum32(15, 0, 0, 5, 7), MISCREG_RAZ },
203  { MiscRegNum32(15, 0, 0, 6, 0), MISCREG_RAZ },
204  { MiscRegNum32(15, 0, 0, 6, 1), MISCREG_RAZ },
205  { MiscRegNum32(15, 0, 0, 6, 2), MISCREG_RAZ },
206  { MiscRegNum32(15, 0, 0, 6, 3), MISCREG_RAZ },
207  { MiscRegNum32(15, 0, 0, 6, 4), MISCREG_RAZ },
208  { MiscRegNum32(15, 0, 0, 6, 5), MISCREG_RAZ },
209  { MiscRegNum32(15, 0, 0, 6, 6), MISCREG_RAZ },
210  { MiscRegNum32(15, 0, 0, 6, 7), MISCREG_RAZ },
211  { MiscRegNum32(15, 0, 0, 7, 0), MISCREG_RAZ },
212  { MiscRegNum32(15, 0, 0, 7, 1), MISCREG_RAZ },
213  { MiscRegNum32(15, 0, 0, 7, 2), MISCREG_RAZ },
214  { MiscRegNum32(15, 0, 0, 7, 3), MISCREG_RAZ },
215  { MiscRegNum32(15, 0, 0, 7, 4), MISCREG_RAZ },
216  { MiscRegNum32(15, 0, 0, 7, 5), MISCREG_RAZ },
217  { MiscRegNum32(15, 0, 0, 7, 6), MISCREG_RAZ },
218  { MiscRegNum32(15, 0, 0, 7, 7), MISCREG_RAZ },
219  { MiscRegNum32(15, 0, 0, 8, 0), MISCREG_RAZ },
220  { MiscRegNum32(15, 0, 0, 8, 1), MISCREG_RAZ },
221  { MiscRegNum32(15, 0, 0, 8, 2), MISCREG_RAZ },
222  { MiscRegNum32(15, 0, 0, 8, 3), MISCREG_RAZ },
223  { MiscRegNum32(15, 0, 0, 8, 4), MISCREG_RAZ },
224  { MiscRegNum32(15, 0, 0, 8, 5), MISCREG_RAZ },
225  { MiscRegNum32(15, 0, 0, 8, 6), MISCREG_RAZ },
226  { MiscRegNum32(15, 0, 0, 8, 7), MISCREG_RAZ },
227  { MiscRegNum32(15, 0, 0, 9, 0), MISCREG_RAZ },
228  { MiscRegNum32(15, 0, 0, 9, 1), MISCREG_RAZ },
229  { MiscRegNum32(15, 0, 0, 9, 2), MISCREG_RAZ },
230  { MiscRegNum32(15, 0, 0, 9, 3), MISCREG_RAZ },
231  { MiscRegNum32(15, 0, 0, 9, 4), MISCREG_RAZ },
232  { MiscRegNum32(15, 0, 0, 9, 5), MISCREG_RAZ },
233  { MiscRegNum32(15, 0, 0, 9, 6), MISCREG_RAZ },
234  { MiscRegNum32(15, 0, 0, 9, 7), MISCREG_RAZ },
235  { MiscRegNum32(15, 0, 0, 10, 0), MISCREG_RAZ },
236  { MiscRegNum32(15, 0, 0, 10, 1), MISCREG_RAZ },
237  { MiscRegNum32(15, 0, 0, 10, 2), MISCREG_RAZ },
238  { MiscRegNum32(15, 0, 0, 10, 3), MISCREG_RAZ },
239  { MiscRegNum32(15, 0, 0, 10, 4), MISCREG_RAZ },
240  { MiscRegNum32(15, 0, 0, 10, 5), MISCREG_RAZ },
241  { MiscRegNum32(15, 0, 0, 10, 6), MISCREG_RAZ },
242  { MiscRegNum32(15, 0, 0, 10, 7), MISCREG_RAZ },
243  { MiscRegNum32(15, 0, 0, 11, 0), MISCREG_RAZ },
244  { MiscRegNum32(15, 0, 0, 11, 1), MISCREG_RAZ },
245  { MiscRegNum32(15, 0, 0, 11, 2), MISCREG_RAZ },
246  { MiscRegNum32(15, 0, 0, 11, 3), MISCREG_RAZ },
247  { MiscRegNum32(15, 0, 0, 11, 4), MISCREG_RAZ },
248  { MiscRegNum32(15, 0, 0, 11, 5), MISCREG_RAZ },
249  { MiscRegNum32(15, 0, 0, 11, 6), MISCREG_RAZ },
250  { MiscRegNum32(15, 0, 0, 11, 7), MISCREG_RAZ },
251  { MiscRegNum32(15, 0, 0, 12, 0), MISCREG_RAZ },
252  { MiscRegNum32(15, 0, 0, 12, 1), MISCREG_RAZ },
253  { MiscRegNum32(15, 0, 0, 12, 2), MISCREG_RAZ },
254  { MiscRegNum32(15, 0, 0, 12, 3), MISCREG_RAZ },
255  { MiscRegNum32(15, 0, 0, 12, 4), MISCREG_RAZ },
256  { MiscRegNum32(15, 0, 0, 12, 5), MISCREG_RAZ },
257  { MiscRegNum32(15, 0, 0, 12, 6), MISCREG_RAZ },
258  { MiscRegNum32(15, 0, 0, 12, 7), MISCREG_RAZ },
259  { MiscRegNum32(15, 0, 0, 13, 0), MISCREG_RAZ },
260  { MiscRegNum32(15, 0, 0, 13, 1), MISCREG_RAZ },
261  { MiscRegNum32(15, 0, 0, 13, 2), MISCREG_RAZ },
262  { MiscRegNum32(15, 0, 0, 13, 3), MISCREG_RAZ },
263  { MiscRegNum32(15, 0, 0, 13, 4), MISCREG_RAZ },
264  { MiscRegNum32(15, 0, 0, 13, 5), MISCREG_RAZ },
265  { MiscRegNum32(15, 0, 0, 13, 6), MISCREG_RAZ },
266  { MiscRegNum32(15, 0, 0, 13, 7), MISCREG_RAZ },
267  { MiscRegNum32(15, 0, 0, 14, 0), MISCREG_RAZ },
268  { MiscRegNum32(15, 0, 0, 14, 1), MISCREG_RAZ },
269  { MiscRegNum32(15, 0, 0, 14, 2), MISCREG_RAZ },
270  { MiscRegNum32(15, 0, 0, 14, 3), MISCREG_RAZ },
271  { MiscRegNum32(15, 0, 0, 14, 4), MISCREG_RAZ },
272  { MiscRegNum32(15, 0, 0, 14, 5), MISCREG_RAZ },
273  { MiscRegNum32(15, 0, 0, 14, 6), MISCREG_RAZ },
274  { MiscRegNum32(15, 0, 0, 14, 7), MISCREG_RAZ },
275  { MiscRegNum32(15, 0, 0, 15, 0), MISCREG_RAZ },
276  { MiscRegNum32(15, 0, 0, 15, 1), MISCREG_RAZ },
277  { MiscRegNum32(15, 0, 0, 15, 2), MISCREG_RAZ },
278  { MiscRegNum32(15, 0, 0, 15, 3), MISCREG_RAZ },
279  { MiscRegNum32(15, 0, 0, 15, 4), MISCREG_RAZ },
280  { MiscRegNum32(15, 0, 0, 15, 5), MISCREG_RAZ },
281  { MiscRegNum32(15, 0, 0, 15, 6), MISCREG_RAZ },
282  { MiscRegNum32(15, 0, 0, 15, 7), MISCREG_RAZ },
283  { MiscRegNum32(15, 0, 1, 0, 0), MISCREG_SCTLR },
284  { MiscRegNum32(15, 0, 1, 0, 1), MISCREG_ACTLR },
285  { MiscRegNum32(15, 0, 1, 0, 2), MISCREG_CPACR },
286  { MiscRegNum32(15, 0, 1, 1, 0), MISCREG_SCR },
287  { MiscRegNum32(15, 0, 1, 1, 1), MISCREG_SDER },
288  { MiscRegNum32(15, 0, 1, 1, 2), MISCREG_NSACR },
289  { MiscRegNum32(15, 0, 1, 3, 1), MISCREG_SDCR },
290  { MiscRegNum32(15, 0, 2, 0, 0), MISCREG_TTBR0 },
291  { MiscRegNum32(15, 0, 2, 0, 1), MISCREG_TTBR1 },
292  { MiscRegNum32(15, 0, 2, 0, 2), MISCREG_TTBCR },
293  { MiscRegNum32(15, 0, 3, 0, 0), MISCREG_DACR },
294  { MiscRegNum32(15, 0, 4, 6, 0), MISCREG_ICC_PMR },
295  { MiscRegNum32(15, 0, 5, 0, 0), MISCREG_DFSR },
296  { MiscRegNum32(15, 0, 5, 0, 1), MISCREG_IFSR },
297  { MiscRegNum32(15, 0, 5, 1, 0), MISCREG_ADFSR },
298  { MiscRegNum32(15, 0, 5, 1, 1), MISCREG_AIFSR },
299  { MiscRegNum32(15, 0, 6, 0, 0), MISCREG_DFAR },
300  { MiscRegNum32(15, 0, 6, 0, 2), MISCREG_IFAR },
301  { MiscRegNum32(15, 0, 7, 0, 4), MISCREG_NOP },
302  { MiscRegNum32(15, 0, 7, 1, 0), MISCREG_ICIALLUIS },
303  { MiscRegNum32(15, 0, 7, 1, 6), MISCREG_BPIALLIS },
304  { MiscRegNum32(15, 0, 7, 2, 7), MISCREG_DBGDEVID0 },
305  { MiscRegNum32(15, 0, 7, 4, 0), MISCREG_PAR },
306  { MiscRegNum32(15, 0, 7, 5, 0), MISCREG_ICIALLU },
307  { MiscRegNum32(15, 0, 7, 5, 1), MISCREG_ICIMVAU },
308  { MiscRegNum32(15, 0, 7, 5, 4), MISCREG_CP15ISB },
309  { MiscRegNum32(15, 0, 7, 5, 6), MISCREG_BPIALL },
310  { MiscRegNum32(15, 0, 7, 5, 7), MISCREG_BPIMVA },
311  { MiscRegNum32(15, 0, 7, 6, 1), MISCREG_DCIMVAC },
312  { MiscRegNum32(15, 0, 7, 6, 2), MISCREG_DCISW },
313  { MiscRegNum32(15, 0, 7, 8, 0), MISCREG_ATS1CPR },
314  { MiscRegNum32(15, 0, 7, 8, 1), MISCREG_ATS1CPW },
315  { MiscRegNum32(15, 0, 7, 8, 2), MISCREG_ATS1CUR },
316  { MiscRegNum32(15, 0, 7, 8, 3), MISCREG_ATS1CUW },
317  { MiscRegNum32(15, 0, 7, 8, 4), MISCREG_ATS12NSOPR },
318  { MiscRegNum32(15, 0, 7, 8, 5), MISCREG_ATS12NSOPW },
319  { MiscRegNum32(15, 0, 7, 8, 6), MISCREG_ATS12NSOUR },
320  { MiscRegNum32(15, 0, 7, 8, 7), MISCREG_ATS12NSOUW },
321  { MiscRegNum32(15, 0, 7, 10, 1), MISCREG_DCCMVAC },
322  { MiscRegNum32(15, 0, 7, 10, 2), MISCREG_DCCSW },
323  { MiscRegNum32(15, 0, 7, 10, 4), MISCREG_CP15DSB },
324  { MiscRegNum32(15, 0, 7, 10, 5), MISCREG_CP15DMB },
325  { MiscRegNum32(15, 0, 7, 11, 1), MISCREG_DCCMVAU },
326  { MiscRegNum32(15, 0, 7, 13, 1), MISCREG_NOP },
327  { MiscRegNum32(15, 0, 7, 14, 1), MISCREG_DCCIMVAC },
328  { MiscRegNum32(15, 0, 7, 14, 2), MISCREG_DCCISW },
329  { MiscRegNum32(15, 0, 8, 3, 0), MISCREG_TLBIALLIS },
330  { MiscRegNum32(15, 0, 8, 3, 1), MISCREG_TLBIMVAIS },
331  { MiscRegNum32(15, 0, 8, 3, 2), MISCREG_TLBIASIDIS },
332  { MiscRegNum32(15, 0, 8, 3, 3), MISCREG_TLBIMVAAIS },
333  { MiscRegNum32(15, 0, 8, 3, 5), MISCREG_TLBIMVALIS },
334  { MiscRegNum32(15, 0, 8, 3, 7), MISCREG_TLBIMVAALIS },
335  { MiscRegNum32(15, 0, 8, 5, 0), MISCREG_ITLBIALL },
336  { MiscRegNum32(15, 0, 8, 5, 1), MISCREG_ITLBIMVA },
337  { MiscRegNum32(15, 0, 8, 5, 2), MISCREG_ITLBIASID },
338  { MiscRegNum32(15, 0, 8, 6, 0), MISCREG_DTLBIALL },
339  { MiscRegNum32(15, 0, 8, 6, 1), MISCREG_DTLBIMVA },
340  { MiscRegNum32(15, 0, 8, 6, 2), MISCREG_DTLBIASID },
341  { MiscRegNum32(15, 0, 8, 7, 0), MISCREG_TLBIALL },
342  { MiscRegNum32(15, 0, 8, 7, 1), MISCREG_TLBIMVA },
343  { MiscRegNum32(15, 0, 8, 7, 2), MISCREG_TLBIASID },
344  { MiscRegNum32(15, 0, 8, 7, 3), MISCREG_TLBIMVAA },
345  { MiscRegNum32(15, 0, 8, 7, 5), MISCREG_TLBIMVAL },
346  { MiscRegNum32(15, 0, 8, 7, 7), MISCREG_TLBIMVAAL },
347  { MiscRegNum32(15, 0, 9, 12, 0), MISCREG_PMCR },
348  { MiscRegNum32(15, 0, 9, 12, 1), MISCREG_PMCNTENSET },
349  { MiscRegNum32(15, 0, 9, 12, 2), MISCREG_PMCNTENCLR },
350  { MiscRegNum32(15, 0, 9, 12, 3), MISCREG_PMOVSR },
351  { MiscRegNum32(15, 0, 9, 12, 4), MISCREG_PMSWINC },
352  { MiscRegNum32(15, 0, 9, 12, 5), MISCREG_PMSELR },
353  { MiscRegNum32(15, 0, 9, 12, 6), MISCREG_PMCEID0 },
354  { MiscRegNum32(15, 0, 9, 12, 7), MISCREG_PMCEID1 },
355  { MiscRegNum32(15, 0, 9, 13, 0), MISCREG_PMCCNTR },
356  { MiscRegNum32(15, 0, 9, 13, 1), MISCREG_PMXEVTYPER_PMCCFILTR },
357  { MiscRegNum32(15, 0, 9, 13, 2), MISCREG_PMXEVCNTR },
358  { MiscRegNum32(15, 0, 9, 14, 0), MISCREG_PMUSERENR },
359  { MiscRegNum32(15, 0, 9, 14, 1), MISCREG_PMINTENSET },
360  { MiscRegNum32(15, 0, 9, 14, 2), MISCREG_PMINTENCLR },
361  { MiscRegNum32(15, 0, 9, 14, 3), MISCREG_PMOVSSET },
362  { MiscRegNum32(15, 0, 10, 2, 0), MISCREG_PRRR_MAIR0 },
363  { MiscRegNum32(15, 0, 10, 2, 1), MISCREG_NMRR_MAIR1 },
364  { MiscRegNum32(15, 0, 10, 3, 0), MISCREG_AMAIR0 },
365  { MiscRegNum32(15, 0, 10, 3, 1), MISCREG_AMAIR1 },
366  { MiscRegNum32(15, 0, 12, 0, 0), MISCREG_VBAR },
367  { MiscRegNum32(15, 0, 12, 0, 1), MISCREG_MVBAR },
368  { MiscRegNum32(15, 0, 12, 1, 0), MISCREG_ISR },
369  { MiscRegNum32(15, 0, 12, 8, 0), MISCREG_ICC_IAR0 },
370  { MiscRegNum32(15, 0, 12, 8, 1), MISCREG_ICC_EOIR0 },
371  { MiscRegNum32(15, 0, 12, 8, 2), MISCREG_ICC_HPPIR0 },
372  { MiscRegNum32(15, 0, 12, 8, 3), MISCREG_ICC_BPR0 },
373  { MiscRegNum32(15, 0, 12, 8, 4), MISCREG_ICC_AP0R0 },
374  { MiscRegNum32(15, 0, 12, 8, 5), MISCREG_ICC_AP0R1 },
375  { MiscRegNum32(15, 0, 12, 8, 6), MISCREG_ICC_AP0R2 },
376  { MiscRegNum32(15, 0, 12, 8, 7), MISCREG_ICC_AP0R3 },
377  { MiscRegNum32(15, 0, 12, 9, 0), MISCREG_ICC_AP1R0 },
378  { MiscRegNum32(15, 0, 12, 9, 1), MISCREG_ICC_AP1R1 },
379  { MiscRegNum32(15, 0, 12, 9, 2), MISCREG_ICC_AP1R2 },
380  { MiscRegNum32(15, 0, 12, 9, 3), MISCREG_ICC_AP1R3 },
381  { MiscRegNum32(15, 0, 12, 11, 1), MISCREG_ICC_DIR },
382  { MiscRegNum32(15, 0, 12, 11, 3), MISCREG_ICC_RPR },
383  { MiscRegNum32(15, 0, 12, 12, 0), MISCREG_ICC_IAR1 },
384  { MiscRegNum32(15, 0, 12, 12, 1), MISCREG_ICC_EOIR1 },
385  { MiscRegNum32(15, 0, 12, 12, 2), MISCREG_ICC_HPPIR1 },
386  { MiscRegNum32(15, 0, 12, 12, 3), MISCREG_ICC_BPR1 },
387  { MiscRegNum32(15, 0, 12, 12, 4), MISCREG_ICC_CTLR },
388  { MiscRegNum32(15, 0, 12, 12, 5), MISCREG_ICC_SRE },
389  { MiscRegNum32(15, 0, 12, 12, 6), MISCREG_ICC_IGRPEN0 },
390  { MiscRegNum32(15, 0, 12, 12, 7), MISCREG_ICC_IGRPEN1 },
391  { MiscRegNum32(15, 0, 13, 0, 0), MISCREG_FCSEIDR },
392  { MiscRegNum32(15, 0, 13, 0, 1), MISCREG_CONTEXTIDR },
393  { MiscRegNum32(15, 0, 13, 0, 2), MISCREG_TPIDRURW },
394  { MiscRegNum32(15, 0, 13, 0, 3), MISCREG_TPIDRURO },
395  { MiscRegNum32(15, 0, 13, 0, 4), MISCREG_TPIDRPRW },
396  { MiscRegNum32(15, 0, 14, 0, 0), MISCREG_CNTFRQ },
397  { MiscRegNum32(15, 0, 14, 1, 0), MISCREG_CNTKCTL },
398  { MiscRegNum32(15, 0, 14, 2, 0), MISCREG_CNTP_TVAL },
399  { MiscRegNum32(15, 0, 14, 2, 1), MISCREG_CNTP_CTL },
400  { MiscRegNum32(15, 0, 14, 3, 0), MISCREG_CNTV_TVAL },
401  { MiscRegNum32(15, 0, 14, 3, 1), MISCREG_CNTV_CTL },
402  { MiscRegNum32(15, 1, 0, 0, 0), MISCREG_CCSIDR },
403  { MiscRegNum32(15, 1, 0, 0, 1), MISCREG_CLIDR },
404  { MiscRegNum32(15, 1, 0, 0, 7), MISCREG_AIDR },
405  { MiscRegNum32(15, 2, 0, 0, 0), MISCREG_CSSELR },
406  { MiscRegNum32(15, 4, 0, 0, 0), MISCREG_VPIDR },
407  { MiscRegNum32(15, 4, 0, 0, 5), MISCREG_VMPIDR },
408  { MiscRegNum32(15, 4, 1, 0, 0), MISCREG_HSCTLR },
409  { MiscRegNum32(15, 4, 1, 0, 1), MISCREG_HACTLR },
410  { MiscRegNum32(15, 4, 1, 1, 0), MISCREG_HCR },
411  { MiscRegNum32(15, 4, 1, 1, 1), MISCREG_HDCR },
412  { MiscRegNum32(15, 4, 1, 1, 2), MISCREG_HCPTR },
413  { MiscRegNum32(15, 4, 1, 1, 3), MISCREG_HSTR },
414  { MiscRegNum32(15, 4, 1, 1, 4), MISCREG_HCR2 },
415  { MiscRegNum32(15, 4, 1, 1, 7), MISCREG_HACR },
416  { MiscRegNum32(15, 4, 2, 0, 2), MISCREG_HTCR },
417  { MiscRegNum32(15, 4, 2, 1, 2), MISCREG_VTCR },
418  { MiscRegNum32(15, 4, 5, 1, 0), MISCREG_HADFSR },
419  { MiscRegNum32(15, 4, 5, 1, 1), MISCREG_HAIFSR },
420  { MiscRegNum32(15, 4, 5, 2, 0), MISCREG_HSR },
421  { MiscRegNum32(15, 4, 6, 0, 0), MISCREG_HDFAR },
422  { MiscRegNum32(15, 4, 6, 0, 2), MISCREG_HIFAR },
423  { MiscRegNum32(15, 4, 6, 0, 4), MISCREG_HPFAR },
424  { MiscRegNum32(15, 4, 7, 8, 0), MISCREG_ATS1HR },
425  { MiscRegNum32(15, 4, 7, 8, 1), MISCREG_ATS1HW },
426  { MiscRegNum32(15, 4, 8, 0, 1), MISCREG_TLBIIPAS2IS },
427  { MiscRegNum32(15, 4, 8, 0, 5), MISCREG_TLBIIPAS2LIS },
428  { MiscRegNum32(15, 4, 8, 3, 0), MISCREG_TLBIALLHIS },
429  { MiscRegNum32(15, 4, 8, 3, 1), MISCREG_TLBIMVAHIS },
430  { MiscRegNum32(15, 4, 8, 3, 4), MISCREG_TLBIALLNSNHIS },
431  { MiscRegNum32(15, 4, 8, 3, 5), MISCREG_TLBIMVALHIS },
432  { MiscRegNum32(15, 4, 8, 4, 1), MISCREG_TLBIIPAS2 },
433  { MiscRegNum32(15, 4, 8, 4, 5), MISCREG_TLBIIPAS2L },
434  { MiscRegNum32(15, 4, 8, 7, 0), MISCREG_TLBIALLH },
435  { MiscRegNum32(15, 4, 8, 7, 1), MISCREG_TLBIMVAH },
436  { MiscRegNum32(15, 4, 8, 7, 4), MISCREG_TLBIALLNSNH },
437  { MiscRegNum32(15, 4, 8, 7, 5), MISCREG_TLBIMVALH },
438  { MiscRegNum32(15, 4, 10, 2, 0), MISCREG_HMAIR0 },
439  { MiscRegNum32(15, 4, 10, 2, 1), MISCREG_HMAIR1 },
440  { MiscRegNum32(15, 4, 10, 3, 0), MISCREG_HAMAIR0 },
441  { MiscRegNum32(15, 4, 10, 3, 1), MISCREG_HAMAIR1 },
442  { MiscRegNum32(15, 4, 12, 0, 0), MISCREG_HVBAR },
443  { MiscRegNum32(15, 4, 12, 8, 0), MISCREG_ICH_AP0R0 },
444  { MiscRegNum32(15, 4, 12, 8, 1), MISCREG_ICH_AP0R1 },
445  { MiscRegNum32(15, 4, 12, 8, 2), MISCREG_ICH_AP0R2 },
446  { MiscRegNum32(15, 4, 12, 8, 3), MISCREG_ICH_AP0R3 },
447  { MiscRegNum32(15, 4, 12, 9, 0), MISCREG_ICH_AP1R0 },
448  { MiscRegNum32(15, 4, 12, 9, 1), MISCREG_ICH_AP1R1 },
449  { MiscRegNum32(15, 4, 12, 9, 2), MISCREG_ICH_AP1R2 },
450  { MiscRegNum32(15, 4, 12, 9, 3), MISCREG_ICH_AP1R3 },
451  { MiscRegNum32(15, 4, 12, 9, 5), MISCREG_ICC_HSRE },
452  { MiscRegNum32(15, 4, 12, 11, 0), MISCREG_ICH_HCR },
453  { MiscRegNum32(15, 4, 12, 11, 1), MISCREG_ICH_VTR },
454  { MiscRegNum32(15, 4, 12, 11, 2), MISCREG_ICH_MISR },
455  { MiscRegNum32(15, 4, 12, 11, 3), MISCREG_ICH_EISR },
456  { MiscRegNum32(15, 4, 12, 11, 5), MISCREG_ICH_ELRSR },
457  { MiscRegNum32(15, 4, 12, 11, 7), MISCREG_ICH_VMCR },
458  { MiscRegNum32(15, 4, 12, 12, 0), MISCREG_ICH_LR0 },
459  { MiscRegNum32(15, 4, 12, 12, 1), MISCREG_ICH_LR1 },
460  { MiscRegNum32(15, 4, 12, 12, 2), MISCREG_ICH_LR2 },
461  { MiscRegNum32(15, 4, 12, 12, 3), MISCREG_ICH_LR3 },
462  { MiscRegNum32(15, 4, 12, 12, 4), MISCREG_ICH_LR4 },
463  { MiscRegNum32(15, 4, 12, 12, 5), MISCREG_ICH_LR5 },
464  { MiscRegNum32(15, 4, 12, 12, 6), MISCREG_ICH_LR6 },
465  { MiscRegNum32(15, 4, 12, 12, 7), MISCREG_ICH_LR7 },
466  { MiscRegNum32(15, 4, 12, 13, 0), MISCREG_ICH_LR8 },
467  { MiscRegNum32(15, 4, 12, 13, 1), MISCREG_ICH_LR9 },
468  { MiscRegNum32(15, 4, 12, 13, 2), MISCREG_ICH_LR10 },
469  { MiscRegNum32(15, 4, 12, 13, 3), MISCREG_ICH_LR11 },
470  { MiscRegNum32(15, 4, 12, 13, 4), MISCREG_ICH_LR12 },
471  { MiscRegNum32(15, 4, 12, 13, 5), MISCREG_ICH_LR13 },
472  { MiscRegNum32(15, 4, 12, 13, 6), MISCREG_ICH_LR14 },
473  { MiscRegNum32(15, 4, 12, 13, 7), MISCREG_ICH_LR15 },
474  { MiscRegNum32(15, 4, 12, 14, 0), MISCREG_ICH_LRC0 },
475  { MiscRegNum32(15, 4, 12, 14, 1), MISCREG_ICH_LRC1 },
476  { MiscRegNum32(15, 4, 12, 14, 2), MISCREG_ICH_LRC2 },
477  { MiscRegNum32(15, 4, 12, 14, 3), MISCREG_ICH_LRC3 },
478  { MiscRegNum32(15, 4, 12, 14, 4), MISCREG_ICH_LRC4 },
479  { MiscRegNum32(15, 4, 12, 14, 5), MISCREG_ICH_LRC5 },
480  { MiscRegNum32(15, 4, 12, 14, 6), MISCREG_ICH_LRC6 },
481  { MiscRegNum32(15, 4, 12, 14, 7), MISCREG_ICH_LRC7 },
482  { MiscRegNum32(15, 4, 12, 15, 0), MISCREG_ICH_LRC8 },
483  { MiscRegNum32(15, 4, 12, 15, 1), MISCREG_ICH_LRC9 },
484  { MiscRegNum32(15, 4, 12, 15, 2), MISCREG_ICH_LRC10 },
485  { MiscRegNum32(15, 4, 12, 15, 3), MISCREG_ICH_LRC11 },
486  { MiscRegNum32(15, 4, 12, 15, 4), MISCREG_ICH_LRC12 },
487  { MiscRegNum32(15, 4, 12, 15, 5), MISCREG_ICH_LRC13 },
488  { MiscRegNum32(15, 4, 12, 15, 6), MISCREG_ICH_LRC14 },
489  { MiscRegNum32(15, 4, 12, 15, 7), MISCREG_ICH_LRC15 },
490  { MiscRegNum32(15, 4, 13, 0, 2), MISCREG_HTPIDR },
491  { MiscRegNum32(15, 4, 14, 1, 0), MISCREG_CNTHCTL },
492  { MiscRegNum32(15, 4, 14, 2, 0), MISCREG_CNTHP_TVAL },
493  { MiscRegNum32(15, 4, 14, 2, 1), MISCREG_CNTHP_CTL },
494  { MiscRegNum32(15, 6, 12, 12, 4), MISCREG_ICC_MCTLR },
495  { MiscRegNum32(15, 6, 12, 12, 5), MISCREG_ICC_MSRE },
496  { MiscRegNum32(15, 6, 12, 12, 7), MISCREG_ICC_MGRPEN1 },
497  // MCRR/MRRC regs
498  { MiscRegNum32(15, 0, 2), MISCREG_TTBR0 },
499  { MiscRegNum32(15, 0, 7), MISCREG_PAR },
500  { MiscRegNum32(15, 0, 12), MISCREG_ICC_SGI1R },
501  { MiscRegNum32(15, 0, 14), MISCREG_CNTPCT },
502  { MiscRegNum32(15, 0, 15), MISCREG_CPUMERRSR },
503  { MiscRegNum32(15, 1, 2), MISCREG_TTBR1 },
504  { MiscRegNum32(15, 1, 12), MISCREG_ICC_ASGI1R },
505  { MiscRegNum32(15, 1, 14), MISCREG_CNTVCT },
506  { MiscRegNum32(15, 1, 15), MISCREG_L2MERRSR },
507  { MiscRegNum32(15, 2, 12), MISCREG_ICC_SGI0R },
508  { MiscRegNum32(15, 2, 14), MISCREG_CNTP_CVAL },
509  { MiscRegNum32(15, 3, 14), MISCREG_CNTV_CVAL },
510  { MiscRegNum32(15, 4, 2), MISCREG_HTTBR },
511  { MiscRegNum32(15, 4, 14), MISCREG_CNTVOFF },
512  { MiscRegNum32(15, 6, 2), MISCREG_VTTBR },
513  { MiscRegNum32(15, 6, 14), MISCREG_CNTHP_CVAL },
514 };
515 
516 }
517 
519 decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
520 {
521  MiscRegNum32 cop_reg(14, opc1, crn, crm, opc2);
522  auto it = miscRegNum32ToIdx.find(cop_reg);
523  if (it != miscRegNum32ToIdx.end()) {
524  return it->second;
525  } else {
526  warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
527  crn, opc1, crm, opc2);
528  return MISCREG_UNKNOWN;
529  }
530 }
531 
533 decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
534 {
535  MiscRegNum32 cop_reg(15, opc1, crn, crm, opc2);
536  auto it = miscRegNum32ToIdx.find(cop_reg);
537  if (it != miscRegNum32ToIdx.end()) {
538  return it->second;
539  } else {
540  if ((crn == 15) ||
541  (crn == 9 && (crm <= 2 || crm >= 5)) ||
542  (crn == 10 && opc1 == 0 && crm <= 1) ||
543  (crn == 11 && opc1 <= 7 && (crm <= 8 || crm ==15))) {
544  return MISCREG_IMPDEF_UNIMPL;
545  } else {
546  return MISCREG_UNKNOWN;
547  }
548  }
549 }
550 
552 decodeCP15Reg64(unsigned crm, unsigned opc1)
553 {
554  MiscRegNum32 cop_reg(15, opc1, crm);
555  auto it = miscRegNum32ToIdx.find(cop_reg);
556  if (it != miscRegNum32ToIdx.end()) {
557  return it->second;
558  } else {
559  return MISCREG_UNKNOWN;
560  }
561 }
562 
563 std::tuple<bool, bool>
565 {
566  bool secure = !scr.ns;
567  bool can_read = false;
568  bool undefined = false;
569  auto& miscreg_info = lookUpMiscReg[reg].info;
570 
571  switch (cpsr.mode) {
572  case MODE_USER:
573  can_read = secure ? miscreg_info[MISCREG_USR_S_RD] :
574  miscreg_info[MISCREG_USR_NS_RD];
575  break;
576  case MODE_FIQ:
577  case MODE_IRQ:
578  case MODE_SVC:
579  case MODE_ABORT:
580  case MODE_UNDEFINED:
581  case MODE_SYSTEM:
582  can_read = secure ? miscreg_info[MISCREG_PRI_S_RD] :
583  miscreg_info[MISCREG_PRI_NS_RD];
584  break;
585  case MODE_MON:
586  can_read = secure ? miscreg_info[MISCREG_MON_NS0_RD] :
587  miscreg_info[MISCREG_MON_NS1_RD];
588  break;
589  case MODE_HYP:
590  can_read = miscreg_info[MISCREG_HYP_NS_RD];
591  break;
592  default:
593  undefined = true;
594  }
595 
596  switch (reg) {
598  if (!undefined)
599  undefined = AArch32isUndefinedGenericTimer(reg, tc);
600  break;
601  default:
602  break;
603  }
604 
605  // can't do permissions checkes on the root of a banked pair of regs
606  assert(!miscreg_info[MISCREG_BANKED]);
607  return std::make_tuple(can_read, undefined);
608 }
609 
610 std::tuple<bool, bool>
612 {
613  bool secure = !scr.ns;
614  bool can_write = false;
615  bool undefined = false;
616  const auto& miscreg_info = lookUpMiscReg[reg].info;
617 
618  switch (cpsr.mode) {
619  case MODE_USER:
620  can_write = secure ? miscreg_info[MISCREG_USR_S_WR] :
621  miscreg_info[MISCREG_USR_NS_WR];
622  break;
623  case MODE_FIQ:
624  case MODE_IRQ:
625  case MODE_SVC:
626  case MODE_ABORT:
627  case MODE_UNDEFINED:
628  case MODE_SYSTEM:
629  can_write = secure ? miscreg_info[MISCREG_PRI_S_WR] :
630  miscreg_info[MISCREG_PRI_NS_WR];
631  break;
632  case MODE_MON:
633  can_write = secure ? miscreg_info[MISCREG_MON_NS0_WR] :
634  miscreg_info[MISCREG_MON_NS1_WR];
635  break;
636  case MODE_HYP:
637  can_write = miscreg_info[MISCREG_HYP_NS_WR];
638  break;
639  default:
640  undefined = true;
641  }
642 
643  switch (reg) {
645  if (!undefined)
646  undefined = AArch32isUndefinedGenericTimer(reg, tc);
647  break;
648  default:
649  break;
650  }
651 
652  // can't do permissions checkes on the root of a banked pair of regs
653  assert(!miscreg_info[MISCREG_BANKED]);
654  return std::make_tuple(can_write, undefined);
655 }
656 
657 bool
659 {
660  if (currEL(tc) == EL0 && ELIs32(tc, EL1)) {
661  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
662  bool trap_cond = condGenericTimerSystemAccessTrapEL1(reg, tc);
663  if (trap_cond && (!EL2Enabled(tc) || !hcr.tge))
664  return true;
665  }
666  return false;
667 }
668 
669 int
671 {
672  SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
673  return snsBankedIndex(reg, tc, scr.ns);
674 }
675 
676 int
678 {
679  int reg_as_int = static_cast<int>(reg);
680  if (lookUpMiscReg[reg].info[MISCREG_BANKED]) {
681  reg_as_int += (ArmSystem::haveEL(tc, EL3) &&
682  !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
683  }
684  return reg_as_int;
685 }
686 
687 int
689 {
690  auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
691  SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
692  return isa->snsBankedIndex64(reg, scr.ns);
693 }
694 
704 
705 void
707 {
708  int reg = -1;
709  for (int i = 0 ; i < NUM_MISCREGS; i++){
710  if (lookUpMiscReg[i].info[MISCREG_BANKED])
711  reg = i;
714  else
716  // if this assert fails, no parent was found, and something is broken
717  assert(unflattenResultMiscReg[i] > -1);
718  }
719 }
720 
721 int
723 {
724  return unflattenResultMiscReg[reg];
725 }
726 
727 Fault
729  ThreadContext *tc, const MiscRegOp64 &inst)
730 {
731  return lookUpMiscReg[reg].checkFault(tc, inst, currEL(cpsr));
732 }
733 
735 
736 namespace {
737 
738 // The map is translating a MiscRegIndex into AArch64 system register
739 // numbers (op0, op1, crn, crm, op2)
740 std::unordered_map<MiscRegIndex, MiscRegNum64> idxToMiscRegNum;
741 
742 // The map is translating AArch64 system register numbers
743 // (op0, op1, crn, crm, op2) into a MiscRegIndex
744 std::unordered_map<MiscRegNum64, MiscRegIndex> miscRegNumToIdx{
745  { MiscRegNum64(1, 0, 7, 1, 0), MISCREG_IC_IALLUIS },
746  { MiscRegNum64(1, 0, 7, 5, 0), MISCREG_IC_IALLU },
747  { MiscRegNum64(1, 0, 7, 6, 1), MISCREG_DC_IVAC_Xt },
748  { MiscRegNum64(1, 0, 7, 6, 2), MISCREG_DC_ISW_Xt },
749  { MiscRegNum64(1, 0, 7, 8, 0), MISCREG_AT_S1E1R_Xt },
750  { MiscRegNum64(1, 0, 7, 8, 1), MISCREG_AT_S1E1W_Xt },
751  { MiscRegNum64(1, 0, 7, 8, 2), MISCREG_AT_S1E0R_Xt },
752  { MiscRegNum64(1, 0, 7, 8, 3), MISCREG_AT_S1E0W_Xt },
753  { MiscRegNum64(1, 0, 7, 10, 2), MISCREG_DC_CSW_Xt },
754  { MiscRegNum64(1, 0, 7, 14, 2), MISCREG_DC_CISW_Xt },
755  { MiscRegNum64(1, 0, 8, 3, 0), MISCREG_TLBI_VMALLE1IS },
756  { MiscRegNum64(1, 0, 8, 3, 1), MISCREG_TLBI_VAE1IS_Xt },
757  { MiscRegNum64(1, 0, 8, 3, 2), MISCREG_TLBI_ASIDE1IS_Xt },
758  { MiscRegNum64(1, 0, 8, 3, 3), MISCREG_TLBI_VAAE1IS_Xt },
759  { MiscRegNum64(1, 0, 8, 3, 5), MISCREG_TLBI_VALE1IS_Xt },
760  { MiscRegNum64(1, 0, 8, 3, 7), MISCREG_TLBI_VAALE1IS_Xt },
761  { MiscRegNum64(1, 0, 8, 7, 0), MISCREG_TLBI_VMALLE1 },
762  { MiscRegNum64(1, 0, 8, 7, 1), MISCREG_TLBI_VAE1_Xt },
763  { MiscRegNum64(1, 0, 8, 7, 2), MISCREG_TLBI_ASIDE1_Xt },
764  { MiscRegNum64(1, 0, 8, 7, 3), MISCREG_TLBI_VAAE1_Xt },
765  { MiscRegNum64(1, 0, 8, 7, 5), MISCREG_TLBI_VALE1_Xt },
766  { MiscRegNum64(1, 0, 8, 7, 7), MISCREG_TLBI_VAALE1_Xt },
767  { MiscRegNum64(1, 3, 7, 4, 1), MISCREG_DC_ZVA_Xt },
768  { MiscRegNum64(1, 3, 7, 5, 1), MISCREG_IC_IVAU_Xt },
769  { MiscRegNum64(1, 3, 7, 10, 1), MISCREG_DC_CVAC_Xt },
770  { MiscRegNum64(1, 3, 7, 11, 1), MISCREG_DC_CVAU_Xt },
771  { MiscRegNum64(1, 3, 7, 14, 1), MISCREG_DC_CIVAC_Xt },
772  { MiscRegNum64(1, 4, 7, 8, 0), MISCREG_AT_S1E2R_Xt },
773  { MiscRegNum64(1, 4, 7, 8, 1), MISCREG_AT_S1E2W_Xt },
774  { MiscRegNum64(1, 4, 7, 8, 4), MISCREG_AT_S12E1R_Xt },
775  { MiscRegNum64(1, 4, 7, 8, 5), MISCREG_AT_S12E1W_Xt },
776  { MiscRegNum64(1, 4, 7, 8, 6), MISCREG_AT_S12E0R_Xt },
777  { MiscRegNum64(1, 4, 7, 8, 7), MISCREG_AT_S12E0W_Xt },
778  { MiscRegNum64(1, 4, 8, 0, 1), MISCREG_TLBI_IPAS2E1IS_Xt },
779  { MiscRegNum64(1, 4, 8, 0, 5), MISCREG_TLBI_IPAS2LE1IS_Xt },
780  { MiscRegNum64(1, 4, 8, 3, 0), MISCREG_TLBI_ALLE2IS },
781  { MiscRegNum64(1, 4, 8, 3, 1), MISCREG_TLBI_VAE2IS_Xt },
782  { MiscRegNum64(1, 4, 8, 3, 4), MISCREG_TLBI_ALLE1IS },
783  { MiscRegNum64(1, 4, 8, 3, 5), MISCREG_TLBI_VALE2IS_Xt },
784  { MiscRegNum64(1, 4, 8, 3, 6), MISCREG_TLBI_VMALLS12E1IS },
785  { MiscRegNum64(1, 4, 8, 4, 1), MISCREG_TLBI_IPAS2E1_Xt },
786  { MiscRegNum64(1, 4, 8, 4, 5), MISCREG_TLBI_IPAS2LE1_Xt },
787  { MiscRegNum64(1, 4, 8, 7, 0), MISCREG_TLBI_ALLE2 },
788  { MiscRegNum64(1, 4, 8, 7, 1), MISCREG_TLBI_VAE2_Xt },
789  { MiscRegNum64(1, 4, 8, 7, 4), MISCREG_TLBI_ALLE1 },
790  { MiscRegNum64(1, 4, 8, 7, 5), MISCREG_TLBI_VALE2_Xt },
791  { MiscRegNum64(1, 4, 8, 7, 6), MISCREG_TLBI_VMALLS12E1 },
792  { MiscRegNum64(1, 6, 7, 8, 0), MISCREG_AT_S1E3R_Xt },
793  { MiscRegNum64(1, 6, 7, 8, 1), MISCREG_AT_S1E3W_Xt },
794  { MiscRegNum64(1, 6, 8, 3, 0), MISCREG_TLBI_ALLE3IS },
795  { MiscRegNum64(1, 6, 8, 3, 1), MISCREG_TLBI_VAE3IS_Xt },
796  { MiscRegNum64(1, 6, 8, 3, 5), MISCREG_TLBI_VALE3IS_Xt },
797  { MiscRegNum64(1, 6, 8, 7, 0), MISCREG_TLBI_ALLE3 },
798  { MiscRegNum64(1, 6, 8, 7, 1), MISCREG_TLBI_VAE3_Xt },
799  { MiscRegNum64(1, 6, 8, 7, 5), MISCREG_TLBI_VALE3_Xt },
800  { MiscRegNum64(2, 0, 0, 0, 2), MISCREG_OSDTRRX_EL1 },
801  { MiscRegNum64(2, 0, 0, 0, 4), MISCREG_DBGBVR0_EL1 },
802  { MiscRegNum64(2, 0, 0, 0, 5), MISCREG_DBGBCR0_EL1 },
803  { MiscRegNum64(2, 0, 0, 0, 6), MISCREG_DBGWVR0_EL1 },
804  { MiscRegNum64(2, 0, 0, 0, 7), MISCREG_DBGWCR0_EL1 },
805  { MiscRegNum64(2, 0, 0, 1, 4), MISCREG_DBGBVR1_EL1 },
806  { MiscRegNum64(2, 0, 0, 1, 5), MISCREG_DBGBCR1_EL1 },
807  { MiscRegNum64(2, 0, 0, 1, 6), MISCREG_DBGWVR1_EL1 },
808  { MiscRegNum64(2, 0, 0, 1, 7), MISCREG_DBGWCR1_EL1 },
809  { MiscRegNum64(2, 0, 0, 2, 0), MISCREG_MDCCINT_EL1 },
810  { MiscRegNum64(2, 0, 0, 2, 2), MISCREG_MDSCR_EL1 },
811  { MiscRegNum64(2, 0, 0, 2, 4), MISCREG_DBGBVR2_EL1 },
812  { MiscRegNum64(2, 0, 0, 2, 5), MISCREG_DBGBCR2_EL1 },
813  { MiscRegNum64(2, 0, 0, 2, 6), MISCREG_DBGWVR2_EL1 },
814  { MiscRegNum64(2, 0, 0, 2, 7), MISCREG_DBGWCR2_EL1 },
815  { MiscRegNum64(2, 0, 0, 3, 2), MISCREG_OSDTRTX_EL1 },
816  { MiscRegNum64(2, 0, 0, 3, 4), MISCREG_DBGBVR3_EL1 },
817  { MiscRegNum64(2, 0, 0, 3, 5), MISCREG_DBGBCR3_EL1 },
818  { MiscRegNum64(2, 0, 0, 3, 6), MISCREG_DBGWVR3_EL1 },
819  { MiscRegNum64(2, 0, 0, 3, 7), MISCREG_DBGWCR3_EL1 },
820  { MiscRegNum64(2, 0, 0, 4, 4), MISCREG_DBGBVR4_EL1 },
821  { MiscRegNum64(2, 0, 0, 4, 5), MISCREG_DBGBCR4_EL1 },
822  { MiscRegNum64(2, 0, 0, 4, 6), MISCREG_DBGWVR4_EL1 },
823  { MiscRegNum64(2, 0, 0, 4, 7), MISCREG_DBGWCR4_EL1 },
824  { MiscRegNum64(2, 0, 0, 5, 4), MISCREG_DBGBVR5_EL1 },
825  { MiscRegNum64(2, 0, 0, 5, 5), MISCREG_DBGBCR5_EL1 },
826  { MiscRegNum64(2, 0, 0, 5, 6), MISCREG_DBGWVR5_EL1 },
827  { MiscRegNum64(2, 0, 0, 5, 7), MISCREG_DBGWCR5_EL1 },
828  { MiscRegNum64(2, 0, 0, 6, 2), MISCREG_OSECCR_EL1 },
829  { MiscRegNum64(2, 0, 0, 6, 4), MISCREG_DBGBVR6_EL1 },
830  { MiscRegNum64(2, 0, 0, 6, 5), MISCREG_DBGBCR6_EL1 },
831  { MiscRegNum64(2, 0, 0, 6, 6), MISCREG_DBGWVR6_EL1 },
832  { MiscRegNum64(2, 0, 0, 6, 7), MISCREG_DBGWCR6_EL1 },
833  { MiscRegNum64(2, 0, 0, 7, 4), MISCREG_DBGBVR7_EL1 },
834  { MiscRegNum64(2, 0, 0, 7, 5), MISCREG_DBGBCR7_EL1 },
835  { MiscRegNum64(2, 0, 0, 7, 6), MISCREG_DBGWVR7_EL1 },
836  { MiscRegNum64(2, 0, 0, 7, 7), MISCREG_DBGWCR7_EL1 },
837  { MiscRegNum64(2, 0, 0, 8, 4), MISCREG_DBGBVR8_EL1 },
838  { MiscRegNum64(2, 0, 0, 8, 5), MISCREG_DBGBCR8_EL1 },
839  { MiscRegNum64(2, 0, 0, 8, 6), MISCREG_DBGWVR8_EL1 },
840  { MiscRegNum64(2, 0, 0, 8, 7), MISCREG_DBGWCR8_EL1 },
841  { MiscRegNum64(2, 0, 0, 9, 4), MISCREG_DBGBVR9_EL1 },
842  { MiscRegNum64(2, 0, 0, 9, 5), MISCREG_DBGBCR9_EL1 },
843  { MiscRegNum64(2, 0, 0, 9, 6), MISCREG_DBGWVR9_EL1 },
844  { MiscRegNum64(2, 0, 0, 9, 7), MISCREG_DBGWCR9_EL1 },
845  { MiscRegNum64(2, 0, 0, 10, 4), MISCREG_DBGBVR10_EL1 },
846  { MiscRegNum64(2, 0, 0, 10, 5), MISCREG_DBGBCR10_EL1 },
847  { MiscRegNum64(2, 0, 0, 10, 6), MISCREG_DBGWVR10_EL1 },
848  { MiscRegNum64(2, 0, 0, 10, 7), MISCREG_DBGWCR10_EL1 },
849  { MiscRegNum64(2, 0, 0, 11, 4), MISCREG_DBGBVR11_EL1 },
850  { MiscRegNum64(2, 0, 0, 11, 5), MISCREG_DBGBCR11_EL1 },
851  { MiscRegNum64(2, 0, 0, 11, 6), MISCREG_DBGWVR11_EL1 },
852  { MiscRegNum64(2, 0, 0, 11, 7), MISCREG_DBGWCR11_EL1 },
853  { MiscRegNum64(2, 0, 0, 12, 4), MISCREG_DBGBVR12_EL1 },
854  { MiscRegNum64(2, 0, 0, 12, 5), MISCREG_DBGBCR12_EL1 },
855  { MiscRegNum64(2, 0, 0, 12, 6), MISCREG_DBGWVR12_EL1 },
856  { MiscRegNum64(2, 0, 0, 12, 7), MISCREG_DBGWCR12_EL1 },
857  { MiscRegNum64(2, 0, 0, 13, 4), MISCREG_DBGBVR13_EL1 },
858  { MiscRegNum64(2, 0, 0, 13, 5), MISCREG_DBGBCR13_EL1 },
859  { MiscRegNum64(2, 0, 0, 13, 6), MISCREG_DBGWVR13_EL1 },
860  { MiscRegNum64(2, 0, 0, 13, 7), MISCREG_DBGWCR13_EL1 },
861  { MiscRegNum64(2, 0, 0, 14, 4), MISCREG_DBGBVR14_EL1 },
862  { MiscRegNum64(2, 0, 0, 14, 5), MISCREG_DBGBCR14_EL1 },
863  { MiscRegNum64(2, 0, 0, 14, 6), MISCREG_DBGWVR14_EL1 },
864  { MiscRegNum64(2, 0, 0, 14, 7), MISCREG_DBGWCR14_EL1 },
865  { MiscRegNum64(2, 0, 0, 15, 4), MISCREG_DBGBVR15_EL1 },
866  { MiscRegNum64(2, 0, 0, 15, 5), MISCREG_DBGBCR15_EL1 },
867  { MiscRegNum64(2, 0, 0, 15, 6), MISCREG_DBGWVR15_EL1 },
868  { MiscRegNum64(2, 0, 0, 15, 7), MISCREG_DBGWCR15_EL1 },
869  { MiscRegNum64(2, 0, 1, 0, 0), MISCREG_MDRAR_EL1 },
870  { MiscRegNum64(2, 0, 1, 0, 4), MISCREG_OSLAR_EL1 },
871  { MiscRegNum64(2, 0, 1, 1, 4), MISCREG_OSLSR_EL1 },
872  { MiscRegNum64(2, 0, 1, 3, 4), MISCREG_OSDLR_EL1 },
873  { MiscRegNum64(2, 0, 1, 4, 4), MISCREG_DBGPRCR_EL1 },
874  { MiscRegNum64(2, 0, 7, 8, 6), MISCREG_DBGCLAIMSET_EL1 },
875  { MiscRegNum64(2, 0, 7, 9, 6), MISCREG_DBGCLAIMCLR_EL1 },
876  { MiscRegNum64(2, 0, 7, 14, 6), MISCREG_DBGAUTHSTATUS_EL1 },
877  { MiscRegNum64(2, 2, 0, 0, 0), MISCREG_TEECR32_EL1 },
878  { MiscRegNum64(2, 2, 1, 0, 0), MISCREG_TEEHBR32_EL1 },
879  { MiscRegNum64(2, 3, 0, 1, 0), MISCREG_MDCCSR_EL0 },
880  { MiscRegNum64(2, 3, 0, 4, 0), MISCREG_MDDTR_EL0 },
881  { MiscRegNum64(2, 3, 0, 5, 0), MISCREG_MDDTRRX_EL0 },
882  { MiscRegNum64(2, 4, 0, 7, 0), MISCREG_DBGVCR32_EL2 },
883  { MiscRegNum64(3, 0, 0, 0, 0), MISCREG_MIDR_EL1 },
884  { MiscRegNum64(3, 0, 0, 0, 5), MISCREG_MPIDR_EL1 },
885  { MiscRegNum64(3, 0, 0, 0, 6), MISCREG_REVIDR_EL1 },
886  { MiscRegNum64(3, 0, 0, 1, 0), MISCREG_ID_PFR0_EL1 },
887  { MiscRegNum64(3, 0, 0, 1, 1), MISCREG_ID_PFR1_EL1 },
888  { MiscRegNum64(3, 0, 0, 1, 2), MISCREG_ID_DFR0_EL1 },
889  { MiscRegNum64(3, 0, 0, 1, 3), MISCREG_ID_AFR0_EL1 },
890  { MiscRegNum64(3, 0, 0, 1, 4), MISCREG_ID_MMFR0_EL1 },
891  { MiscRegNum64(3, 0, 0, 1, 5), MISCREG_ID_MMFR1_EL1 },
892  { MiscRegNum64(3, 0, 0, 1, 6), MISCREG_ID_MMFR2_EL1 },
893  { MiscRegNum64(3, 0, 0, 1, 7), MISCREG_ID_MMFR3_EL1 },
894  { MiscRegNum64(3, 0, 0, 2, 0), MISCREG_ID_ISAR0_EL1 },
895  { MiscRegNum64(3, 0, 0, 2, 1), MISCREG_ID_ISAR1_EL1 },
896  { MiscRegNum64(3, 0, 0, 2, 2), MISCREG_ID_ISAR2_EL1 },
897  { MiscRegNum64(3, 0, 0, 2, 3), MISCREG_ID_ISAR3_EL1 },
898  { MiscRegNum64(3, 0, 0, 2, 4), MISCREG_ID_ISAR4_EL1 },
899  { MiscRegNum64(3, 0, 0, 2, 5), MISCREG_ID_ISAR5_EL1 },
900  { MiscRegNum64(3, 0, 0, 2, 6), MISCREG_ID_MMFR4_EL1 },
901  { MiscRegNum64(3, 0, 0, 2, 7), MISCREG_ID_ISAR6_EL1 },
902  { MiscRegNum64(3, 0, 0, 3, 0), MISCREG_MVFR0_EL1 },
903  { MiscRegNum64(3, 0, 0, 3, 1), MISCREG_MVFR1_EL1 },
904  { MiscRegNum64(3, 0, 0, 3, 2), MISCREG_MVFR2_EL1 },
905  { MiscRegNum64(3, 0, 0, 3, 3), MISCREG_RAZ },
906  { MiscRegNum64(3, 0, 0, 3, 4), MISCREG_RAZ },
907  { MiscRegNum64(3, 0, 0, 3, 5), MISCREG_RAZ },
908  { MiscRegNum64(3, 0, 0, 3, 6), MISCREG_RAZ },
909  { MiscRegNum64(3, 0, 0, 3, 7), MISCREG_RAZ },
910  { MiscRegNum64(3, 0, 0, 4, 0), MISCREG_ID_AA64PFR0_EL1 },
911  { MiscRegNum64(3, 0, 0, 4, 1), MISCREG_ID_AA64PFR1_EL1 },
912  { MiscRegNum64(3, 0, 0, 4, 2), MISCREG_RAZ },
913  { MiscRegNum64(3, 0, 0, 4, 3), MISCREG_RAZ },
914  { MiscRegNum64(3, 0, 0, 4, 4), MISCREG_ID_AA64ZFR0_EL1 },
915  { MiscRegNum64(3, 0, 0, 4, 5), MISCREG_RAZ },
916  { MiscRegNum64(3, 0, 0, 4, 6), MISCREG_RAZ },
917  { MiscRegNum64(3, 0, 0, 4, 7), MISCREG_RAZ },
918  { MiscRegNum64(3, 0, 0, 5, 0), MISCREG_ID_AA64DFR0_EL1 },
919  { MiscRegNum64(3, 0, 0, 5, 1), MISCREG_ID_AA64DFR1_EL1 },
920  { MiscRegNum64(3, 0, 0, 5, 2), MISCREG_RAZ },
921  { MiscRegNum64(3, 0, 0, 5, 3), MISCREG_RAZ },
922  { MiscRegNum64(3, 0, 0, 5, 4), MISCREG_ID_AA64AFR0_EL1 },
923  { MiscRegNum64(3, 0, 0, 5, 5), MISCREG_ID_AA64AFR1_EL1 },
924  { MiscRegNum64(3, 0, 0, 5, 6), MISCREG_RAZ },
925  { MiscRegNum64(3, 0, 0, 5, 7), MISCREG_RAZ },
926  { MiscRegNum64(3, 0, 0, 6, 0), MISCREG_ID_AA64ISAR0_EL1 },
927  { MiscRegNum64(3, 0, 0, 6, 1), MISCREG_ID_AA64ISAR1_EL1 },
928  { MiscRegNum64(3, 0, 0, 6, 2), MISCREG_RAZ },
929  { MiscRegNum64(3, 0, 0, 6, 3), MISCREG_RAZ },
930  { MiscRegNum64(3, 0, 0, 6, 4), MISCREG_RAZ },
931  { MiscRegNum64(3, 0, 0, 6, 5), MISCREG_RAZ },
932  { MiscRegNum64(3, 0, 0, 6, 6), MISCREG_RAZ },
933  { MiscRegNum64(3, 0, 0, 6, 7), MISCREG_RAZ },
934  { MiscRegNum64(3, 0, 0, 7, 0), MISCREG_ID_AA64MMFR0_EL1 },
935  { MiscRegNum64(3, 0, 0, 7, 1), MISCREG_ID_AA64MMFR1_EL1 },
936  { MiscRegNum64(3, 0, 0, 7, 2), MISCREG_ID_AA64MMFR2_EL1 },
937  { MiscRegNum64(3, 0, 0, 7, 3), MISCREG_RAZ },
938  { MiscRegNum64(3, 0, 0, 7, 4), MISCREG_RAZ },
939  { MiscRegNum64(3, 0, 0, 7, 5), MISCREG_RAZ },
940  { MiscRegNum64(3, 0, 0, 7, 6), MISCREG_RAZ },
941  { MiscRegNum64(3, 0, 0, 7, 7), MISCREG_RAZ },
942  { MiscRegNum64(3, 0, 1, 0, 0), MISCREG_SCTLR_EL1 },
943  { MiscRegNum64(3, 0, 1, 0, 1), MISCREG_ACTLR_EL1 },
944  { MiscRegNum64(3, 0, 1, 0, 2), MISCREG_CPACR_EL1 },
945  { MiscRegNum64(3, 0, 1, 2, 0), MISCREG_ZCR_EL1 },
946  { MiscRegNum64(3, 0, 2, 0, 0), MISCREG_TTBR0_EL1 },
947  { MiscRegNum64(3, 0, 2, 0, 1), MISCREG_TTBR1_EL1 },
948  { MiscRegNum64(3, 0, 2, 0, 2), MISCREG_TCR_EL1 },
949  { MiscRegNum64(3, 0, 2, 1, 0), MISCREG_APIAKeyLo_EL1 },
950  { MiscRegNum64(3, 0, 2, 1, 1), MISCREG_APIAKeyHi_EL1 },
951  { MiscRegNum64(3, 0, 2, 1, 2), MISCREG_APIBKeyLo_EL1 },
952  { MiscRegNum64(3, 0, 2, 1, 3), MISCREG_APIBKeyHi_EL1 },
953  { MiscRegNum64(3, 0, 2, 2, 0), MISCREG_APDAKeyLo_EL1 },
954  { MiscRegNum64(3, 0, 2, 2, 1), MISCREG_APDAKeyHi_EL1 },
955  { MiscRegNum64(3, 0, 2, 2, 2), MISCREG_APDBKeyLo_EL1 },
956  { MiscRegNum64(3, 0, 2, 2, 3), MISCREG_APDBKeyHi_EL1 },
957  { MiscRegNum64(3, 0, 2, 3, 0), MISCREG_APGAKeyLo_EL1 },
958  { MiscRegNum64(3, 0, 2, 3, 1), MISCREG_APGAKeyHi_EL1 },
959  { MiscRegNum64(3, 0, 4, 0, 0), MISCREG_SPSR_EL1 },
960  { MiscRegNum64(3, 0, 4, 0, 1), MISCREG_ELR_EL1 },
961  { MiscRegNum64(3, 0, 4, 1, 0), MISCREG_SP_EL0 },
962  { MiscRegNum64(3, 0, 4, 2, 0), MISCREG_SPSEL },
963  { MiscRegNum64(3, 0, 4, 2, 2), MISCREG_CURRENTEL },
964  { MiscRegNum64(3, 0, 4, 2, 3), MISCREG_PAN },
965  { MiscRegNum64(3, 0, 4, 2, 4), MISCREG_UAO },
966  { MiscRegNum64(3, 0, 4, 6, 0), MISCREG_ICC_PMR_EL1 },
967  { MiscRegNum64(3, 0, 5, 1, 0), MISCREG_AFSR0_EL1 },
968  { MiscRegNum64(3, 0, 5, 1, 1), MISCREG_AFSR1_EL1 },
969  { MiscRegNum64(3, 0, 5, 2, 0), MISCREG_ESR_EL1 },
970  { MiscRegNum64(3, 0, 5, 3, 0), MISCREG_ERRIDR_EL1 },
971  { MiscRegNum64(3, 0, 5, 3, 1), MISCREG_ERRSELR_EL1 },
972  { MiscRegNum64(3, 0, 5, 4, 0), MISCREG_ERXFR_EL1 },
973  { MiscRegNum64(3, 0, 5, 4, 1), MISCREG_ERXCTLR_EL1 },
974  { MiscRegNum64(3, 0, 5, 4, 2), MISCREG_ERXSTATUS_EL1 },
975  { MiscRegNum64(3, 0, 5, 4, 3), MISCREG_ERXADDR_EL1 },
976  { MiscRegNum64(3, 0, 5, 5, 0), MISCREG_ERXMISC0_EL1 },
977  { MiscRegNum64(3, 0, 5, 5, 1), MISCREG_ERXMISC1_EL1 },
978  { MiscRegNum64(3, 0, 6, 0, 0), MISCREG_FAR_EL1 },
979  { MiscRegNum64(3, 0, 7, 4, 0), MISCREG_PAR_EL1 },
980  { MiscRegNum64(3, 0, 9, 14, 1), MISCREG_PMINTENSET_EL1 },
981  { MiscRegNum64(3, 0, 9, 14, 2), MISCREG_PMINTENCLR_EL1 },
982  { MiscRegNum64(3, 0, 10, 2, 0), MISCREG_MAIR_EL1 },
983  { MiscRegNum64(3, 0, 10, 3, 0), MISCREG_AMAIR_EL1 },
984  { MiscRegNum64(3, 0, 12, 0, 0), MISCREG_VBAR_EL1 },
985  { MiscRegNum64(3, 0, 12, 0, 1), MISCREG_RVBAR_EL1 },
986  { MiscRegNum64(3, 0, 12, 1, 0), MISCREG_ISR_EL1 },
987  { MiscRegNum64(3, 0, 12, 1, 1), MISCREG_DISR_EL1 },
988  { MiscRegNum64(3, 0, 12, 8, 0), MISCREG_ICC_IAR0_EL1 },
989  { MiscRegNum64(3, 0, 12, 8, 1), MISCREG_ICC_EOIR0_EL1 },
990  { MiscRegNum64(3, 0, 12, 8, 2), MISCREG_ICC_HPPIR0_EL1 },
991  { MiscRegNum64(3, 0, 12, 8, 3), MISCREG_ICC_BPR0_EL1 },
992  { MiscRegNum64(3, 0, 12, 8, 4), MISCREG_ICC_AP0R0_EL1 },
993  { MiscRegNum64(3, 0, 12, 8, 5), MISCREG_ICC_AP0R1_EL1 },
994  { MiscRegNum64(3, 0, 12, 8, 6), MISCREG_ICC_AP0R2_EL1 },
995  { MiscRegNum64(3, 0, 12, 8, 7), MISCREG_ICC_AP0R3_EL1 },
996  { MiscRegNum64(3, 0, 12, 9, 0), MISCREG_ICC_AP1R0_EL1 },
997  { MiscRegNum64(3, 0, 12, 9, 1), MISCREG_ICC_AP1R1_EL1 },
998  { MiscRegNum64(3, 0, 12, 9, 2), MISCREG_ICC_AP1R2_EL1 },
999  { MiscRegNum64(3, 0, 12, 9, 3), MISCREG_ICC_AP1R3_EL1 },
1000  { MiscRegNum64(3, 0, 12, 11, 1), MISCREG_ICC_DIR_EL1 },
1001  { MiscRegNum64(3, 0, 12, 11, 3), MISCREG_ICC_RPR_EL1 },
1002  { MiscRegNum64(3, 0, 12, 11, 5), MISCREG_ICC_SGI1R_EL1 },
1003  { MiscRegNum64(3, 0, 12, 11, 6), MISCREG_ICC_ASGI1R_EL1 },
1004  { MiscRegNum64(3, 0, 12, 11, 7), MISCREG_ICC_SGI0R_EL1 },
1005  { MiscRegNum64(3, 0, 12, 12, 0), MISCREG_ICC_IAR1_EL1 },
1006  { MiscRegNum64(3, 0, 12, 12, 1), MISCREG_ICC_EOIR1_EL1 },
1007  { MiscRegNum64(3, 0, 12, 12, 2), MISCREG_ICC_HPPIR1_EL1 },
1008  { MiscRegNum64(3, 0, 12, 12, 3), MISCREG_ICC_BPR1_EL1 },
1009  { MiscRegNum64(3, 0, 12, 12, 4), MISCREG_ICC_CTLR_EL1 },
1010  { MiscRegNum64(3, 0, 12, 12, 5), MISCREG_ICC_SRE_EL1 },
1011  { MiscRegNum64(3, 0, 12, 12, 6), MISCREG_ICC_IGRPEN0_EL1 },
1012  { MiscRegNum64(3, 0, 12, 12, 7), MISCREG_ICC_IGRPEN1_EL1 },
1013  { MiscRegNum64(3, 0, 13, 0, 1), MISCREG_CONTEXTIDR_EL1 },
1014  { MiscRegNum64(3, 0, 13, 0, 4), MISCREG_TPIDR_EL1 },
1015  { MiscRegNum64(3, 0, 14, 1, 0), MISCREG_CNTKCTL_EL1 },
1016  { MiscRegNum64(3, 0, 15, 0, 0), MISCREG_IL1DATA0_EL1 },
1017  { MiscRegNum64(3, 0, 15, 0, 1), MISCREG_IL1DATA1_EL1 },
1018  { MiscRegNum64(3, 0, 15, 0, 2), MISCREG_IL1DATA2_EL1 },
1019  { MiscRegNum64(3, 0, 15, 0, 3), MISCREG_IL1DATA3_EL1 },
1020  { MiscRegNum64(3, 0, 15, 1, 0), MISCREG_DL1DATA0_EL1 },
1021  { MiscRegNum64(3, 0, 15, 1, 1), MISCREG_DL1DATA1_EL1 },
1022  { MiscRegNum64(3, 0, 15, 1, 2), MISCREG_DL1DATA2_EL1 },
1023  { MiscRegNum64(3, 0, 15, 1, 3), MISCREG_DL1DATA3_EL1 },
1024  { MiscRegNum64(3, 0, 15, 1, 4), MISCREG_DL1DATA4_EL1 },
1025  { MiscRegNum64(3, 1, 0, 0, 0), MISCREG_CCSIDR_EL1 },
1026  { MiscRegNum64(3, 1, 0, 0, 1), MISCREG_CLIDR_EL1 },
1027  { MiscRegNum64(3, 1, 0, 0, 7), MISCREG_AIDR_EL1 },
1028  { MiscRegNum64(3, 1, 11, 0, 2), MISCREG_L2CTLR_EL1 },
1029  { MiscRegNum64(3, 1, 11, 0, 3), MISCREG_L2ECTLR_EL1 },
1030  { MiscRegNum64(3, 1, 15, 0, 0), MISCREG_L2ACTLR_EL1 },
1031  { MiscRegNum64(3, 1, 15, 2, 0), MISCREG_CPUACTLR_EL1 },
1032  { MiscRegNum64(3, 1, 15, 2, 1), MISCREG_CPUECTLR_EL1 },
1033  { MiscRegNum64(3, 1, 15, 2, 2), MISCREG_CPUMERRSR_EL1 },
1034  { MiscRegNum64(3, 1, 15, 2, 3), MISCREG_L2MERRSR_EL1 },
1035  { MiscRegNum64(3, 1, 15, 3, 0), MISCREG_CBAR_EL1 },
1036  { MiscRegNum64(3, 2, 0, 0, 0), MISCREG_CSSELR_EL1 },
1037  { MiscRegNum64(3, 3, 0, 0, 1), MISCREG_CTR_EL0 },
1038  { MiscRegNum64(3, 3, 0, 0, 7), MISCREG_DCZID_EL0 },
1039  { MiscRegNum64(3, 3, 4, 2, 0), MISCREG_NZCV },
1040  { MiscRegNum64(3, 3, 4, 2, 1), MISCREG_DAIF },
1041  { MiscRegNum64(3, 3, 4, 4, 0), MISCREG_FPCR },
1042  { MiscRegNum64(3, 3, 4, 4, 1), MISCREG_FPSR },
1043  { MiscRegNum64(3, 3, 4, 5, 0), MISCREG_DSPSR_EL0 },
1044  { MiscRegNum64(3, 3, 4, 5, 1), MISCREG_DLR_EL0 },
1045  { MiscRegNum64(3, 3, 9, 12, 0), MISCREG_PMCR_EL0 },
1046  { MiscRegNum64(3, 3, 9, 12, 1), MISCREG_PMCNTENSET_EL0 },
1047  { MiscRegNum64(3, 3, 9, 12, 2), MISCREG_PMCNTENCLR_EL0 },
1048  { MiscRegNum64(3, 3, 9, 12, 3), MISCREG_PMOVSCLR_EL0 },
1049  { MiscRegNum64(3, 3, 9, 12, 4), MISCREG_PMSWINC_EL0 },
1050  { MiscRegNum64(3, 3, 9, 12, 5), MISCREG_PMSELR_EL0 },
1051  { MiscRegNum64(3, 3, 9, 12, 6), MISCREG_PMCEID0_EL0 },
1052  { MiscRegNum64(3, 3, 9, 12, 7), MISCREG_PMCEID1_EL0 },
1053  { MiscRegNum64(3, 3, 9, 13, 0), MISCREG_PMCCNTR_EL0 },
1054  { MiscRegNum64(3, 3, 9, 13, 1), MISCREG_PMXEVTYPER_EL0 },
1055  { MiscRegNum64(3, 3, 9, 13, 2), MISCREG_PMXEVCNTR_EL0 },
1056  { MiscRegNum64(3, 3, 9, 14, 0), MISCREG_PMUSERENR_EL0 },
1057  { MiscRegNum64(3, 3, 9, 14, 3), MISCREG_PMOVSSET_EL0 },
1058  { MiscRegNum64(3, 3, 13, 0, 2), MISCREG_TPIDR_EL0 },
1059  { MiscRegNum64(3, 3, 13, 0, 3), MISCREG_TPIDRRO_EL0 },
1060  { MiscRegNum64(3, 3, 14, 0, 0), MISCREG_CNTFRQ_EL0 },
1061  { MiscRegNum64(3, 3, 14, 0, 1), MISCREG_CNTPCT_EL0 },
1062  { MiscRegNum64(3, 3, 14, 0, 2), MISCREG_CNTVCT_EL0 },
1063  { MiscRegNum64(3, 3, 14, 2, 0), MISCREG_CNTP_TVAL_EL0 },
1064  { MiscRegNum64(3, 3, 14, 2, 1), MISCREG_CNTP_CTL_EL0 },
1065  { MiscRegNum64(3, 3, 14, 2, 2), MISCREG_CNTP_CVAL_EL0 },
1066  { MiscRegNum64(3, 3, 14, 3, 0), MISCREG_CNTV_TVAL_EL0 },
1067  { MiscRegNum64(3, 3, 14, 3, 1), MISCREG_CNTV_CTL_EL0 },
1068  { MiscRegNum64(3, 3, 14, 3, 2), MISCREG_CNTV_CVAL_EL0 },
1069  { MiscRegNum64(3, 3, 14, 8, 0), MISCREG_PMEVCNTR0_EL0 },
1070  { MiscRegNum64(3, 3, 14, 8, 1), MISCREG_PMEVCNTR1_EL0 },
1071  { MiscRegNum64(3, 3, 14, 8, 2), MISCREG_PMEVCNTR2_EL0 },
1072  { MiscRegNum64(3, 3, 14, 8, 3), MISCREG_PMEVCNTR3_EL0 },
1073  { MiscRegNum64(3, 3, 14, 8, 4), MISCREG_PMEVCNTR4_EL0 },
1074  { MiscRegNum64(3, 3, 14, 8, 5), MISCREG_PMEVCNTR5_EL0 },
1075  { MiscRegNum64(3, 3, 14, 12, 0), MISCREG_PMEVTYPER0_EL0 },
1076  { MiscRegNum64(3, 3, 14, 12, 1), MISCREG_PMEVTYPER1_EL0 },
1077  { MiscRegNum64(3, 3, 14, 12, 2), MISCREG_PMEVTYPER2_EL0 },
1078  { MiscRegNum64(3, 3, 14, 12, 3), MISCREG_PMEVTYPER3_EL0 },
1079  { MiscRegNum64(3, 3, 14, 12, 4), MISCREG_PMEVTYPER4_EL0 },
1080  { MiscRegNum64(3, 3, 14, 12, 5), MISCREG_PMEVTYPER5_EL0 },
1081  { MiscRegNum64(3, 3, 14, 15, 7), MISCREG_PMCCFILTR_EL0 },
1082  { MiscRegNum64(3, 4, 0, 0, 0), MISCREG_VPIDR_EL2 },
1083  { MiscRegNum64(3, 4, 0, 0, 5), MISCREG_VMPIDR_EL2 },
1084  { MiscRegNum64(3, 4, 1, 0, 0), MISCREG_SCTLR_EL2 },
1085  { MiscRegNum64(3, 4, 1, 0, 1), MISCREG_ACTLR_EL2 },
1086  { MiscRegNum64(3, 4, 1, 1, 0), MISCREG_HCR_EL2 },
1087  { MiscRegNum64(3, 4, 1, 1, 1), MISCREG_MDCR_EL2 },
1088  { MiscRegNum64(3, 4, 1, 1, 2), MISCREG_CPTR_EL2 },
1089  { MiscRegNum64(3, 4, 1, 1, 3), MISCREG_HSTR_EL2 },
1090  { MiscRegNum64(3, 4, 1, 1, 7), MISCREG_HACR_EL2 },
1091  { MiscRegNum64(3, 4, 1, 2, 0), MISCREG_ZCR_EL2 },
1092  { MiscRegNum64(3, 4, 2, 0, 0), MISCREG_TTBR0_EL2 },
1093  { MiscRegNum64(3, 4, 2, 0, 1), MISCREG_TTBR1_EL2 },
1094  { MiscRegNum64(3, 4, 2, 0, 2), MISCREG_TCR_EL2 },
1095  { MiscRegNum64(3, 4, 2, 1, 0), MISCREG_VTTBR_EL2 },
1096  { MiscRegNum64(3, 4, 2, 1, 2), MISCREG_VTCR_EL2 },
1097  { MiscRegNum64(3, 4, 2, 6, 0), MISCREG_VSTTBR_EL2 },
1098  { MiscRegNum64(3, 4, 2, 6, 2), MISCREG_VSTCR_EL2 },
1099  { MiscRegNum64(3, 4, 3, 0, 0), MISCREG_DACR32_EL2 },
1100  { MiscRegNum64(3, 4, 4, 0, 0), MISCREG_SPSR_EL2 },
1101  { MiscRegNum64(3, 4, 4, 0, 1), MISCREG_ELR_EL2 },
1102  { MiscRegNum64(3, 4, 4, 1, 0), MISCREG_SP_EL1 },
1103  { MiscRegNum64(3, 4, 4, 3, 0), MISCREG_SPSR_IRQ_AA64 },
1104  { MiscRegNum64(3, 4, 4, 3, 1), MISCREG_SPSR_ABT_AA64 },
1105  { MiscRegNum64(3, 4, 4, 3, 2), MISCREG_SPSR_UND_AA64 },
1106  { MiscRegNum64(3, 4, 4, 3, 3), MISCREG_SPSR_FIQ_AA64 },
1107  { MiscRegNum64(3, 4, 5, 0, 1), MISCREG_IFSR32_EL2 },
1108  { MiscRegNum64(3, 4, 5, 1, 0), MISCREG_AFSR0_EL2 },
1109  { MiscRegNum64(3, 4, 5, 1, 1), MISCREG_AFSR1_EL2 },
1110  { MiscRegNum64(3, 4, 5, 2, 0), MISCREG_ESR_EL2 },
1111  { MiscRegNum64(3, 4, 5, 2, 3), MISCREG_VSESR_EL2 },
1112  { MiscRegNum64(3, 4, 5, 3, 0), MISCREG_FPEXC32_EL2 },
1113  { MiscRegNum64(3, 4, 6, 0, 0), MISCREG_FAR_EL2 },
1114  { MiscRegNum64(3, 4, 6, 0, 4), MISCREG_HPFAR_EL2 },
1115  { MiscRegNum64(3, 4, 10, 2, 0), MISCREG_MAIR_EL2 },
1116  { MiscRegNum64(3, 4, 10, 3, 0), MISCREG_AMAIR_EL2 },
1117  { MiscRegNum64(3, 4, 12, 0, 0), MISCREG_VBAR_EL2 },
1118  { MiscRegNum64(3, 4, 12, 0, 1), MISCREG_RVBAR_EL2 },
1119  { MiscRegNum64(3, 4, 12, 1, 1), MISCREG_VDISR_EL2 },
1120  { MiscRegNum64(3, 4, 12, 8, 0), MISCREG_ICH_AP0R0_EL2 },
1121  { MiscRegNum64(3, 4, 12, 8, 1), MISCREG_ICH_AP0R1_EL2 },
1122  { MiscRegNum64(3, 4, 12, 8, 2), MISCREG_ICH_AP0R2_EL2 },
1123  { MiscRegNum64(3, 4, 12, 8, 3), MISCREG_ICH_AP0R3_EL2 },
1124  { MiscRegNum64(3, 4, 12, 9, 0), MISCREG_ICH_AP1R0_EL2 },
1125  { MiscRegNum64(3, 4, 12, 9, 1), MISCREG_ICH_AP1R1_EL2 },
1126  { MiscRegNum64(3, 4, 12, 9, 2), MISCREG_ICH_AP1R2_EL2 },
1127  { MiscRegNum64(3, 4, 12, 9, 3), MISCREG_ICH_AP1R3_EL2 },
1128  { MiscRegNum64(3, 4, 12, 9, 5), MISCREG_ICC_SRE_EL2 },
1129  { MiscRegNum64(3, 4, 12, 11, 0), MISCREG_ICH_HCR_EL2 },
1130  { MiscRegNum64(3, 4, 12, 11, 1), MISCREG_ICH_VTR_EL2 },
1131  { MiscRegNum64(3, 4, 12, 11, 2), MISCREG_ICH_MISR_EL2 },
1132  { MiscRegNum64(3, 4, 12, 11, 3), MISCREG_ICH_EISR_EL2 },
1133  { MiscRegNum64(3, 4, 12, 11, 5), MISCREG_ICH_ELRSR_EL2 },
1134  { MiscRegNum64(3, 4, 12, 11, 7), MISCREG_ICH_VMCR_EL2 },
1135  { MiscRegNum64(3, 4, 12, 12, 0), MISCREG_ICH_LR0_EL2 },
1136  { MiscRegNum64(3, 4, 12, 12, 1), MISCREG_ICH_LR1_EL2 },
1137  { MiscRegNum64(3, 4, 12, 12, 2), MISCREG_ICH_LR2_EL2 },
1138  { MiscRegNum64(3, 4, 12, 12, 3), MISCREG_ICH_LR3_EL2 },
1139  { MiscRegNum64(3, 4, 12, 12, 4), MISCREG_ICH_LR4_EL2 },
1140  { MiscRegNum64(3, 4, 12, 12, 5), MISCREG_ICH_LR5_EL2 },
1141  { MiscRegNum64(3, 4, 12, 12, 6), MISCREG_ICH_LR6_EL2 },
1142  { MiscRegNum64(3, 4, 12, 12, 7), MISCREG_ICH_LR7_EL2 },
1143  { MiscRegNum64(3, 4, 12, 13, 0), MISCREG_ICH_LR8_EL2 },
1144  { MiscRegNum64(3, 4, 12, 13, 1), MISCREG_ICH_LR9_EL2 },
1145  { MiscRegNum64(3, 4, 12, 13, 2), MISCREG_ICH_LR10_EL2 },
1146  { MiscRegNum64(3, 4, 12, 13, 3), MISCREG_ICH_LR11_EL2 },
1147  { MiscRegNum64(3, 4, 12, 13, 4), MISCREG_ICH_LR12_EL2 },
1148  { MiscRegNum64(3, 4, 12, 13, 5), MISCREG_ICH_LR13_EL2 },
1149  { MiscRegNum64(3, 4, 12, 13, 6), MISCREG_ICH_LR14_EL2 },
1150  { MiscRegNum64(3, 4, 12, 13, 7), MISCREG_ICH_LR15_EL2 },
1151  { MiscRegNum64(3, 4, 13, 0, 1), MISCREG_CONTEXTIDR_EL2 },
1152  { MiscRegNum64(3, 4, 13, 0, 2), MISCREG_TPIDR_EL2 },
1153  { MiscRegNum64(3, 4, 14, 0, 3), MISCREG_CNTVOFF_EL2 },
1154  { MiscRegNum64(3, 4, 14, 1, 0), MISCREG_CNTHCTL_EL2 },
1155  { MiscRegNum64(3, 4, 14, 2, 0), MISCREG_CNTHP_TVAL_EL2 },
1156  { MiscRegNum64(3, 4, 14, 2, 1), MISCREG_CNTHP_CTL_EL2 },
1157  { MiscRegNum64(3, 4, 14, 2, 2), MISCREG_CNTHP_CVAL_EL2 },
1158  { MiscRegNum64(3, 4, 14, 3, 0), MISCREG_CNTHV_TVAL_EL2 },
1159  { MiscRegNum64(3, 4, 14, 3, 1), MISCREG_CNTHV_CTL_EL2 },
1160  { MiscRegNum64(3, 4, 14, 3, 2), MISCREG_CNTHV_CVAL_EL2 },
1161  { MiscRegNum64(3, 4, 14, 4, 0), MISCREG_CNTHVS_TVAL_EL2 },
1162  { MiscRegNum64(3, 4, 14, 4, 1), MISCREG_CNTHVS_CTL_EL2 },
1163  { MiscRegNum64(3, 4, 14, 4, 2), MISCREG_CNTHVS_CVAL_EL2 },
1164  { MiscRegNum64(3, 4, 14, 5, 0), MISCREG_CNTHPS_TVAL_EL2 },
1165  { MiscRegNum64(3, 4, 14, 5, 1), MISCREG_CNTHPS_CTL_EL2 },
1166  { MiscRegNum64(3, 4, 14, 5, 2), MISCREG_CNTHPS_CVAL_EL2 },
1167  { MiscRegNum64(3, 5, 1, 0, 0), MISCREG_SCTLR_EL12 },
1168  { MiscRegNum64(3, 5, 1, 0, 2), MISCREG_CPACR_EL12 },
1169  { MiscRegNum64(3, 5, 1, 2, 0), MISCREG_ZCR_EL12 },
1170  { MiscRegNum64(3, 5, 2, 0, 0), MISCREG_TTBR0_EL12 },
1171  { MiscRegNum64(3, 5, 2, 0, 1), MISCREG_TTBR1_EL12 },
1172  { MiscRegNum64(3, 5, 2, 0, 2), MISCREG_TCR_EL12 },
1173  { MiscRegNum64(3, 5, 4, 0, 0), MISCREG_SPSR_EL12 },
1174  { MiscRegNum64(3, 5, 4, 0, 1), MISCREG_ELR_EL12 },
1175  { MiscRegNum64(3, 5, 5, 1, 0), MISCREG_AFSR0_EL12 },
1176  { MiscRegNum64(3, 5, 5, 1, 1), MISCREG_AFSR1_EL12 },
1177  { MiscRegNum64(3, 5, 5, 2, 0), MISCREG_ESR_EL12 },
1178  { MiscRegNum64(3, 5, 6, 0, 0), MISCREG_FAR_EL12 },
1179  { MiscRegNum64(3, 5, 10, 2, 0), MISCREG_MAIR_EL12 },
1180  { MiscRegNum64(3, 5, 10, 3, 0), MISCREG_AMAIR_EL12 },
1181  { MiscRegNum64(3, 5, 12, 0, 0), MISCREG_VBAR_EL12 },
1182  { MiscRegNum64(3, 5, 13, 0, 1), MISCREG_CONTEXTIDR_EL12 },
1183  { MiscRegNum64(3, 5, 14, 1, 0), MISCREG_CNTKCTL_EL12 },
1184  { MiscRegNum64(3, 5, 14, 2, 0), MISCREG_CNTP_TVAL_EL02 },
1185  { MiscRegNum64(3, 5, 14, 2, 1), MISCREG_CNTP_CTL_EL02 },
1186  { MiscRegNum64(3, 5, 14, 2, 2), MISCREG_CNTP_CVAL_EL02 },
1187  { MiscRegNum64(3, 5, 14, 3, 0), MISCREG_CNTV_TVAL_EL02 },
1188  { MiscRegNum64(3, 5, 14, 3, 1), MISCREG_CNTV_CTL_EL02 },
1189  { MiscRegNum64(3, 5, 14, 3, 2), MISCREG_CNTV_CVAL_EL02 },
1190  { MiscRegNum64(3, 6, 1, 0, 0), MISCREG_SCTLR_EL3 },
1191  { MiscRegNum64(3, 6, 1, 0, 1), MISCREG_ACTLR_EL3 },
1192  { MiscRegNum64(3, 6, 1, 1, 0), MISCREG_SCR_EL3 },
1193  { MiscRegNum64(3, 6, 1, 1, 1), MISCREG_SDER32_EL3 },
1194  { MiscRegNum64(3, 6, 1, 1, 2), MISCREG_CPTR_EL3 },
1195  { MiscRegNum64(3, 6, 1, 2, 0), MISCREG_ZCR_EL3 },
1196  { MiscRegNum64(3, 6, 1, 3, 1), MISCREG_MDCR_EL3 },
1197  { MiscRegNum64(3, 6, 2, 0, 0), MISCREG_TTBR0_EL3 },
1198  { MiscRegNum64(3, 6, 2, 0, 2), MISCREG_TCR_EL3 },
1199  { MiscRegNum64(3, 6, 4, 0, 0), MISCREG_SPSR_EL3 },
1200  { MiscRegNum64(3, 6, 4, 0, 1), MISCREG_ELR_EL3 },
1201  { MiscRegNum64(3, 6, 4, 1, 0), MISCREG_SP_EL2 },
1202  { MiscRegNum64(3, 6, 5, 1, 0), MISCREG_AFSR0_EL3 },
1203  { MiscRegNum64(3, 6, 5, 1, 1), MISCREG_AFSR1_EL3 },
1204  { MiscRegNum64(3, 6, 5, 2, 0), MISCREG_ESR_EL3 },
1205  { MiscRegNum64(3, 6, 6, 0, 0), MISCREG_FAR_EL3 },
1206  { MiscRegNum64(3, 6, 10, 2, 0), MISCREG_MAIR_EL3 },
1207  { MiscRegNum64(3, 6, 10, 3, 0), MISCREG_AMAIR_EL3 },
1208  { MiscRegNum64(3, 6, 12, 0, 0), MISCREG_VBAR_EL3 },
1209  { MiscRegNum64(3, 6, 12, 0, 1), MISCREG_RVBAR_EL3 },
1210  { MiscRegNum64(3, 6, 12, 0, 2), MISCREG_RMR_EL3 },
1211  { MiscRegNum64(3, 6, 12, 12, 4), MISCREG_ICC_CTLR_EL3 },
1212  { MiscRegNum64(3, 6, 12, 12, 5), MISCREG_ICC_SRE_EL3 },
1213  { MiscRegNum64(3, 6, 12, 12, 7), MISCREG_ICC_IGRPEN1_EL3 },
1214  { MiscRegNum64(3, 6, 13, 0, 2), MISCREG_TPIDR_EL3 },
1215  { MiscRegNum64(3, 7, 14, 2, 0), MISCREG_CNTPS_TVAL_EL1 },
1216  { MiscRegNum64(3, 7, 14, 2, 1), MISCREG_CNTPS_CTL_EL1 },
1217  { MiscRegNum64(3, 7, 14, 2, 2), MISCREG_CNTPS_CVAL_EL1 }
1218 };
1219 
1220 Fault
1221 faultSpEL0(const MiscRegLUTEntry &entry, ThreadContext *tc,
1222  const MiscRegOp64 &inst)
1223 {
1224  if (tc->readMiscReg(MISCREG_SPSEL) == 0)
1225  return inst.undefined();
1226  else
1227  return NoFault;
1228 }
1229 
1230 Fault
1231 faultDaif(const MiscRegLUTEntry &entry, ThreadContext *tc,
1232  const MiscRegOp64 &inst)
1233 {
1234  const bool el2_enabled = EL2Enabled(tc);
1235  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1236  const SCTLR sctlr = tc->readMiscRegNoEffect(MISCREG_SCTLR_EL1);
1237  if ((el2_enabled && hcr.e2h && hcr.tge) || sctlr.uma == 0) {
1238  if (el2_enabled && hcr.tge) {
1239  return inst.generateTrap(EL2);
1240  } else {
1241  return inst.generateTrap(EL1);
1242  }
1243  } else {
1244  return NoFault;
1245  }
1246 }
1247 
1248 Fault
1249 faultDczvaEL0(const MiscRegLUTEntry &entry, ThreadContext *tc,
1250  const MiscRegOp64 &inst)
1251 {
1252  if (!FullSystem)
1253  return NoFault;
1254 
1255  const SCTLR sctlr = tc->readMiscRegNoEffect(MISCREG_SCTLR_EL1);
1256  const SCTLR sctlr2 = tc->readMiscRegNoEffect(MISCREG_SCTLR_EL2);
1257  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1258 
1259  const bool el2_enabled = EL2Enabled(tc);
1260  const bool in_host = hcr.e2h && hcr.tge;
1261  if (!(el2_enabled && in_host) && !sctlr.dze) {
1262  if (el2_enabled && hcr.tge) {
1263  return inst.generateTrap(EL2);
1264  } else {
1265  return inst.generateTrap(EL1);
1266  }
1267  } else if (el2_enabled && !in_host && hcr.tdz) {
1268  return inst.generateTrap(EL2);
1269  } else if (el2_enabled && in_host && !sctlr2.dze) {
1270  return inst.generateTrap(EL2);
1271  } else {
1272  return NoFault;
1273  }
1274 }
1275 
1276 Fault
1277 faultCvacEL0(const MiscRegLUTEntry &entry, ThreadContext *tc,
1278  const MiscRegOp64 &inst)
1279 {
1280  const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1281  const SCTLR sctlr2 = tc->readMiscReg(MISCREG_SCTLR_EL2);
1282  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1283 
1284  const bool el2_enabled = EL2Enabled(tc);
1285  const bool in_host = hcr.e2h && hcr.tge;
1286  if (!(el2_enabled && in_host) && !sctlr.uci) {
1287  if (el2_enabled && hcr.tge) {
1288  return inst.generateTrap(EL2);
1289  } else {
1290  return inst.generateTrap(EL1);
1291  }
1292  } else if (el2_enabled && !in_host && hcr.tpc) {
1293  return inst.generateTrap(EL2);
1294  } else if (el2_enabled && in_host && !sctlr2.uci) {
1295  return inst.generateTrap(EL2);
1296  } else {
1297  return NoFault;
1298  }
1299 }
1300 
1301 Fault
1302 faultFpcrEL0(const MiscRegLUTEntry &entry, ThreadContext *tc,
1303  const MiscRegOp64 &inst)
1304 {
1305  const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
1306  const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
1307  const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1308 
1309  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1310  const bool el2_enabled = EL2Enabled(tc);
1311  const bool in_host = hcr.e2h && hcr.tge;
1312  if (!(el2_enabled && in_host) && cpacr.fpen != 0b11) {
1313  if (el2_enabled && hcr.tge) {
1314  return inst.generateTrap(EL2, ExceptionClass::UNKNOWN, inst.iss());
1315  } else {
1316  return inst.generateTrap(EL1,
1317  ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1318  }
1319  } else if (el2_enabled && in_host && cptr_el2.fpen != 0b11) {
1320  return inst.generateTrap(EL2,
1321  ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1322  } else if (el2_enabled && hcr.e2h && ((cptr_el2.fpen & 0b1) == 0b0)) {
1323  return inst.generateTrap(EL2,
1324  ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1325  } else if (el2_enabled && !hcr.e2h && cptr_el2.tfp) {
1326  return inst.generateTrap(EL2,
1327  ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1328  } else if (ArmSystem::haveEL(tc, EL3) && cptr_el3.tfp) {
1329  return inst.generateTrap(EL3,
1330  ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1331  } else {
1332  return NoFault;
1333  }
1334 }
1335 
1336 Fault
1337 faultFpcrEL1(const MiscRegLUTEntry &entry, ThreadContext *tc,
1338  const MiscRegOp64 &inst)
1339 {
1340  const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
1341  const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
1342  const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1343 
1344  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1345  const bool el2_enabled = EL2Enabled(tc);
1346  if ((cpacr.fpen & 0b1) == 0b0) {
1347  return inst.generateTrap(EL1,
1348  ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1349  } else if (el2_enabled && !hcr.e2h && cptr_el2.tfp) {
1350  return inst.generateTrap(EL2,
1351  ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1352  } else if (el2_enabled && hcr.e2h && ((cptr_el2.fpen & 0b1) == 0b0)) {
1353  return inst.generateTrap(EL2,
1354  ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1355  } else if (ArmSystem::haveEL(tc, EL3) && cptr_el3.tfp) {
1356  return inst.generateTrap(EL3,
1357  ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1358  } else {
1359  return NoFault;
1360  }
1361 }
1362 
1363 Fault
1364 faultFpcrEL2(const MiscRegLUTEntry &entry, ThreadContext *tc,
1365  const MiscRegOp64 &inst)
1366 {
1367  const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
1368  const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1369 
1370  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1371  if (!hcr.e2h && cptr_el2.tfp) {
1372  return inst.generateTrap(EL2,
1373  ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1374  } else if (hcr.e2h && ((cptr_el2.fpen & 0b1) == 0b0)) {
1375  return inst.generateTrap(EL2,
1376  ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1377  } else if (ArmSystem::haveEL(tc, EL3) && cptr_el3.tfp) {
1378  return inst.generateTrap(EL3,
1379  ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1380  } else {
1381  return NoFault;
1382  }
1383 }
1384 
1385 Fault
1386 faultFpcrEL3(const MiscRegLUTEntry &entry,
1387  ThreadContext *tc, const MiscRegOp64 &inst)
1388 {
1389  const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1390  if (cptr_el3.tfp) {
1391  return inst.generateTrap(EL3,
1392  ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1393  } else {
1394  return NoFault;
1395  }
1396 }
1397 
1398 Fault
1399 faultPouEL0(const MiscRegLUTEntry &entry,
1400  ThreadContext *tc, const MiscRegOp64 &inst)
1401 {
1402  const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1403  const SCTLR sctlr2 = tc->readMiscReg(MISCREG_SCTLR_EL2);
1404  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1405 
1406  const bool el2_enabled = EL2Enabled(tc);
1407  const bool in_host = hcr.e2h && hcr.tge;
1408  if (!(el2_enabled && in_host) && !sctlr.uci) {
1409  if (el2_enabled && hcr.tge) {
1410  return inst.generateTrap(EL2);
1411  } else {
1412  return inst.generateTrap(EL1);
1413  }
1414  } else if (el2_enabled && !in_host && hcr.tpu) {
1415  return inst.generateTrap(EL2);
1416  } else if (el2_enabled && !in_host && hcr.tocu) {
1417  return inst.generateTrap(EL2);
1418  } else if (el2_enabled && in_host && !sctlr2.uci) {
1419  return inst.generateTrap(EL2);
1420  } else {
1421  return NoFault;
1422  }
1423 }
1424 
1425 Fault
1426 faultPouEL1(const MiscRegLUTEntry &entry,
1427  ThreadContext *tc, const MiscRegOp64 &inst)
1428 {
1429  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1430  const bool el2_enabled = EL2Enabled(tc);
1431  if (el2_enabled && hcr.tpu) {
1432  return inst.generateTrap(EL2);
1433  } else if (el2_enabled && hcr.tocu) {
1434  return inst.generateTrap(EL2);
1435  } else {
1436  return NoFault;
1437  }
1438 }
1439 
1440 Fault
1441 faultPouIsEL1(const MiscRegLUTEntry &entry,
1442  ThreadContext *tc, const MiscRegOp64 &inst)
1443 {
1444  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1445  const bool el2_enabled = EL2Enabled(tc);
1446  if (el2_enabled && hcr.tpu) {
1447  return inst.generateTrap(EL2);
1448  } else if (el2_enabled && hcr.ticab) {
1449  return inst.generateTrap(EL2);
1450  } else {
1451  return NoFault;
1452  }
1453 }
1454 
1455 Fault
1456 faultCtrEL0(const MiscRegLUTEntry &entry,
1457  ThreadContext *tc, const MiscRegOp64 &inst)
1458 {
1459  const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1460  const SCTLR sctlr2 = tc->readMiscReg(MISCREG_SCTLR_EL2);
1461  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1462 
1463  const bool el2_enabled = EL2Enabled(tc);
1464  const bool in_host = hcr.e2h && hcr.tge;
1465  if (!(el2_enabled && in_host) && !sctlr.uct) {
1466  if (el2_enabled && hcr.tge) {
1467  return inst.generateTrap(EL2);
1468  } else {
1469  return inst.generateTrap(EL1);
1470  }
1471  } else if (el2_enabled && !in_host && hcr.tid2) {
1472  return inst.generateTrap(EL2);
1473  } else if (el2_enabled && in_host && !sctlr2.uct) {
1474  return inst.generateTrap(EL2);
1475  } else {
1476  return NoFault;
1477  }
1478 }
1479 
1480 Fault
1481 faultMdccsrEL0(const MiscRegLUTEntry &entry,
1482  ThreadContext *tc, const MiscRegOp64 &inst)
1483 {
1484  const DBGDS32 mdscr = tc->readMiscReg(MISCREG_MDSCR_EL1);
1485  const HDCR mdcr_el2 = tc->readMiscReg(MISCREG_MDCR_EL2);
1486  const HDCR mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
1487 
1488  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1489  const bool el2_enabled = EL2Enabled(tc);
1490  if (mdscr.tdcc) {
1491  if (el2_enabled && hcr.tge) {
1492  return inst.generateTrap(EL2);
1493  } else {
1494  return inst.generateTrap(EL1);
1495  }
1496  } else if (el2_enabled && mdcr_el2.tdcc) {
1497  return inst.generateTrap(EL2);
1498  } else if (el2_enabled && (hcr.tge || (mdcr_el2.tde || mdcr_el2.tda))) {
1499  return inst.generateTrap(EL2);
1500  } else if (ArmSystem::haveEL(tc, EL3) && (mdcr_el3.tdcc || mdcr_el3.tda)) {
1501  return inst.generateTrap(EL3);
1502  } else {
1503  return NoFault;
1504  }
1505 }
1506 
1507 Fault
1508 faultMdccsrEL1(const MiscRegLUTEntry &entry,
1509  ThreadContext *tc, const MiscRegOp64 &inst)
1510 {
1511  const HDCR mdcr_el2 = tc->readMiscReg(MISCREG_MDCR_EL2);
1512  const HDCR mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
1513 
1514  const bool el2_enabled = EL2Enabled(tc);
1515  if (el2_enabled && mdcr_el2.tdcc) {
1516  return inst.generateTrap(EL2);
1517  } else if (el2_enabled && (mdcr_el2.tde || mdcr_el2.tda)) {
1518  return inst.generateTrap(EL2);
1519  } else if (ArmSystem::haveEL(tc, EL3) && (mdcr_el3.tdcc || mdcr_el3.tda)) {
1520  return inst.generateTrap(EL3);
1521  } else {
1522  return NoFault;
1523  }
1524 }
1525 
1526 Fault
1527 faultMdccsrEL2(const MiscRegLUTEntry &entry,
1528  ThreadContext *tc, const MiscRegOp64 &inst)
1529 {
1530  const HDCR mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
1531  if (ArmSystem::haveEL(tc, EL3) && (mdcr_el3.tdcc || mdcr_el3.tda)) {
1532  return inst.generateTrap(EL3);
1533  } else {
1534  return NoFault;
1535  }
1536 }
1537 
1538 Fault
1539 faultDebugEL1(const MiscRegLUTEntry &entry,
1540  ThreadContext *tc, const MiscRegOp64 &inst)
1541 {
1542  const HDCR mdcr_el2 = tc->readMiscReg(MISCREG_MDCR_EL2);
1543  const HDCR mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
1544 
1545  const bool el2_enabled = EL2Enabled(tc);
1546  if (el2_enabled && (mdcr_el2.tde || mdcr_el2.tda)) {
1547  return inst.generateTrap(EL2);
1548  } else if (ArmSystem::haveEL(tc, EL3) && mdcr_el3.tda) {
1549  return inst.generateTrap(EL3);
1550  } else {
1551  return NoFault;
1552  }
1553 }
1554 
1555 Fault
1556 faultDebugEL2(const MiscRegLUTEntry &entry,
1557  ThreadContext *tc, const MiscRegOp64 &inst)
1558 {
1559  const HDCR mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
1560  if (ArmSystem::haveEL(tc, EL3) && mdcr_el3.tda) {
1561  return inst.generateTrap(EL3);
1562  } else {
1563  return NoFault;
1564  }
1565 }
1566 
1567 Fault
1568 faultZcrEL1(const MiscRegLUTEntry &entry,
1569  ThreadContext *tc, const MiscRegOp64 &inst)
1570 {
1571  const CPACR cpacr_el1 = tc->readMiscReg(MISCREG_CPACR_EL1);
1572  const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
1573  const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1574 
1575  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1576  const bool el2_enabled = EL2Enabled(tc);
1577  if (!(cpacr_el1.zen & 0x1)) {
1578  return inst.generateTrap(EL1, ExceptionClass::TRAPPED_SVE, 0);
1579  } else if (el2_enabled && !hcr.e2h && cptr_el2.tz) {
1580  return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SVE, 0);
1581  } else if (el2_enabled && hcr.e2h && !(cptr_el2.zen & 0x1)) {
1582  return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SVE, 0);
1583  } else if (ArmSystem::haveEL(tc, EL3) && !cptr_el3.ez) {
1584  return inst.generateTrap(EL3, ExceptionClass::TRAPPED_SVE, 0);
1585  } else {
1586  return NoFault;
1587  }
1588 }
1589 
1590 Fault
1591 faultZcrEL2(const MiscRegLUTEntry &entry,
1592  ThreadContext *tc, const MiscRegOp64 &inst)
1593 {
1594  const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
1595  const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1596 
1597  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1598  if (!hcr.e2h && cptr_el2.tz) {
1599  return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SVE, 0);
1600  } else if (hcr.e2h && !(cptr_el2.zen & 0x1)) {
1601  return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SVE, 0);
1602  } else if (ArmSystem::haveEL(tc, EL3) && !cptr_el3.ez) {
1603  return inst.generateTrap(EL3, ExceptionClass::TRAPPED_SVE, 0);
1604  } else {
1605  return NoFault;
1606  }
1607 }
1608 
1609 Fault
1610 faultZcrEL3(const MiscRegLUTEntry &entry,
1611  ThreadContext *tc, const MiscRegOp64 &inst)
1612 {
1613  const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1614  if (!cptr_el3.ez) {
1615  return inst.generateTrap(EL3, ExceptionClass::TRAPPED_SVE, 0);
1616  } else {
1617  return NoFault;
1618  }
1619 }
1620 
1621 Fault
1622 faultGicv3(const MiscRegLUTEntry &entry,
1623  ThreadContext *tc, const MiscRegOp64 &inst)
1624 {
1625  auto gic = static_cast<ArmSystem*>(tc->getSystemPtr())->getGIC();
1626  if (!gic->supportsVersion(BaseGic::GicVersion::GIC_V3)) {
1627  return inst.undefined();
1628  } else {
1629  return NoFault;
1630  }
1631 }
1632 
1633 Fault
1634 faultIccSgiEL1(const MiscRegLUTEntry &entry,
1635  ThreadContext *tc, const MiscRegOp64 &inst)
1636 {
1637  if (auto fault = faultGicv3(entry, tc, inst); fault != NoFault) {
1638  return fault;
1639  }
1640 
1641  const Gicv3CPUInterface::ICH_HCR_EL2 ich_hcr =
1642  tc->readMiscReg(MISCREG_ICH_HCR_EL2);
1643  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1644  const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
1645  if (EL2Enabled(tc) && (hcr.fmo || hcr.imo || ich_hcr.TC)) {
1646  return inst.generateTrap(EL2);
1647  } else if (ArmSystem::haveEL(tc, EL3) && scr.irq && scr.fiq) {
1648  return inst.generateTrap(EL3);
1649  } else {
1650  return NoFault;
1651  }
1652 }
1653 
1654 Fault
1655 faultIccSgiEL2(const MiscRegLUTEntry &entry,
1656  ThreadContext *tc, const MiscRegOp64 &inst)
1657 {
1658  if (auto fault = faultGicv3(entry, tc, inst); fault != NoFault) {
1659  return fault;
1660  }
1661 
1662  const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
1663  if (ArmSystem::haveEL(tc, EL3) && scr.irq && scr.fiq) {
1664  return inst.generateTrap(EL3);
1665  } else {
1666  return NoFault;
1667  }
1668 }
1669 
1670 Fault
1671 faultCpacrEL1(const MiscRegLUTEntry &entry,
1672  ThreadContext *tc, const MiscRegOp64 &inst)
1673 {
1674  const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
1675  const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1676  if (EL2Enabled(tc) && cptr_el2.tcpac) {
1677  return inst.generateTrap(EL2);
1678  } else if (ArmSystem::haveEL(tc, EL3) && cptr_el3.tcpac) {
1679  return inst.generateTrap(EL3);
1680  } else {
1681  return NoFault;
1682  }
1683 }
1684 
1685 Fault
1686 faultCpacrEL2(const MiscRegLUTEntry &entry,
1687  ThreadContext *tc, const MiscRegOp64 &inst)
1688 {
1689  const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1690  if (ArmSystem::haveEL(tc, EL3) && cptr_el3.tcpac) {
1691  return inst.generateTrap(EL3);
1692  } else {
1693  return NoFault;
1694  }
1695 }
1696 
1697 Fault
1698 faultCpacrVheEL2(const MiscRegLUTEntry &entry,
1699  ThreadContext *tc, const MiscRegOp64 &inst)
1700 {
1701  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1702  if (hcr.e2h) {
1703  return faultCpacrEL2(entry, tc, inst);
1704  } else {
1705  return inst.undefined();
1706  }
1707 }
1708 
1709 #define HCR_TRAP(bitfield) [] (const MiscRegLUTEntry &entry, \
1710  ThreadContext *tc, const MiscRegOp64 &inst) -> Fault \
1711 { \
1712  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); \
1713  if (EL2Enabled(tc) && hcr.bitfield) { \
1714  return inst.generateTrap(EL2); \
1715  } else { \
1716  return NoFault; \
1717  } \
1718 }
1719 
1720 Fault
1721 faultPauthEL1(const MiscRegLUTEntry &entry,
1722  ThreadContext *tc, const MiscRegOp64 &inst)
1723 {
1724  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1725  const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
1726  if (EL2Enabled(tc) && !hcr.apk) {
1727  return inst.generateTrap(EL2);
1728  } else if (ArmSystem::haveEL(tc, EL3) && !scr.apk) {
1729  return inst.generateTrap(EL3);
1730  } else {
1731  return NoFault;
1732  }
1733 }
1734 
1735 Fault
1736 faultPauthEL2(const MiscRegLUTEntry &entry,
1737  ThreadContext *tc, const MiscRegOp64 &inst)
1738 {
1739  const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
1740  if (ArmSystem::haveEL(tc, EL3) && !scr.apk) {
1741  return inst.generateTrap(EL3);
1742  } else {
1743  return NoFault;
1744  }
1745 }
1746 
1747 Fault
1748 faultGenericTimerEL0(const MiscRegLUTEntry &entry,
1749  ThreadContext *tc, const MiscRegOp64 &inst)
1750 {
1751  const bool el2_enabled = EL2Enabled(tc);
1752  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1753  const bool in_host = el2_enabled && hcr.e2h && hcr.tge;
1754  const CNTKCTL cntkctl_el1 = tc->readMiscReg(MISCREG_CNTKCTL_EL1);
1755  const CNTHCTL_E2H cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1756  if (!(in_host) && !cntkctl_el1.el0pcten && !cntkctl_el1.el0vcten) {
1757  if (el2_enabled && hcr.tge)
1758  return inst.generateTrap(EL2);
1759  else
1760  return inst.generateTrap(EL1);
1761  } else if (in_host && !cnthctl_el2.el0pcten && !cnthctl_el2.el0vcten) {
1762  return inst.generateTrap(EL2);
1763  } else {
1764  return NoFault;
1765  }
1766 }
1767 
1768 Fault
1769 faultCntpctEL0(const MiscRegLUTEntry &entry,
1770  ThreadContext *tc, const MiscRegOp64 &inst)
1771 {
1772  const bool el2_enabled = EL2Enabled(tc);
1773  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1774  const bool in_host = el2_enabled && hcr.e2h && hcr.tge;
1775  const CNTKCTL cntkctl_el1 = tc->readMiscReg(MISCREG_CNTKCTL_EL1);
1776  const RegVal cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1777  if (!(in_host) && !cntkctl_el1.el0pcten) {
1778  if (el2_enabled && hcr.tge)
1779  return inst.generateTrap(EL2);
1780  else
1781  return inst.generateTrap(EL1);
1782  } else if (el2_enabled && !hcr.e2h &&
1783  !static_cast<CNTHCTL>(cnthctl_el2).el1pcten) {
1784  return inst.generateTrap(EL2);
1785  } else if (el2_enabled && hcr.e2h && !hcr.tge &&
1786  !static_cast<CNTHCTL_E2H>(cnthctl_el2).el1pcten) {
1787  return inst.generateTrap(EL2);
1788  } else if (in_host &&
1789  !static_cast<CNTHCTL_E2H>(cnthctl_el2).el0pcten) {
1790  return inst.generateTrap(EL2);
1791  } else {
1792  return NoFault;
1793  }
1794 }
1795 
1796 Fault
1797 faultCntpctEL1(const MiscRegLUTEntry &entry,
1798  ThreadContext *tc, const MiscRegOp64 &inst)
1799 {
1800  const bool el2_enabled = EL2Enabled(tc);
1801  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1802  const RegVal cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1803  if (el2_enabled && hcr.e2h &&
1804  !static_cast<CNTHCTL_E2H>(cnthctl_el2).el1pcten) {
1805  return inst.generateTrap(EL2);
1806  } else if (el2_enabled && !hcr.e2h &&
1807  !static_cast<CNTHCTL>(cnthctl_el2).el1pcten) {
1808  return inst.generateTrap(EL2);
1809  } else {
1810  return NoFault;
1811  }
1812 }
1813 
1814 Fault
1815 faultCntvctEL0(const MiscRegLUTEntry &entry,
1816  ThreadContext *tc, const MiscRegOp64 &inst)
1817 {
1818  const bool el2_enabled = EL2Enabled(tc);
1819  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1820  const bool in_host = el2_enabled && hcr.e2h && hcr.tge;
1821  const CNTKCTL cntkctl_el1 = tc->readMiscReg(MISCREG_CNTKCTL_EL1);
1822  const CNTHCTL_E2H cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1823  if (!(in_host) && !cntkctl_el1.el0vcten) {
1824  if (el2_enabled && hcr.tge)
1825  return inst.generateTrap(EL2);
1826  else
1827  return inst.generateTrap(EL1);
1828  } else if (in_host && !cnthctl_el2.el0vcten) {
1829  return inst.generateTrap(EL2);
1830  } else if (el2_enabled && !(hcr.e2h && hcr.tge) && cnthctl_el2.el1tvct) {
1831  return inst.generateTrap(EL2);
1832  } else {
1833  return NoFault;
1834  }
1835 }
1836 
1837 Fault
1838 faultCntvctEL1(const MiscRegLUTEntry &entry,
1839  ThreadContext *tc, const MiscRegOp64 &inst)
1840 {
1841  const CNTHCTL cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1842  if (EL2Enabled(tc) && cnthctl_el2.el1tvct) {
1843  return inst.generateTrap(EL2);
1844  } else {
1845  return NoFault;
1846  }
1847 }
1848 
1849 //TODO: See faultCntpctEL0
1850 Fault
1851 faultCntpCtlEL0(const MiscRegLUTEntry &entry,
1852  ThreadContext *tc, const MiscRegOp64 &inst)
1853 {
1854  const bool el2_enabled = EL2Enabled(tc);
1855  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1856  const bool in_host = el2_enabled && hcr.e2h && hcr.tge;
1857  const CNTKCTL cntkctl_el1 = tc->readMiscReg(MISCREG_CNTKCTL_EL1);
1858  const RegVal cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1859  if (!(in_host) && !cntkctl_el1.el0pten) {
1860  if (el2_enabled && hcr.tge)
1861  return inst.generateTrap(EL2);
1862  else
1863  return inst.generateTrap(EL1);
1864  } else if (el2_enabled && !hcr.e2h &&
1865  !static_cast<CNTHCTL>(cnthctl_el2).el1pcen) {
1866  return inst.generateTrap(EL2);
1867  } else if (el2_enabled && hcr.e2h && !hcr.tge &&
1868  !static_cast<CNTHCTL_E2H>(cnthctl_el2).el1pten) {
1869  return inst.generateTrap(EL2);
1870  } else if (in_host &&
1871  !static_cast<CNTHCTL_E2H>(cnthctl_el2).el0pten) {
1872  return inst.generateTrap(EL2);
1873  } else {
1874  return NoFault;
1875  }
1876 }
1877 
1878 Fault
1879 faultCntpCtlEL1(const MiscRegLUTEntry &entry,
1880  ThreadContext *tc, const MiscRegOp64 &inst)
1881 {
1882  const bool el2_enabled = EL2Enabled(tc);
1883  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1884  const RegVal cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1885  if (el2_enabled && !hcr.e2h &&
1886  !static_cast<CNTHCTL>(cnthctl_el2).el1pcen) {
1887  return inst.generateTrap(EL2);
1888  } else if (el2_enabled && hcr.e2h &&
1889  !static_cast<CNTHCTL_E2H>(cnthctl_el2).el1pten) {
1890  return inst.generateTrap(EL2);
1891  } else {
1892  return NoFault;
1893  }
1894 }
1895 
1896 // TODO: see faultCntvctEL0
1897 Fault
1898 faultCntvCtlEL0(const MiscRegLUTEntry &entry,
1899  ThreadContext *tc, const MiscRegOp64 &inst)
1900 {
1901  const bool el2_enabled = EL2Enabled(tc);
1902  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1903  const bool in_host = el2_enabled && hcr.e2h && hcr.tge;
1904  const CNTKCTL cntkctl_el1 = tc->readMiscReg(MISCREG_CNTKCTL_EL1);
1905  const CNTHCTL_E2H cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1906  if (!(in_host) && !cntkctl_el1.el0vten) {
1907  if (el2_enabled && hcr.tge)
1908  return inst.generateTrap(EL2);
1909  else
1910  return inst.generateTrap(EL1);
1911  } else if (in_host && !cnthctl_el2.el0vten) {
1912  return inst.generateTrap(EL2);
1913  } else if (el2_enabled && !(hcr.e2h && hcr.tge) && cnthctl_el2.el1tvt) {
1914  return inst.generateTrap(EL2);
1915  } else {
1916  return NoFault;
1917  }
1918 }
1919 
1920 Fault
1921 faultCntvCtlEL1(const MiscRegLUTEntry &entry,
1922  ThreadContext *tc, const MiscRegOp64 &inst)
1923 {
1924  const CNTHCTL cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1925  if (EL2Enabled(tc) && cnthctl_el2.el1tvt) {
1926  return inst.generateTrap(EL2);
1927  } else {
1928  return NoFault;
1929  }
1930 }
1931 
1932 Fault
1933 faultCntpsCtlEL1(const MiscRegLUTEntry &entry,
1934  ThreadContext *tc, const MiscRegOp64 &inst)
1935 {
1936  const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
1937  if (ArmSystem::haveEL(tc, EL3) && !scr.ns) {
1938  if (scr.eel2)
1939  return inst.undefined();
1940  else if (!scr.st)
1941  return inst.generateTrap(EL3);
1942  else
1943  return NoFault;
1944  } else {
1945  return inst.undefined();
1946  }
1947 }
1948 
1949 Fault
1950 faultUnimplemented(const MiscRegLUTEntry &entry,
1951  ThreadContext *tc, const MiscRegOp64 &inst)
1952 {
1953  if (entry.info[MISCREG_WARN_NOT_FAIL]) {
1954  return NoFault;
1955  } else {
1956  return inst.undefined();
1957  }
1958 }
1959 
1960 Fault
1961 faultImpdefUnimplEL1(const MiscRegLUTEntry &entry,
1962  ThreadContext *tc, const MiscRegOp64 &inst)
1963 {
1964  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1965  if (EL2Enabled(tc) && hcr.tidcp) {
1966  return inst.generateTrap(EL2);
1967  } else {
1968  return faultUnimplemented(entry, tc, inst);
1969  }
1970 }
1971 
1972 }
1973 
1975 decodeAArch64SysReg(unsigned op0, unsigned op1,
1976  unsigned crn, unsigned crm,
1977  unsigned op2)
1978 {
1979  MiscRegNum64 sys_reg(op0, op1, crn, crm, op2);
1980  return decodeAArch64SysReg(sys_reg);
1981 }
1982 
1985 {
1986  auto it = miscRegNumToIdx.find(sys_reg);
1987  if (it != miscRegNumToIdx.end()) {
1988  return it->second;
1989  } else {
1990  // Check for a pseudo register before returning MISCREG_UNKNOWN
1991  if ((sys_reg.op0 == 1 || sys_reg.op0 == 3) &&
1992  (sys_reg.crn == 11 || sys_reg.crn == 15)) {
1993  return MISCREG_IMPDEF_UNIMPL;
1994  } else {
1995  return MISCREG_UNKNOWN;
1996  }
1997  }
1998 }
1999 
2002 {
2003  if (auto it = idxToMiscRegNum.find(misc_reg);
2004  it != idxToMiscRegNum.end()) {
2005  return it->second;
2006  } else {
2007  panic("Invalid MiscRegIndex: %d\n", misc_reg);
2008  }
2009 }
2010 
2011 Fault
2013  const MiscRegOp64 &inst, ExceptionLevel el)
2014 {
2015  return !inst.miscRead() ? faultWrite[el](*this, tc, inst) :
2016  faultRead[el](*this, tc, inst);
2017 }
2018 
2019 template <MiscRegInfo Sec, MiscRegInfo NonSec>
2020 Fault
2022  ThreadContext *tc, const MiscRegOp64 &inst)
2023 {
2024  if (isSecureBelowEL3(tc) ? entry.info[Sec] : entry.info[NonSec]) {
2025  return NoFault;
2026  } else {
2027  return inst.undefined();
2028  }
2029 }
2030 
2031 static Fault
2033  ThreadContext *tc, const MiscRegOp64 &inst)
2034 {
2035  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
2036  if (hcr.e2h) {
2037  return NoFault;
2038  } else {
2039  return inst.undefined();
2040  }
2041 }
2042 
2043 static Fault
2045  ThreadContext *tc, const MiscRegOp64 &inst)
2046 {
2047  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
2048  const bool el2_host = EL2Enabled(tc) && hcr.e2h;
2049  if (el2_host) {
2050  return NoFault;
2051  } else {
2052  return inst.undefined();
2053  }
2054 }
2055 
2058 {
2059  switch (FullSystem ? sys->highestEL() : EL1) {
2060  case EL0:
2061  case EL1: priv(); break;
2062  case EL2: hyp(); break;
2063  case EL3: mon(); break;
2064  }
2065  return *this;
2066 }
2067 
2068 
2069 void
2071 {
2072  // the MiscReg metadata tables are shared across all instances of the
2073  // ISA object, so there's no need to initialize them multiple times.
2074  static bool completed = false;
2075  if (completed)
2076  return;
2077 
2078  // This boolean variable specifies if the system is running in aarch32 at
2079  // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
2080  // is running in aarch64 (aarch32EL3 = false)
2081  bool aarch32EL3 = release->has(ArmExtension::SECURITY) && !highestELIs64;
2082 
2083  // Set Privileged Access Never on taking an exception to EL1 (Arm 8.1+),
2084  // unsupported
2085  bool SPAN = false;
2086 
2087  // Implicit error synchronization event enable (Arm 8.2+), unsupported
2088  bool IESB = false;
2089 
2090  // Load Multiple and Store Multiple Atomicity and Ordering (Arm 8.2+),
2091  // unsupported
2092  bool LSMAOE = false;
2093 
2094  // No Trap Load Multiple and Store Multiple (Arm 8.2+), unsupported
2095  bool nTLSMD = false;
2096 
2097  // Pointer authentication (Arm 8.3+), unsupported
2098  bool EnDA = true; // using APDAKey_EL1 key of instr addrs in ELs 0,1
2099  bool EnDB = true; // using APDBKey_EL1 key of instr addrs in ELs 0,1
2100  bool EnIA = true; // using APIAKey_EL1 key of instr addrs in ELs 0,1
2101  bool EnIB = true; // using APIBKey_EL1 key of instr addrs in ELs 0,1
2102 
2103  const bool vhe_implemented = release->has(ArmExtension::FEAT_VHE);
2104  const bool sel2_implemented = release->has(ArmExtension::FEAT_SEL2);
2105 
2106 
2121  .allPrivileges();
2123  .allPrivileges();
2125  .allPrivileges();
2127  .allPrivileges();
2129  .allPrivileges();
2131  .allPrivileges();
2133  .allPrivileges();
2135  .allPrivileges();
2137  .allPrivileges();
2139  .allPrivileges();
2141  .allPrivileges();
2143  .allPrivileges();
2145  .allPrivileges();
2147  .allPrivileges();
2149  .allPrivileges();
2150 
2151  // Helper registers
2153  .allPrivileges();
2155  .allPrivileges();
2157  .allPrivileges();
2159  .allPrivileges();
2161  .allPrivileges();
2163  .allPrivileges();
2165  .mutex()
2166  .banked();
2168  .mutex()
2169  .privSecure(!aarch32EL3)
2170  .bankedChild();
2172  .mutex()
2173  .bankedChild();
2175  .mutex()
2176  .banked();
2178  .mutex()
2179  .privSecure(!aarch32EL3)
2180  .bankedChild();
2182  .mutex()
2183  .bankedChild();
2185  .mutex();
2187  .allPrivileges();
2189  .allPrivileges();
2192 
2193  // AArch32 CP14 registers
2199  .unimplemented()
2200  .allPrivileges();
2202  .unimplemented()
2203  .allPrivileges();
2205  .unimplemented()
2206  .allPrivileges();
2208  .unimplemented()
2209  .allPrivileges();
2213  .unimplemented()
2214  .allPrivileges();
2216  .allPrivileges();
2218  .unimplemented()
2219  .allPrivileges();
2221  .unimplemented()
2222  .allPrivileges();
2352  .unimplemented()
2393  .unimplemented()
2394  .warnNotFail()
2395  .allPrivileges();
2397  .unimplemented()
2398  .allPrivileges();
2400  .unimplemented()
2403  .unimplemented()
2404  .allPrivileges();
2406  .unimplemented()
2407  .allPrivileges();
2409  .unimplemented()
2412  .unimplemented()
2415  .unimplemented()
2420  .unimplemented()
2421  .allPrivileges();
2423  .allPrivileges();
2425  .allPrivileges();
2427  .allPrivileges();
2429  .allPrivileges();
2430 
2431  // AArch32 CP15 registers
2443  .unimplemented()
2444  .warnNotFail()
2485  .banked();
2487  .bankedChild()
2488  .privSecure(!aarch32EL3)
2491  .bankedChild()
2492  .secure().exceptUserMode();
2494  .hyp().monNonSecure();
2496  .hyp().monNonSecure();
2498  .banked()
2499  // readMiscRegNoEffect() uses this metadata
2500  // despite using children (below) as backing store
2501  .res0(0x8d22c600)
2502  .res1(0x00400800 | (SPAN ? 0 : 0x800000)
2503  | (LSMAOE ? 0 : 0x10)
2504  | (nTLSMD ? 0 : 0x8));
2506  .bankedChild()
2507  .privSecure(!aarch32EL3)
2510  .bankedChild()
2511  .secure().exceptUserMode();
2513  .banked();
2515  .bankedChild()
2516  .privSecure(!aarch32EL3)
2519  .bankedChild()
2520  .secure().exceptUserMode();
2524  .mon();
2526  .mon().secure().exceptUserMode()
2527  .res0(0xff40) // [31:16], [6]
2528  .res1(0x0030); // [5:4]
2530  .mon();
2534  .hyp().monNonSecure()
2535  .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
2536  | (IESB ? 0 : 0x200000)
2537  | (EnDA ? 0 : 0x8000000)
2538  | (EnIB ? 0 : 0x40000000)
2539  | (EnIA ? 0 : 0x80000000))
2540  .res1(0x30c50830);
2542  .hyp().monNonSecure();
2544  .hyp().monNonSecure()
2545  .res0(0x90000000);
2547  .hyp().monNonSecure()
2548  .res0(0xffa9ff8c);
2550  .hyp().monNonSecure();
2552  .hyp().monNonSecure();
2554  .hyp().monNonSecure();
2556  .unimplemented()
2557  .warnNotFail()
2558  .hyp().monNonSecure();
2560  .banked();
2562  .bankedChild()
2563  .privSecure(!aarch32EL3)
2566  .bankedChild()
2567  .secure().exceptUserMode();
2569  .banked();
2571  .bankedChild()
2572  .privSecure(!aarch32EL3)
2575  .bankedChild()
2576  .secure().exceptUserMode();
2578  .banked();
2580  .bankedChild()
2581  .privSecure(!aarch32EL3)
2584  .bankedChild()
2585  .secure().exceptUserMode();
2587  .hyp().monNonSecure();
2589  .hyp().monNonSecure();
2591  .banked();
2593  .bankedChild()
2594  .privSecure(!aarch32EL3)
2597  .bankedChild()
2598  .secure().exceptUserMode();
2600  .banked();
2602  .bankedChild()
2603  .privSecure(!aarch32EL3)
2606  .bankedChild()
2607  .secure().exceptUserMode();
2609  .banked();
2611  .bankedChild()
2612  .privSecure(!aarch32EL3)
2615  .bankedChild()
2616  .secure().exceptUserMode();
2618  .unimplemented()
2619  .warnNotFail()
2620  .banked();
2622  .unimplemented()
2623  .warnNotFail()
2624  .bankedChild()
2625  .privSecure(!aarch32EL3)
2628  .unimplemented()
2629  .warnNotFail()
2630  .bankedChild()
2631  .secure().exceptUserMode();
2633  .unimplemented()
2634  .warnNotFail()
2635  .banked();
2637  .unimplemented()
2638  .warnNotFail()
2639  .bankedChild()
2640  .privSecure(!aarch32EL3)
2643  .unimplemented()
2644  .warnNotFail()
2645  .bankedChild()
2646  .secure().exceptUserMode();
2648  .hyp().monNonSecure();
2650  .hyp().monNonSecure();
2652  .hyp().monNonSecure();
2654  .banked();
2656  .bankedChild()
2657  .privSecure(!aarch32EL3)
2660  .bankedChild()
2661  .secure().exceptUserMode();
2663  .banked();
2665  .bankedChild()
2666  .privSecure(!aarch32EL3)
2669  .bankedChild()
2670  .secure().exceptUserMode();
2672  .hyp().monNonSecure();
2674  .hyp().monNonSecure();
2676  .hyp().monNonSecure();
2678  .unimplemented()
2679  .warnNotFail()
2680  .writes(1).exceptUserMode();
2682  .unimplemented()
2683  .warnNotFail()
2684  .writes(1).exceptUserMode();
2686  .banked();
2688  .bankedChild()
2689  .privSecure(!aarch32EL3)
2692  .bankedChild()
2693  .secure().exceptUserMode();
2695  .writes(1).exceptUserMode();
2697  .unimplemented()
2698  .warnNotFail()
2699  .writes(1).exceptUserMode();
2701  .writes(1);
2703  .unimplemented()
2704  .warnNotFail()
2705  .writes(1).exceptUserMode();
2707  .unimplemented()
2708  .warnNotFail()
2709  .writes(1).exceptUserMode();
2711  .unimplemented()
2712  .warnNotFail()
2713  .writes(1).exceptUserMode();
2715  .unimplemented()
2716  .warnNotFail()
2717  .writes(1).exceptUserMode();
2719  .writes(1).exceptUserMode();
2721  .writes(1).exceptUserMode();
2723  .writes(1).exceptUserMode();
2725  .writes(1).exceptUserMode();
2735  .writes(1).exceptUserMode();
2737  .unimplemented()
2738  .warnNotFail()
2739  .writes(1).exceptUserMode();
2741  .writes(1);
2743  .writes(1);
2745  .unimplemented()
2746  .warnNotFail()
2747  .writes(1).exceptUserMode();
2749  .unimplemented()
2750  .warnNotFail()
2751  .writes(1).exceptUserMode();
2753  .unimplemented()
2754  .warnNotFail()
2755  .writes(1).exceptUserMode();
2761  .writes(1).exceptUserMode();
2763  .writes(1).exceptUserMode();
2765  .writes(1).exceptUserMode();
2767  .writes(1).exceptUserMode();
2769  .writes(1).exceptUserMode();
2771  .writes(1).exceptUserMode();
2773  .writes(1).exceptUserMode();
2775  .writes(1).exceptUserMode();
2777  .writes(1).exceptUserMode();
2779  .writes(1).exceptUserMode();
2781  .writes(1).exceptUserMode();
2783  .writes(1).exceptUserMode();
2785  .writes(1).exceptUserMode();
2787  .writes(1).exceptUserMode();
2789  .writes(1).exceptUserMode();
2791  .writes(1).exceptUserMode();
2793  .writes(1).exceptUserMode();
2795  .writes(1).exceptUserMode();
2821  .allPrivileges();
2823  .allPrivileges();
2825  .allPrivileges();
2827  .allPrivileges();
2829  .allPrivileges();
2831  .allPrivileges();
2833  .allPrivileges();
2835  .allPrivileges();
2837  .allPrivileges();
2839  .allPrivileges();
2841  .allPrivileges();
2843  .allPrivileges();
2851  .unimplemented()
2852  .allPrivileges();
2856  .unimplemented()
2859  .banked();
2861  .bankedChild()
2862  .privSecure(!aarch32EL3)
2865  .bankedChild()
2866  .secure().exceptUserMode();
2868  .banked();
2870  .bankedChild()
2871  .privSecure(!aarch32EL3)
2874  .bankedChild()
2875  .secure().exceptUserMode();
2877  .banked();
2879  .bankedChild()
2880  .privSecure(!aarch32EL3)
2883  .bankedChild()
2884  .secure().exceptUserMode();
2886  .banked();
2888  .bankedChild()
2889  .privSecure(!aarch32EL3)
2892  .bankedChild()
2893  .secure().exceptUserMode();
2895  .banked();
2897  .bankedChild()
2898  .privSecure(!aarch32EL3)
2901  .bankedChild()
2902  .secure().exceptUserMode();
2904  .banked();
2906  .bankedChild()
2907  .privSecure(!aarch32EL3)
2910  .bankedChild()
2911  .secure().exceptUserMode();
2913  .hyp().monNonSecure();
2915  .hyp().monNonSecure();
2917  .unimplemented()
2918  .warnNotFail()
2919  .hyp().monNonSecure();
2921  .unimplemented()
2922  .warnNotFail()
2923  .hyp().monNonSecure();
2925  .banked();
2927  .bankedChild()
2928  .privSecure(!aarch32EL3)
2931  .bankedChild()
2932  .secure().exceptUserMode();
2934  .mon().secure()
2937  .exceptUserMode();
2939  .unimplemented()
2940  .mon().secure().exceptUserMode();
2944  .hyp().monNonSecure()
2945  .res0(0x1f);
2947  .unimplemented()
2948  .warnNotFail()
2951  .banked();
2953  .bankedChild()
2954  .privSecure(!aarch32EL3)
2957  .bankedChild()
2958  .secure().exceptUserMode();
2960  .banked();
2962  .bankedChild()
2963  .allPrivileges()
2964  .privSecure(!aarch32EL3)
2965  .monSecure(0);
2967  .bankedChild()
2968  .secure();
2970  .banked();
2972  .bankedChild()
2973  .allPrivileges()
2975  .privSecure(!aarch32EL3)
2976  .monSecure(0);
2978  .bankedChild()
2979  .secure().userSecureWrite(0);
2981  .banked();
2983  .bankedChild()
2985  .privSecure(!aarch32EL3);
2987  .bankedChild()
2988  .secure().exceptUserMode();
2990  .hyp().monNonSecure();
2991  // BEGIN Generic Timer (AArch32)
2993  .reads(1)
2994  .highest(system)
2995  .privSecureWrite(aarch32EL3);
2997  .unverifiable()
2998  .reads(1);
3000  .unverifiable()
3001  .reads(1);
3003  .banked();
3005  .bankedChild()
3006  .nonSecure()
3007  .privSecure(!aarch32EL3)
3008  .userSecureRead(!aarch32EL3)
3009  .userSecureWrite(!aarch32EL3)
3010  .res0(0xfffffff8);
3012  .bankedChild()
3013  .secure()
3014  .privSecure(aarch32EL3)
3015  .res0(0xfffffff8);
3017  .banked();
3019  .bankedChild()
3020  .nonSecure()
3021  .privSecure(!aarch32EL3)
3022  .userSecureRead(!aarch32EL3)
3023  .userSecureWrite(!aarch32EL3);
3025  .bankedChild()
3026  .secure()
3027  .privSecure(aarch32EL3);
3029  .banked();
3031  .bankedChild()
3032  .nonSecure()
3033  .privSecure(!aarch32EL3)
3034  .userSecureRead(!aarch32EL3)
3035  .userSecureWrite(!aarch32EL3);
3037  .bankedChild()
3038  .secure()
3039  .privSecure(aarch32EL3);
3041  .allPrivileges()
3042  .res0(0xfffffff8);
3044  .allPrivileges();
3046  .allPrivileges();
3048  .allPrivileges()
3049  .exceptUserMode()
3050  .res0(0xfffdfc00);
3052  .monNonSecure()
3053  .hyp()
3054  .res0(0xfffdff00);
3056  .monNonSecure()
3057  .hyp()
3058  .res0(0xfffffff8);
3060  .monNonSecure()
3061  .hyp();
3063  .monNonSecure()
3064  .hyp();
3066  .monNonSecure()
3067  .hyp();
3068  // END Generic Timer (AArch32)
3070  .unimplemented()
3073  .unimplemented()
3076  .unimplemented()
3079  .unimplemented()
3082  .unimplemented()
3085  .unimplemented()
3088  .unimplemented()
3091  .unimplemented()
3094  .unimplemented()
3097  .unimplemented()
3098  .writes(1).exceptUserMode();
3100  .unimplemented()
3103  .unimplemented()
3106  .hyp().monNonSecure();
3108  .hyp().monNonSecure();
3110  .unimplemented()
3113  .unimplemented()
3114  .warnNotFail()
3116 
3117  // AArch64 registers (Op0=2);
3119  .fault(EL1, faultMdccsrEL1)
3120  .fault(EL2, faultMdccsrEL2)
3121  .allPrivileges();
3123  .allPrivileges()
3126  .allPrivileges()
3129  .allPrivileges()
3132  .allPrivileges()
3136  .fault(EL1, faultDebugEL1)
3137  .fault(EL2, faultDebugEL2)
3141  .fault(EL1, faultDebugEL1)
3142  .fault(EL2, faultDebugEL2)
3146  .fault(EL1, faultDebugEL1)
3147  .fault(EL2, faultDebugEL2)
3151  .fault(EL1, faultDebugEL1)
3152  .fault(EL2, faultDebugEL2)
3156  .fault(EL1, faultDebugEL1)
3157  .fault(EL2, faultDebugEL2)
3161  .fault(EL1, faultDebugEL1)
3162  .fault(EL2, faultDebugEL2)
3166  .fault(EL1, faultDebugEL1)
3167  .fault(EL2, faultDebugEL2)
3171  .fault(EL1, faultDebugEL1)
3172  .fault(EL2, faultDebugEL2)
3176  .fault(EL1, faultDebugEL1)
3177  .fault(EL2, faultDebugEL2)
3181  .fault(EL1, faultDebugEL1)
3182  .fault(EL2, faultDebugEL2)
3186  .fault(EL1, faultDebugEL1)
3187  .fault(EL2, faultDebugEL2)
3191  .fault(EL1, faultDebugEL1)
3192  .fault(EL2, faultDebugEL2)
3196  .fault(EL1, faultDebugEL1)
3197  .fault(EL2, faultDebugEL2)
3201  .fault(EL1, faultDebugEL1)
3202  .fault(EL2, faultDebugEL2)
3206  .fault(EL1, faultDebugEL1)
3207  .fault(EL2, faultDebugEL2)
3211  .fault(EL1, faultDebugEL1)
3212  .fault(EL2, faultDebugEL2)
3216  .fault(EL1, faultDebugEL1)
3217  .fault(EL2, faultDebugEL2)
3221  .fault(EL1, faultDebugEL1)
3222  .fault(EL2, faultDebugEL2)
3226  .fault(EL1, faultDebugEL1)
3227  .fault(EL2, faultDebugEL2)
3231  .fault(EL1, faultDebugEL1)
3232  .fault(EL2, faultDebugEL2)
3236  .fault(EL1, faultDebugEL1)
3237  .fault(EL2, faultDebugEL2)
3241  .fault(EL1, faultDebugEL1)
3242  .fault(EL2, faultDebugEL2)
3246  .fault(EL1, faultDebugEL1)
3247  .fault(EL2, faultDebugEL2)
3251  .fault(EL1, faultDebugEL1)
3252  .fault(EL2, faultDebugEL2)
3256  .fault(EL1, faultDebugEL1)
3257  .fault(EL2, faultDebugEL2)
3261  .fault(EL1, faultDebugEL1)
3262  .fault(EL2, faultDebugEL2)
3266  .fault(EL1, faultDebugEL1)
3267  .fault(EL2, faultDebugEL2)
3271  .fault(EL1, faultDebugEL1)
3272  .fault(EL2, faultDebugEL2)
3276  .fault(EL1, faultDebugEL1)
3277  .fault(EL2, faultDebugEL2)
3281  .fault(EL1, faultDebugEL1)
3282  .fault(EL2, faultDebugEL2)
3286  .fault(EL1, faultDebugEL1)
3287  .fault(EL2, faultDebugEL2)
3291  .fault(EL1, faultDebugEL1)
3292  .fault(EL2, faultDebugEL2)
3296  .fault(EL1, faultDebugEL1)
3297  .fault(EL2, faultDebugEL2)
3301  .fault(EL1, faultDebugEL1)
3302  .fault(EL2, faultDebugEL2)
3306  .fault(EL1, faultDebugEL1)
3307  .fault(EL2, faultDebugEL2)
3311  .fault(EL1, faultDebugEL1)
3312  .fault(EL2, faultDebugEL2)
3316  .fault(EL1, faultDebugEL1)
3317  .fault(EL2, faultDebugEL2)
3321  .fault(EL1, faultDebugEL1)
3322  .fault(EL2, faultDebugEL2)
3326  .fault(EL1, faultDebugEL1)
3327  .fault(EL2, faultDebugEL2)
3331  .fault(EL1, faultDebugEL1)
3332  .fault(EL2, faultDebugEL2)
3336  .fault(EL1, faultDebugEL1)
3337  .fault(EL2, faultDebugEL2)
3341  .fault(EL1, faultDebugEL1)
3342  .fault(EL2, faultDebugEL2)
3346  .fault(EL1, faultDebugEL1)
3347  .fault(EL2, faultDebugEL2)
3351  .fault(EL1, faultDebugEL1)
3352  .fault(EL2, faultDebugEL2)
3356  .fault(EL1, faultDebugEL1)
3357  .fault(EL2, faultDebugEL2)
3361  .fault(EL1, faultDebugEL1)
3362  .fault(EL2, faultDebugEL2)
3366  .fault(EL1, faultDebugEL1)
3367  .fault(EL2, faultDebugEL2)
3371  .fault(EL1, faultDebugEL1)
3372  .fault(EL2, faultDebugEL2)
3376  .fault(EL1, faultDebugEL1)
3377  .fault(EL2, faultDebugEL2)
3381  .fault(EL1, faultDebugEL1)
3382  .fault(EL2, faultDebugEL2)
3386  .fault(EL1, faultDebugEL1)
3387  .fault(EL2, faultDebugEL2)
3391  .fault(EL1, faultDebugEL1)
3392  .fault(EL2, faultDebugEL2)
3396  .fault(EL1, faultDebugEL1)
3397  .fault(EL2, faultDebugEL2)
3401  .fault(EL1, faultDebugEL1)
3402  .fault(EL2, faultDebugEL2)
3406  .fault(EL1, faultDebugEL1)
3407  .fault(EL2, faultDebugEL2)
3411  .fault(EL1, faultDebugEL1)
3412  .fault(EL2, faultDebugEL2)
3416  .fault(EL1, faultDebugEL1)
3417  .fault(EL2, faultDebugEL2)
3421  .fault(EL1, faultDebugEL1)
3422  .fault(EL2, faultDebugEL2)
3426  .fault(EL1, faultDebugEL1)
3427  .fault(EL2, faultDebugEL2)
3431  .fault(EL1, faultDebugEL1)
3432  .fault(EL2, faultDebugEL2)
3436  .fault(EL1, faultDebugEL1)
3437  .fault(EL2, faultDebugEL2)
3441  .fault(EL1, faultDebugEL1)
3442  .fault(EL2, faultDebugEL2)
3446  .fault(EL1, faultDebugEL1)
3447  .fault(EL2, faultDebugEL2)
3451  .fault(EL1, faultDebugEL1)
3452  .fault(EL2, faultDebugEL2)
3455  .allPrivileges().writes(0)
3456  .faultRead(EL0, faultMdccsrEL0)
3457  .faultRead(EL1, faultMdccsrEL1)
3458  .faultRead(EL2, faultMdccsrEL2)
3461  .allPrivileges();
3463  .allPrivileges();
3465  .allPrivileges();
3467  .hyp().mon()
3468  .fault(EL2, faultDebugEL2)
3480  .allPrivileges()
3483  .allPrivileges()
3486  .allPrivileges()
3489  .allPrivileges()
3496 
3497  // AArch64 registers (Op0=1,3);
3611 
3613  .fault(EL1, faultPauthEL1)
3614  .fault(EL2, faultPauthEL2)
3617  .fault(EL1, faultPauthEL1)
3618  .fault(EL2, faultPauthEL2)
3621  .fault(EL1, faultPauthEL1)
3622  .fault(EL2, faultPauthEL2)
3625  .fault(EL1, faultPauthEL1)
3626  .fault(EL2, faultPauthEL2)
3629  .fault(EL1, faultPauthEL1)
3630  .fault(EL2, faultPauthEL2)
3633  .fault(EL1, faultPauthEL1)
3634  .fault(EL2, faultPauthEL2)
3637  .fault(EL1, faultPauthEL1)
3638  .fault(EL2, faultPauthEL2)
3641  .fault(EL1, faultPauthEL1)
3642  .fault(EL2, faultPauthEL2)
3645  .fault(EL1, faultPauthEL1)
3646  .fault(EL2, faultPauthEL2)
3649  .fault(EL1, faultPauthEL1)
3650  .fault(EL2, faultPauthEL2)
3652 
3664  .fault(EL1, HCR_TRAP(tid2))
3667  .faultRead(EL0, faultCtrEL0)
3669  .reads(1);
3671  .reads(1);
3673  .hyp().mon()
3676  .hyp().mon()
3682  .res0( 0x20440 | (EnDB ? 0 : 0x2000)
3683  | (IESB ? 0 : 0x200000)
3684  | (EnDA ? 0 : 0x8000000)
3685  | (EnIB ? 0 : 0x40000000)
3686  | (EnIA ? 0 : 0x80000000))
3687  .res1(0x500800 | (SPAN ? 0 : 0x800000)
3688  | (nTLSMD ? 0 : 0x8000000)
3689  | (LSMAOE ? 0 : 0x10000000))
3694  .res0( 0x20440 | (EnDB ? 0 : 0x2000)
3695  | (IESB ? 0 : 0x200000)
3696  | (EnDA ? 0 : 0x8000000)
3697  | (EnIB ? 0 : 0x40000000)
3698  | (EnIA ? 0 : 0x80000000))
3699  .res1(0x500800 | (SPAN ? 0 : 0x800000)
3700  | (nTLSMD ? 0 : 0x8000000)
3701  | (LSMAOE ? 0 : 0x10000000))
3705  .fault(EL1, HCR_TRAP(tacr))
3709  .fault(EL1, faultCpacrEL1)
3710  .fault(EL2, faultCpacrEL2)
3713  .fault(EL2, faultCpacrVheEL2)
3717  .hyp().mon()
3718  .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
3719  | (IESB ? 0 : 0x200000)
3720  | (EnDA ? 0 : 0x8000000)
3721  | (EnIB ? 0 : 0x40000000)
3722  | (EnIA ? 0 : 0x80000000))
3723  .res1(0x30c50830)
3726  .hyp().mon()
3729  .hyp().mon()
3732  .hyp().mon()
3733  .fault(EL2, faultDebugEL2)
3734  .mapsTo(MISCREG_HDCR);
3736  .hyp().mon()
3737  .fault(EL2, faultCpacrEL2)
3740  .hyp().mon()
3741  .mapsTo(MISCREG_HSTR);
3743  .hyp().mon()
3744  .mapsTo(MISCREG_HACR);
3746  .mon()
3747  .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
3748  | (IESB ? 0 : 0x200000)
3749  | (EnDA ? 0 : 0x8000000)
3750  | (EnIB ? 0 : 0x40000000)
3751  | (EnIA ? 0 : 0x80000000))
3752  .res1(0x30c50830);
3754  .mon();
3756  .mon()
3757  .mapsTo(MISCREG_SCR); // NAM D7-2005
3759  .mon()
3760  .mapsTo(MISCREG_SDER);
3762  .mon();
3764  .mon()
3765  .mapsTo(MISCREG_SDCR);
3794  .hyp().mon()
3797  .hyp().mon();
3799  .hyp().mon()
3800  .mapsTo(MISCREG_HTCR);
3802  .hyp().mon()
3805  .hyp().mon()
3806  .mapsTo(MISCREG_VTCR);
3808  .hypSecure().mon();
3810  .hypSecure().mon();
3812  .mon();
3814  .mon();
3816  .hyp().mon()
3820  .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
3833  .fault(EL1, faultSpEL0)
3834  .fault(EL2, faultSpEL0)
3835  .fault(EL3, faultSpEL0);
3841  .allPrivileges(release->has(ArmExtension::FEAT_PAN))
3842  .exceptUserMode();
3846  .allPrivileges();
3848  .allPrivileges()
3849  .fault(EL0, faultDaif);
3851  .allPrivileges()
3852  .fault(EL0, faultFpcrEL0)
3853  .fault(EL1, faultFpcrEL1)
3854  .fault(EL2, faultFpcrEL2)
3855  .fault(EL3, faultFpcrEL3);
3857  .allPrivileges()
3858  .fault(EL0, faultFpcrEL0)
3859  .fault(EL1, faultFpcrEL1)
3860  .fault(EL2, faultFpcrEL2)
3861  .fault(EL3, faultFpcrEL3);
3863  .