gem5  v22.1.0.0
misc.cc
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1 /*
2  * Copyright (c) 2010-2013, 2015-2022 Arm Limited
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36  */
37 
38 #include "arch/arm/regs/misc.hh"
39 
40 #include <tuple>
41 
42 #include "arch/arm/insts/misc64.hh"
43 #include "arch/arm/isa.hh"
44 #include "base/logging.hh"
45 #include "cpu/thread_context.hh"
46 #include "dev/arm/gic_v3_cpu_interface.hh"
47 #include "sim/full_system.hh"
48 
49 namespace gem5
50 {
51 
52 namespace ArmISA
53 {
54 
55 namespace
56 {
57 
58 std::unordered_map<MiscRegNum32, MiscRegIndex> miscRegNum32ToIdx{
59  // MCR/MRC regs
60  { MiscRegNum32(14, 0, 0, 0, 0), MISCREG_DBGDIDR },
61  { MiscRegNum32(14, 0, 0, 0, 2), MISCREG_DBGDTRRXext },
62  { MiscRegNum32(14, 0, 0, 0, 4), MISCREG_DBGBVR0 },
63  { MiscRegNum32(14, 0, 0, 0, 5), MISCREG_DBGBCR0 },
64  { MiscRegNum32(14, 0, 0, 0, 6), MISCREG_DBGWVR0 },
65  { MiscRegNum32(14, 0, 0, 0, 7), MISCREG_DBGWCR0 },
66  { MiscRegNum32(14, 0, 0, 1, 0), MISCREG_DBGDSCRint },
67  { MiscRegNum32(14, 0, 0, 1, 4), MISCREG_DBGBVR1 },
68  { MiscRegNum32(14, 0, 0, 1, 5), MISCREG_DBGBCR1 },
69  { MiscRegNum32(14, 0, 0, 1, 6), MISCREG_DBGWVR1 },
70  { MiscRegNum32(14, 0, 0, 1, 7), MISCREG_DBGWCR1 },
71  { MiscRegNum32(14, 0, 0, 2, 2), MISCREG_DBGDSCRext },
72  { MiscRegNum32(14, 0, 0, 2, 4), MISCREG_DBGBVR2 },
73  { MiscRegNum32(14, 0, 0, 2, 5), MISCREG_DBGBCR2 },
74  { MiscRegNum32(14, 0, 0, 2, 6), MISCREG_DBGWVR2 },
75  { MiscRegNum32(14, 0, 0, 2, 7), MISCREG_DBGWCR2 },
76  { MiscRegNum32(14, 0, 0, 3, 2), MISCREG_DBGDTRTXext },
77  { MiscRegNum32(14, 0, 0, 3, 4), MISCREG_DBGBVR3 },
78  { MiscRegNum32(14, 0, 0, 3, 5), MISCREG_DBGBCR3 },
79  { MiscRegNum32(14, 0, 0, 3, 6), MISCREG_DBGWVR3 },
80  { MiscRegNum32(14, 0, 0, 3, 7), MISCREG_DBGWCR3 },
81  { MiscRegNum32(14, 0, 0, 4, 4), MISCREG_DBGBVR4 },
82  { MiscRegNum32(14, 0, 0, 4, 5), MISCREG_DBGBCR4 },
83  { MiscRegNum32(14, 0, 0, 4, 6), MISCREG_DBGWVR4 },
84  { MiscRegNum32(14, 0, 0, 4, 7), MISCREG_DBGWCR4 },
85  { MiscRegNum32(14, 0, 0, 5, 4), MISCREG_DBGBVR5 },
86  { MiscRegNum32(14, 0, 0, 5, 5), MISCREG_DBGBCR5 },
87  { MiscRegNum32(14, 0, 0, 5, 6), MISCREG_DBGWVR5 },
88  { MiscRegNum32(14, 0, 0, 5, 7), MISCREG_DBGWCR5 },
89  { MiscRegNum32(14, 0, 0, 6, 2), MISCREG_DBGOSECCR },
90  { MiscRegNum32(14, 0, 0, 6, 4), MISCREG_DBGBVR6 },
91  { MiscRegNum32(14, 0, 0, 6, 5), MISCREG_DBGBCR6 },
92  { MiscRegNum32(14, 0, 0, 6, 6), MISCREG_DBGWVR6 },
93  { MiscRegNum32(14, 0, 0, 6, 7), MISCREG_DBGWCR6 },
94  { MiscRegNum32(14, 0, 0, 7, 0), MISCREG_DBGVCR },
95  { MiscRegNum32(14, 0, 0, 7, 4), MISCREG_DBGBVR7 },
96  { MiscRegNum32(14, 0, 0, 7, 5), MISCREG_DBGBCR7 },
97  { MiscRegNum32(14, 0, 0, 7, 6), MISCREG_DBGWVR7 },
98  { MiscRegNum32(14, 0, 0, 7, 7), MISCREG_DBGWCR7 },
99  { MiscRegNum32(14, 0, 0, 8, 4), MISCREG_DBGBVR8 },
100  { MiscRegNum32(14, 0, 0, 8, 5), MISCREG_DBGBCR8 },
101  { MiscRegNum32(14, 0, 0, 8, 6), MISCREG_DBGWVR8 },
102  { MiscRegNum32(14, 0, 0, 8, 7), MISCREG_DBGWCR8 },
103  { MiscRegNum32(14, 0, 0, 9, 4), MISCREG_DBGBVR9 },
104  { MiscRegNum32(14, 0, 0, 9, 5), MISCREG_DBGBCR9 },
105  { MiscRegNum32(14, 0, 0, 9, 6), MISCREG_DBGWVR9 },
106  { MiscRegNum32(14, 0, 0, 9, 7), MISCREG_DBGWCR9 },
107  { MiscRegNum32(14, 0, 0, 10, 4), MISCREG_DBGBVR10 },
108  { MiscRegNum32(14, 0, 0, 10, 5), MISCREG_DBGBCR10 },
109  { MiscRegNum32(14, 0, 0, 10, 6), MISCREG_DBGWVR10 },
110  { MiscRegNum32(14, 0, 0, 10, 7), MISCREG_DBGWCR10 },
111  { MiscRegNum32(14, 0, 0, 11, 4), MISCREG_DBGBVR11 },
112  { MiscRegNum32(14, 0, 0, 11, 5), MISCREG_DBGBCR11 },
113  { MiscRegNum32(14, 0, 0, 11, 6), MISCREG_DBGWVR11 },
114  { MiscRegNum32(14, 0, 0, 11, 7), MISCREG_DBGWCR11 },
115  { MiscRegNum32(14, 0, 0, 12, 4), MISCREG_DBGBVR12 },
116  { MiscRegNum32(14, 0, 0, 12, 5), MISCREG_DBGBCR12 },
117  { MiscRegNum32(14, 0, 0, 12, 6), MISCREG_DBGWVR12 },
118  { MiscRegNum32(14, 0, 0, 12, 7), MISCREG_DBGWCR12 },
119  { MiscRegNum32(14, 0, 0, 13, 4), MISCREG_DBGBVR13 },
120  { MiscRegNum32(14, 0, 0, 13, 5), MISCREG_DBGBCR13 },
121  { MiscRegNum32(14, 0, 0, 13, 6), MISCREG_DBGWVR13 },
122  { MiscRegNum32(14, 0, 0, 13, 7), MISCREG_DBGWCR13 },
123  { MiscRegNum32(14, 0, 0, 14, 4), MISCREG_DBGBVR14 },
124  { MiscRegNum32(14, 0, 0, 14, 5), MISCREG_DBGBCR14 },
125  { MiscRegNum32(14, 0, 0, 14, 6), MISCREG_DBGWVR14 },
126  { MiscRegNum32(14, 0, 0, 14, 7), MISCREG_DBGWCR14 },
127  { MiscRegNum32(14, 0, 0, 15, 4), MISCREG_DBGBVR15 },
128  { MiscRegNum32(14, 0, 0, 15, 5), MISCREG_DBGBCR15 },
129  { MiscRegNum32(14, 0, 0, 15, 6), MISCREG_DBGWVR15 },
130  { MiscRegNum32(14, 0, 0, 15, 7), MISCREG_DBGWCR15 },
131  { MiscRegNum32(14, 0, 1, 0, 1), MISCREG_DBGBXVR0 },
132  { MiscRegNum32(14, 0, 1, 0, 4), MISCREG_DBGOSLAR },
133  { MiscRegNum32(14, 0, 1, 1, 1), MISCREG_DBGBXVR1 },
134  { MiscRegNum32(14, 0, 1, 1, 4), MISCREG_DBGOSLSR },
135  { MiscRegNum32(14, 0, 1, 2, 1), MISCREG_DBGBXVR2 },
136  { MiscRegNum32(14, 0, 1, 3, 1), MISCREG_DBGBXVR3 },
137  { MiscRegNum32(14, 0, 1, 3, 4), MISCREG_DBGOSDLR },
138  { MiscRegNum32(14, 0, 1, 4, 1), MISCREG_DBGBXVR4 },
139  { MiscRegNum32(14, 0, 1, 4, 4), MISCREG_DBGPRCR },
140  { MiscRegNum32(14, 0, 1, 5, 1), MISCREG_DBGBXVR5 },
141  { MiscRegNum32(14, 0, 1, 6, 1), MISCREG_DBGBXVR6 },
142  { MiscRegNum32(14, 0, 1, 7, 1), MISCREG_DBGBXVR7 },
143  { MiscRegNum32(14, 0, 1, 8, 1), MISCREG_DBGBXVR8 },
144  { MiscRegNum32(14, 0, 1, 9, 1), MISCREG_DBGBXVR9 },
145  { MiscRegNum32(14, 0, 1, 10, 1), MISCREG_DBGBXVR10 },
146  { MiscRegNum32(14, 0, 1, 11, 1), MISCREG_DBGBXVR11 },
147  { MiscRegNum32(14, 0, 1, 12, 1), MISCREG_DBGBXVR12 },
148  { MiscRegNum32(14, 0, 1, 13, 1), MISCREG_DBGBXVR13 },
149  { MiscRegNum32(14, 0, 1, 14, 1), MISCREG_DBGBXVR14 },
150  { MiscRegNum32(14, 0, 1, 15, 1), MISCREG_DBGBXVR15 },
151  { MiscRegNum32(14, 6, 1, 0, 0), MISCREG_TEEHBR },
152  { MiscRegNum32(14, 7, 0, 0, 0), MISCREG_JIDR },
153  { MiscRegNum32(14, 7, 1, 0, 0), MISCREG_JOSCR },
154  { MiscRegNum32(14, 7, 2, 0, 0), MISCREG_JMCR },
155  { MiscRegNum32(15, 0, 0, 0, 0), MISCREG_MIDR },
156  { MiscRegNum32(15, 0, 0, 0, 1), MISCREG_CTR },
157  { MiscRegNum32(15, 0, 0, 0, 2), MISCREG_TCMTR },
158  { MiscRegNum32(15, 0, 0, 0, 3), MISCREG_TLBTR },
159  { MiscRegNum32(15, 0, 0, 0, 4), MISCREG_MIDR },
160  { MiscRegNum32(15, 0, 0, 0, 5), MISCREG_MPIDR },
161  { MiscRegNum32(15, 0, 0, 0, 6), MISCREG_REVIDR },
162  { MiscRegNum32(15, 0, 0, 0, 7), MISCREG_MIDR },
163  { MiscRegNum32(15, 0, 0, 1, 0), MISCREG_ID_PFR0 },
164  { MiscRegNum32(15, 0, 0, 1, 1), MISCREG_ID_PFR1 },
165  { MiscRegNum32(15, 0, 0, 1, 2), MISCREG_ID_DFR0 },
166  { MiscRegNum32(15, 0, 0, 1, 3), MISCREG_ID_AFR0 },
167  { MiscRegNum32(15, 0, 0, 1, 4), MISCREG_ID_MMFR0 },
168  { MiscRegNum32(15, 0, 0, 1, 5), MISCREG_ID_MMFR1 },
169  { MiscRegNum32(15, 0, 0, 1, 6), MISCREG_ID_MMFR2 },
170  { MiscRegNum32(15, 0, 0, 1, 7), MISCREG_ID_MMFR3 },
171  { MiscRegNum32(15, 0, 0, 2, 0), MISCREG_ID_ISAR0 },
172  { MiscRegNum32(15, 0, 0, 2, 1), MISCREG_ID_ISAR1 },
173  { MiscRegNum32(15, 0, 0, 2, 2), MISCREG_ID_ISAR2 },
174  { MiscRegNum32(15, 0, 0, 2, 3), MISCREG_ID_ISAR3 },
175  { MiscRegNum32(15, 0, 0, 2, 4), MISCREG_ID_ISAR4 },
176  { MiscRegNum32(15, 0, 0, 2, 5), MISCREG_ID_ISAR5 },
177  { MiscRegNum32(15, 0, 0, 2, 6), MISCREG_ID_MMFR4 },
178  { MiscRegNum32(15, 0, 0, 2, 7), MISCREG_ID_ISAR6 },
179  { MiscRegNum32(15, 0, 0, 3, 0), MISCREG_RAZ },
180  { MiscRegNum32(15, 0, 0, 3, 1), MISCREG_RAZ },
181  { MiscRegNum32(15, 0, 0, 3, 2), MISCREG_RAZ },
182  { MiscRegNum32(15, 0, 0, 3, 3), MISCREG_RAZ },
183  { MiscRegNum32(15, 0, 0, 3, 4), MISCREG_RAZ },
184  { MiscRegNum32(15, 0, 0, 3, 5), MISCREG_RAZ },
185  { MiscRegNum32(15, 0, 0, 3, 6), MISCREG_RAZ },
186  { MiscRegNum32(15, 0, 0, 3, 7), MISCREG_RAZ },
187  { MiscRegNum32(15, 0, 0, 4, 0), MISCREG_RAZ },
188  { MiscRegNum32(15, 0, 0, 4, 1), MISCREG_RAZ },
189  { MiscRegNum32(15, 0, 0, 4, 2), MISCREG_RAZ },
190  { MiscRegNum32(15, 0, 0, 4, 3), MISCREG_RAZ },
191  { MiscRegNum32(15, 0, 0, 4, 4), MISCREG_RAZ },
192  { MiscRegNum32(15, 0, 0, 4, 5), MISCREG_RAZ },
193  { MiscRegNum32(15, 0, 0, 4, 6), MISCREG_RAZ },
194  { MiscRegNum32(15, 0, 0, 4, 7), MISCREG_RAZ },
195  { MiscRegNum32(15, 0, 0, 5, 0), MISCREG_RAZ },
196  { MiscRegNum32(15, 0, 0, 5, 1), MISCREG_RAZ },
197  { MiscRegNum32(15, 0, 0, 5, 2), MISCREG_RAZ },
198  { MiscRegNum32(15, 0, 0, 5, 3), MISCREG_RAZ },
199  { MiscRegNum32(15, 0, 0, 5, 4), MISCREG_RAZ },
200  { MiscRegNum32(15, 0, 0, 5, 5), MISCREG_RAZ },
201  { MiscRegNum32(15, 0, 0, 5, 6), MISCREG_RAZ },
202  { MiscRegNum32(15, 0, 0, 5, 7), MISCREG_RAZ },
203  { MiscRegNum32(15, 0, 0, 6, 0), MISCREG_RAZ },
204  { MiscRegNum32(15, 0, 0, 6, 1), MISCREG_RAZ },
205  { MiscRegNum32(15, 0, 0, 6, 2), MISCREG_RAZ },
206  { MiscRegNum32(15, 0, 0, 6, 3), MISCREG_RAZ },
207  { MiscRegNum32(15, 0, 0, 6, 4), MISCREG_RAZ },
208  { MiscRegNum32(15, 0, 0, 6, 5), MISCREG_RAZ },
209  { MiscRegNum32(15, 0, 0, 6, 6), MISCREG_RAZ },
210  { MiscRegNum32(15, 0, 0, 6, 7), MISCREG_RAZ },
211  { MiscRegNum32(15, 0, 0, 7, 0), MISCREG_RAZ },
212  { MiscRegNum32(15, 0, 0, 7, 1), MISCREG_RAZ },
213  { MiscRegNum32(15, 0, 0, 7, 2), MISCREG_RAZ },
214  { MiscRegNum32(15, 0, 0, 7, 3), MISCREG_RAZ },
215  { MiscRegNum32(15, 0, 0, 7, 4), MISCREG_RAZ },
216  { MiscRegNum32(15, 0, 0, 7, 5), MISCREG_RAZ },
217  { MiscRegNum32(15, 0, 0, 7, 6), MISCREG_RAZ },
218  { MiscRegNum32(15, 0, 0, 7, 7), MISCREG_RAZ },
219  { MiscRegNum32(15, 0, 0, 8, 0), MISCREG_RAZ },
220  { MiscRegNum32(15, 0, 0, 8, 1), MISCREG_RAZ },
221  { MiscRegNum32(15, 0, 0, 8, 2), MISCREG_RAZ },
222  { MiscRegNum32(15, 0, 0, 8, 3), MISCREG_RAZ },
223  { MiscRegNum32(15, 0, 0, 8, 4), MISCREG_RAZ },
224  { MiscRegNum32(15, 0, 0, 8, 5), MISCREG_RAZ },
225  { MiscRegNum32(15, 0, 0, 8, 6), MISCREG_RAZ },
226  { MiscRegNum32(15, 0, 0, 8, 7), MISCREG_RAZ },
227  { MiscRegNum32(15, 0, 0, 9, 0), MISCREG_RAZ },
228  { MiscRegNum32(15, 0, 0, 9, 1), MISCREG_RAZ },
229  { MiscRegNum32(15, 0, 0, 9, 2), MISCREG_RAZ },
230  { MiscRegNum32(15, 0, 0, 9, 3), MISCREG_RAZ },
231  { MiscRegNum32(15, 0, 0, 9, 4), MISCREG_RAZ },
232  { MiscRegNum32(15, 0, 0, 9, 5), MISCREG_RAZ },
233  { MiscRegNum32(15, 0, 0, 9, 6), MISCREG_RAZ },
234  { MiscRegNum32(15, 0, 0, 9, 7), MISCREG_RAZ },
235  { MiscRegNum32(15, 0, 0, 10, 0), MISCREG_RAZ },
236  { MiscRegNum32(15, 0, 0, 10, 1), MISCREG_RAZ },
237  { MiscRegNum32(15, 0, 0, 10, 2), MISCREG_RAZ },
238  { MiscRegNum32(15, 0, 0, 10, 3), MISCREG_RAZ },
239  { MiscRegNum32(15, 0, 0, 10, 4), MISCREG_RAZ },
240  { MiscRegNum32(15, 0, 0, 10, 5), MISCREG_RAZ },
241  { MiscRegNum32(15, 0, 0, 10, 6), MISCREG_RAZ },
242  { MiscRegNum32(15, 0, 0, 10, 7), MISCREG_RAZ },
243  { MiscRegNum32(15, 0, 0, 11, 0), MISCREG_RAZ },
244  { MiscRegNum32(15, 0, 0, 11, 1), MISCREG_RAZ },
245  { MiscRegNum32(15, 0, 0, 11, 2), MISCREG_RAZ },
246  { MiscRegNum32(15, 0, 0, 11, 3), MISCREG_RAZ },
247  { MiscRegNum32(15, 0, 0, 11, 4), MISCREG_RAZ },
248  { MiscRegNum32(15, 0, 0, 11, 5), MISCREG_RAZ },
249  { MiscRegNum32(15, 0, 0, 11, 6), MISCREG_RAZ },
250  { MiscRegNum32(15, 0, 0, 11, 7), MISCREG_RAZ },
251  { MiscRegNum32(15, 0, 0, 12, 0), MISCREG_RAZ },
252  { MiscRegNum32(15, 0, 0, 12, 1), MISCREG_RAZ },
253  { MiscRegNum32(15, 0, 0, 12, 2), MISCREG_RAZ },
254  { MiscRegNum32(15, 0, 0, 12, 3), MISCREG_RAZ },
255  { MiscRegNum32(15, 0, 0, 12, 4), MISCREG_RAZ },
256  { MiscRegNum32(15, 0, 0, 12, 5), MISCREG_RAZ },
257  { MiscRegNum32(15, 0, 0, 12, 6), MISCREG_RAZ },
258  { MiscRegNum32(15, 0, 0, 12, 7), MISCREG_RAZ },
259  { MiscRegNum32(15, 0, 0, 13, 0), MISCREG_RAZ },
260  { MiscRegNum32(15, 0, 0, 13, 1), MISCREG_RAZ },
261  { MiscRegNum32(15, 0, 0, 13, 2), MISCREG_RAZ },
262  { MiscRegNum32(15, 0, 0, 13, 3), MISCREG_RAZ },
263  { MiscRegNum32(15, 0, 0, 13, 4), MISCREG_RAZ },
264  { MiscRegNum32(15, 0, 0, 13, 5), MISCREG_RAZ },
265  { MiscRegNum32(15, 0, 0, 13, 6), MISCREG_RAZ },
266  { MiscRegNum32(15, 0, 0, 13, 7), MISCREG_RAZ },
267  { MiscRegNum32(15, 0, 0, 14, 0), MISCREG_RAZ },
268  { MiscRegNum32(15, 0, 0, 14, 1), MISCREG_RAZ },
269  { MiscRegNum32(15, 0, 0, 14, 2), MISCREG_RAZ },
270  { MiscRegNum32(15, 0, 0, 14, 3), MISCREG_RAZ },
271  { MiscRegNum32(15, 0, 0, 14, 4), MISCREG_RAZ },
272  { MiscRegNum32(15, 0, 0, 14, 5), MISCREG_RAZ },
273  { MiscRegNum32(15, 0, 0, 14, 6), MISCREG_RAZ },
274  { MiscRegNum32(15, 0, 0, 14, 7), MISCREG_RAZ },
275  { MiscRegNum32(15, 0, 0, 15, 0), MISCREG_RAZ },
276  { MiscRegNum32(15, 0, 0, 15, 1), MISCREG_RAZ },
277  { MiscRegNum32(15, 0, 0, 15, 2), MISCREG_RAZ },
278  { MiscRegNum32(15, 0, 0, 15, 3), MISCREG_RAZ },
279  { MiscRegNum32(15, 0, 0, 15, 4), MISCREG_RAZ },
280  { MiscRegNum32(15, 0, 0, 15, 5), MISCREG_RAZ },
281  { MiscRegNum32(15, 0, 0, 15, 6), MISCREG_RAZ },
282  { MiscRegNum32(15, 0, 0, 15, 7), MISCREG_RAZ },
283  { MiscRegNum32(15, 0, 1, 0, 0), MISCREG_SCTLR },
284  { MiscRegNum32(15, 0, 1, 0, 1), MISCREG_ACTLR },
285  { MiscRegNum32(15, 0, 1, 0, 2), MISCREG_CPACR },
286  { MiscRegNum32(15, 0, 1, 1, 0), MISCREG_SCR },
287  { MiscRegNum32(15, 0, 1, 1, 1), MISCREG_SDER },
288  { MiscRegNum32(15, 0, 1, 1, 2), MISCREG_NSACR },
289  { MiscRegNum32(15, 0, 1, 3, 1), MISCREG_SDCR },
290  { MiscRegNum32(15, 0, 2, 0, 0), MISCREG_TTBR0 },
291  { MiscRegNum32(15, 0, 2, 0, 1), MISCREG_TTBR1 },
292  { MiscRegNum32(15, 0, 2, 0, 2), MISCREG_TTBCR },
293  { MiscRegNum32(15, 0, 3, 0, 0), MISCREG_DACR },
294  { MiscRegNum32(15, 0, 4, 6, 0), MISCREG_ICC_PMR },
295  { MiscRegNum32(15, 0, 5, 0, 0), MISCREG_DFSR },
296  { MiscRegNum32(15, 0, 5, 0, 1), MISCREG_IFSR },
297  { MiscRegNum32(15, 0, 5, 1, 0), MISCREG_ADFSR },
298  { MiscRegNum32(15, 0, 5, 1, 1), MISCREG_AIFSR },
299  { MiscRegNum32(15, 0, 6, 0, 0), MISCREG_DFAR },
300  { MiscRegNum32(15, 0, 6, 0, 2), MISCREG_IFAR },
301  { MiscRegNum32(15, 0, 7, 0, 4), MISCREG_NOP },
302  { MiscRegNum32(15, 0, 7, 1, 0), MISCREG_ICIALLUIS },
303  { MiscRegNum32(15, 0, 7, 1, 6), MISCREG_BPIALLIS },
304  { MiscRegNum32(15, 0, 7, 2, 7), MISCREG_DBGDEVID0 },
305  { MiscRegNum32(15, 0, 7, 4, 0), MISCREG_PAR },
306  { MiscRegNum32(15, 0, 7, 5, 0), MISCREG_ICIALLU },
307  { MiscRegNum32(15, 0, 7, 5, 1), MISCREG_ICIMVAU },
308  { MiscRegNum32(15, 0, 7, 5, 4), MISCREG_CP15ISB },
309  { MiscRegNum32(15, 0, 7, 5, 6), MISCREG_BPIALL },
310  { MiscRegNum32(15, 0, 7, 5, 7), MISCREG_BPIMVA },
311  { MiscRegNum32(15, 0, 7, 6, 1), MISCREG_DCIMVAC },
312  { MiscRegNum32(15, 0, 7, 6, 2), MISCREG_DCISW },
313  { MiscRegNum32(15, 0, 7, 8, 0), MISCREG_ATS1CPR },
314  { MiscRegNum32(15, 0, 7, 8, 1), MISCREG_ATS1CPW },
315  { MiscRegNum32(15, 0, 7, 8, 2), MISCREG_ATS1CUR },
316  { MiscRegNum32(15, 0, 7, 8, 3), MISCREG_ATS1CUW },
317  { MiscRegNum32(15, 0, 7, 8, 4), MISCREG_ATS12NSOPR },
318  { MiscRegNum32(15, 0, 7, 8, 5), MISCREG_ATS12NSOPW },
319  { MiscRegNum32(15, 0, 7, 8, 6), MISCREG_ATS12NSOUR },
320  { MiscRegNum32(15, 0, 7, 8, 7), MISCREG_ATS12NSOUW },
321  { MiscRegNum32(15, 0, 7, 10, 1), MISCREG_DCCMVAC },
322  { MiscRegNum32(15, 0, 7, 10, 2), MISCREG_DCCSW },
323  { MiscRegNum32(15, 0, 7, 10, 4), MISCREG_CP15DSB },
324  { MiscRegNum32(15, 0, 7, 10, 5), MISCREG_CP15DMB },
325  { MiscRegNum32(15, 0, 7, 11, 1), MISCREG_DCCMVAU },
326  { MiscRegNum32(15, 0, 7, 13, 1), MISCREG_NOP },
327  { MiscRegNum32(15, 0, 7, 14, 1), MISCREG_DCCIMVAC },
328  { MiscRegNum32(15, 0, 7, 14, 2), MISCREG_DCCISW },
329  { MiscRegNum32(15, 0, 8, 3, 0), MISCREG_TLBIALLIS },
330  { MiscRegNum32(15, 0, 8, 3, 1), MISCREG_TLBIMVAIS },
331  { MiscRegNum32(15, 0, 8, 3, 2), MISCREG_TLBIASIDIS },
332  { MiscRegNum32(15, 0, 8, 3, 3), MISCREG_TLBIMVAAIS },
333  { MiscRegNum32(15, 0, 8, 3, 5), MISCREG_TLBIMVALIS },
334  { MiscRegNum32(15, 0, 8, 3, 7), MISCREG_TLBIMVAALIS },
335  { MiscRegNum32(15, 0, 8, 5, 0), MISCREG_ITLBIALL },
336  { MiscRegNum32(15, 0, 8, 5, 1), MISCREG_ITLBIMVA },
337  { MiscRegNum32(15, 0, 8, 5, 2), MISCREG_ITLBIASID },
338  { MiscRegNum32(15, 0, 8, 6, 0), MISCREG_DTLBIALL },
339  { MiscRegNum32(15, 0, 8, 6, 1), MISCREG_DTLBIMVA },
340  { MiscRegNum32(15, 0, 8, 6, 2), MISCREG_DTLBIASID },
341  { MiscRegNum32(15, 0, 8, 7, 0), MISCREG_TLBIALL },
342  { MiscRegNum32(15, 0, 8, 7, 1), MISCREG_TLBIMVA },
343  { MiscRegNum32(15, 0, 8, 7, 2), MISCREG_TLBIASID },
344  { MiscRegNum32(15, 0, 8, 7, 3), MISCREG_TLBIMVAA },
345  { MiscRegNum32(15, 0, 8, 7, 5), MISCREG_TLBIMVAL },
346  { MiscRegNum32(15, 0, 8, 7, 7), MISCREG_TLBIMVAAL },
347  { MiscRegNum32(15, 0, 9, 12, 0), MISCREG_PMCR },
348  { MiscRegNum32(15, 0, 9, 12, 1), MISCREG_PMCNTENSET },
349  { MiscRegNum32(15, 0, 9, 12, 2), MISCREG_PMCNTENCLR },
350  { MiscRegNum32(15, 0, 9, 12, 3), MISCREG_PMOVSR },
351  { MiscRegNum32(15, 0, 9, 12, 4), MISCREG_PMSWINC },
352  { MiscRegNum32(15, 0, 9, 12, 5), MISCREG_PMSELR },
353  { MiscRegNum32(15, 0, 9, 12, 6), MISCREG_PMCEID0 },
354  { MiscRegNum32(15, 0, 9, 12, 7), MISCREG_PMCEID1 },
355  { MiscRegNum32(15, 0, 9, 13, 0), MISCREG_PMCCNTR },
356  { MiscRegNum32(15, 0, 9, 13, 1), MISCREG_PMXEVTYPER_PMCCFILTR },
357  { MiscRegNum32(15, 0, 9, 13, 2), MISCREG_PMXEVCNTR },
358  { MiscRegNum32(15, 0, 9, 14, 0), MISCREG_PMUSERENR },
359  { MiscRegNum32(15, 0, 9, 14, 1), MISCREG_PMINTENSET },
360  { MiscRegNum32(15, 0, 9, 14, 2), MISCREG_PMINTENCLR },
361  { MiscRegNum32(15, 0, 9, 14, 3), MISCREG_PMOVSSET },
362  { MiscRegNum32(15, 0, 10, 2, 0), MISCREG_PRRR_MAIR0 },
363  { MiscRegNum32(15, 0, 10, 2, 1), MISCREG_NMRR_MAIR1 },
364  { MiscRegNum32(15, 0, 10, 3, 0), MISCREG_AMAIR0 },
365  { MiscRegNum32(15, 0, 10, 3, 1), MISCREG_AMAIR1 },
366  { MiscRegNum32(15, 0, 12, 0, 0), MISCREG_VBAR },
367  { MiscRegNum32(15, 0, 12, 0, 1), MISCREG_MVBAR },
368  { MiscRegNum32(15, 0, 12, 1, 0), MISCREG_ISR },
369  { MiscRegNum32(15, 0, 12, 8, 0), MISCREG_ICC_IAR0 },
370  { MiscRegNum32(15, 0, 12, 8, 1), MISCREG_ICC_EOIR0 },
371  { MiscRegNum32(15, 0, 12, 8, 2), MISCREG_ICC_HPPIR0 },
372  { MiscRegNum32(15, 0, 12, 8, 3), MISCREG_ICC_BPR0 },
373  { MiscRegNum32(15, 0, 12, 8, 4), MISCREG_ICC_AP0R0 },
374  { MiscRegNum32(15, 0, 12, 8, 5), MISCREG_ICC_AP0R1 },
375  { MiscRegNum32(15, 0, 12, 8, 6), MISCREG_ICC_AP0R2 },
376  { MiscRegNum32(15, 0, 12, 8, 7), MISCREG_ICC_AP0R3 },
377  { MiscRegNum32(15, 0, 12, 9, 0), MISCREG_ICC_AP1R0 },
378  { MiscRegNum32(15, 0, 12, 9, 1), MISCREG_ICC_AP1R1 },
379  { MiscRegNum32(15, 0, 12, 9, 2), MISCREG_ICC_AP1R2 },
380  { MiscRegNum32(15, 0, 12, 9, 3), MISCREG_ICC_AP1R3 },
381  { MiscRegNum32(15, 0, 12, 11, 1), MISCREG_ICC_DIR },
382  { MiscRegNum32(15, 0, 12, 11, 3), MISCREG_ICC_RPR },
383  { MiscRegNum32(15, 0, 12, 12, 0), MISCREG_ICC_IAR1 },
384  { MiscRegNum32(15, 0, 12, 12, 1), MISCREG_ICC_EOIR1 },
385  { MiscRegNum32(15, 0, 12, 12, 2), MISCREG_ICC_HPPIR1 },
386  { MiscRegNum32(15, 0, 12, 12, 3), MISCREG_ICC_BPR1 },
387  { MiscRegNum32(15, 0, 12, 12, 4), MISCREG_ICC_CTLR },
388  { MiscRegNum32(15, 0, 12, 12, 5), MISCREG_ICC_SRE },
389  { MiscRegNum32(15, 0, 12, 12, 6), MISCREG_ICC_IGRPEN0 },
390  { MiscRegNum32(15, 0, 12, 12, 7), MISCREG_ICC_IGRPEN1 },
391  { MiscRegNum32(15, 0, 13, 0, 0), MISCREG_FCSEIDR },
392  { MiscRegNum32(15, 0, 13, 0, 1), MISCREG_CONTEXTIDR },
393  { MiscRegNum32(15, 0, 13, 0, 2), MISCREG_TPIDRURW },
394  { MiscRegNum32(15, 0, 13, 0, 3), MISCREG_TPIDRURO },
395  { MiscRegNum32(15, 0, 13, 0, 4), MISCREG_TPIDRPRW },
396  { MiscRegNum32(15, 0, 14, 0, 0), MISCREG_CNTFRQ },
397  { MiscRegNum32(15, 0, 14, 1, 0), MISCREG_CNTKCTL },
398  { MiscRegNum32(15, 0, 14, 2, 0), MISCREG_CNTP_TVAL },
399  { MiscRegNum32(15, 0, 14, 2, 1), MISCREG_CNTP_CTL },
400  { MiscRegNum32(15, 0, 14, 3, 0), MISCREG_CNTV_TVAL },
401  { MiscRegNum32(15, 0, 14, 3, 1), MISCREG_CNTV_CTL },
402  { MiscRegNum32(15, 1, 0, 0, 0), MISCREG_CCSIDR },
403  { MiscRegNum32(15, 1, 0, 0, 1), MISCREG_CLIDR },
404  { MiscRegNum32(15, 1, 0, 0, 7), MISCREG_AIDR },
405  { MiscRegNum32(15, 2, 0, 0, 0), MISCREG_CSSELR },
406  { MiscRegNum32(15, 4, 0, 0, 0), MISCREG_VPIDR },
407  { MiscRegNum32(15, 4, 0, 0, 5), MISCREG_VMPIDR },
408  { MiscRegNum32(15, 4, 1, 0, 0), MISCREG_HSCTLR },
409  { MiscRegNum32(15, 4, 1, 0, 1), MISCREG_HACTLR },
410  { MiscRegNum32(15, 4, 1, 1, 0), MISCREG_HCR },
411  { MiscRegNum32(15, 4, 1, 1, 1), MISCREG_HDCR },
412  { MiscRegNum32(15, 4, 1, 1, 2), MISCREG_HCPTR },
413  { MiscRegNum32(15, 4, 1, 1, 3), MISCREG_HSTR },
414  { MiscRegNum32(15, 4, 1, 1, 4), MISCREG_HCR2 },
415  { MiscRegNum32(15, 4, 1, 1, 7), MISCREG_HACR },
416  { MiscRegNum32(15, 4, 2, 0, 2), MISCREG_HTCR },
417  { MiscRegNum32(15, 4, 2, 1, 2), MISCREG_VTCR },
418  { MiscRegNum32(15, 4, 5, 1, 0), MISCREG_HADFSR },
419  { MiscRegNum32(15, 4, 5, 1, 1), MISCREG_HAIFSR },
420  { MiscRegNum32(15, 4, 5, 2, 0), MISCREG_HSR },
421  { MiscRegNum32(15, 4, 6, 0, 0), MISCREG_HDFAR },
422  { MiscRegNum32(15, 4, 6, 0, 2), MISCREG_HIFAR },
423  { MiscRegNum32(15, 4, 6, 0, 4), MISCREG_HPFAR },
424  { MiscRegNum32(15, 4, 7, 8, 0), MISCREG_ATS1HR },
425  { MiscRegNum32(15, 4, 7, 8, 1), MISCREG_ATS1HW },
426  { MiscRegNum32(15, 4, 8, 0, 1), MISCREG_TLBIIPAS2IS },
427  { MiscRegNum32(15, 4, 8, 0, 5), MISCREG_TLBIIPAS2LIS },
428  { MiscRegNum32(15, 4, 8, 3, 0), MISCREG_TLBIALLHIS },
429  { MiscRegNum32(15, 4, 8, 3, 1), MISCREG_TLBIMVAHIS },
430  { MiscRegNum32(15, 4, 8, 3, 4), MISCREG_TLBIALLNSNHIS },
431  { MiscRegNum32(15, 4, 8, 3, 5), MISCREG_TLBIMVALHIS },
432  { MiscRegNum32(15, 4, 8, 4, 1), MISCREG_TLBIIPAS2 },
433  { MiscRegNum32(15, 4, 8, 4, 5), MISCREG_TLBIIPAS2L },
434  { MiscRegNum32(15, 4, 8, 7, 0), MISCREG_TLBIALLH },
435  { MiscRegNum32(15, 4, 8, 7, 1), MISCREG_TLBIMVAH },
436  { MiscRegNum32(15, 4, 8, 7, 4), MISCREG_TLBIALLNSNH },
437  { MiscRegNum32(15, 4, 8, 7, 5), MISCREG_TLBIMVALH },
438  { MiscRegNum32(15, 4, 10, 2, 0), MISCREG_HMAIR0 },
439  { MiscRegNum32(15, 4, 10, 2, 1), MISCREG_HMAIR1 },
440  { MiscRegNum32(15, 4, 10, 3, 0), MISCREG_HAMAIR0 },
441  { MiscRegNum32(15, 4, 10, 3, 1), MISCREG_HAMAIR1 },
442  { MiscRegNum32(15, 4, 12, 0, 0), MISCREG_HVBAR },
443  { MiscRegNum32(15, 4, 12, 8, 0), MISCREG_ICH_AP0R0 },
444  { MiscRegNum32(15, 4, 12, 8, 1), MISCREG_ICH_AP0R1 },
445  { MiscRegNum32(15, 4, 12, 8, 2), MISCREG_ICH_AP0R2 },
446  { MiscRegNum32(15, 4, 12, 8, 3), MISCREG_ICH_AP0R3 },
447  { MiscRegNum32(15, 4, 12, 9, 0), MISCREG_ICH_AP1R0 },
448  { MiscRegNum32(15, 4, 12, 9, 1), MISCREG_ICH_AP1R1 },
449  { MiscRegNum32(15, 4, 12, 9, 2), MISCREG_ICH_AP1R2 },
450  { MiscRegNum32(15, 4, 12, 9, 3), MISCREG_ICH_AP1R3 },
451  { MiscRegNum32(15, 4, 12, 9, 5), MISCREG_ICC_HSRE },
452  { MiscRegNum32(15, 4, 12, 11, 0), MISCREG_ICH_HCR },
453  { MiscRegNum32(15, 4, 12, 11, 1), MISCREG_ICH_VTR },
454  { MiscRegNum32(15, 4, 12, 11, 2), MISCREG_ICH_MISR },
455  { MiscRegNum32(15, 4, 12, 11, 3), MISCREG_ICH_EISR },
456  { MiscRegNum32(15, 4, 12, 11, 5), MISCREG_ICH_ELRSR },
457  { MiscRegNum32(15, 4, 12, 11, 7), MISCREG_ICH_VMCR },
458  { MiscRegNum32(15, 4, 12, 12, 0), MISCREG_ICH_LR0 },
459  { MiscRegNum32(15, 4, 12, 12, 1), MISCREG_ICH_LR1 },
460  { MiscRegNum32(15, 4, 12, 12, 2), MISCREG_ICH_LR2 },
461  { MiscRegNum32(15, 4, 12, 12, 3), MISCREG_ICH_LR3 },
462  { MiscRegNum32(15, 4, 12, 12, 4), MISCREG_ICH_LR4 },
463  { MiscRegNum32(15, 4, 12, 12, 5), MISCREG_ICH_LR5 },
464  { MiscRegNum32(15, 4, 12, 12, 6), MISCREG_ICH_LR6 },
465  { MiscRegNum32(15, 4, 12, 12, 7), MISCREG_ICH_LR7 },
466  { MiscRegNum32(15, 4, 12, 13, 0), MISCREG_ICH_LR8 },
467  { MiscRegNum32(15, 4, 12, 13, 1), MISCREG_ICH_LR9 },
468  { MiscRegNum32(15, 4, 12, 13, 2), MISCREG_ICH_LR10 },
469  { MiscRegNum32(15, 4, 12, 13, 3), MISCREG_ICH_LR11 },
470  { MiscRegNum32(15, 4, 12, 13, 4), MISCREG_ICH_LR12 },
471  { MiscRegNum32(15, 4, 12, 13, 5), MISCREG_ICH_LR13 },
472  { MiscRegNum32(15, 4, 12, 13, 6), MISCREG_ICH_LR14 },
473  { MiscRegNum32(15, 4, 12, 13, 7), MISCREG_ICH_LR15 },
474  { MiscRegNum32(15, 4, 12, 14, 0), MISCREG_ICH_LRC0 },
475  { MiscRegNum32(15, 4, 12, 14, 1), MISCREG_ICH_LRC1 },
476  { MiscRegNum32(15, 4, 12, 14, 2), MISCREG_ICH_LRC2 },
477  { MiscRegNum32(15, 4, 12, 14, 3), MISCREG_ICH_LRC3 },
478  { MiscRegNum32(15, 4, 12, 14, 4), MISCREG_ICH_LRC4 },
479  { MiscRegNum32(15, 4, 12, 14, 5), MISCREG_ICH_LRC5 },
480  { MiscRegNum32(15, 4, 12, 14, 6), MISCREG_ICH_LRC6 },
481  { MiscRegNum32(15, 4, 12, 14, 7), MISCREG_ICH_LRC7 },
482  { MiscRegNum32(15, 4, 12, 15, 0), MISCREG_ICH_LRC8 },
483  { MiscRegNum32(15, 4, 12, 15, 1), MISCREG_ICH_LRC9 },
484  { MiscRegNum32(15, 4, 12, 15, 2), MISCREG_ICH_LRC10 },
485  { MiscRegNum32(15, 4, 12, 15, 3), MISCREG_ICH_LRC11 },
486  { MiscRegNum32(15, 4, 12, 15, 4), MISCREG_ICH_LRC12 },
487  { MiscRegNum32(15, 4, 12, 15, 5), MISCREG_ICH_LRC13 },
488  { MiscRegNum32(15, 4, 12, 15, 6), MISCREG_ICH_LRC14 },
489  { MiscRegNum32(15, 4, 12, 15, 7), MISCREG_ICH_LRC15 },
490  { MiscRegNum32(15, 4, 13, 0, 2), MISCREG_HTPIDR },
491  { MiscRegNum32(15, 4, 14, 1, 0), MISCREG_CNTHCTL },
492  { MiscRegNum32(15, 4, 14, 2, 0), MISCREG_CNTHP_TVAL },
493  { MiscRegNum32(15, 4, 14, 2, 1), MISCREG_CNTHP_CTL },
494  { MiscRegNum32(15, 6, 12, 12, 4), MISCREG_ICC_MCTLR },
495  { MiscRegNum32(15, 6, 12, 12, 5), MISCREG_ICC_MSRE },
496  { MiscRegNum32(15, 6, 12, 12, 7), MISCREG_ICC_MGRPEN1 },
497  // MCRR/MRRC regs
498  { MiscRegNum32(15, 0, 2), MISCREG_TTBR0 },
499  { MiscRegNum32(15, 0, 7), MISCREG_PAR },
500  { MiscRegNum32(15, 0, 12), MISCREG_ICC_SGI1R },
501  { MiscRegNum32(15, 0, 14), MISCREG_CNTPCT },
502  { MiscRegNum32(15, 0, 15), MISCREG_CPUMERRSR },
503  { MiscRegNum32(15, 1, 2), MISCREG_TTBR1 },
504  { MiscRegNum32(15, 1, 12), MISCREG_ICC_ASGI1R },
505  { MiscRegNum32(15, 1, 14), MISCREG_CNTVCT },
506  { MiscRegNum32(15, 1, 15), MISCREG_L2MERRSR },
507  { MiscRegNum32(15, 2, 12), MISCREG_ICC_SGI0R },
508  { MiscRegNum32(15, 2, 14), MISCREG_CNTP_CVAL },
509  { MiscRegNum32(15, 3, 14), MISCREG_CNTV_CVAL },
510  { MiscRegNum32(15, 4, 2), MISCREG_HTTBR },
511  { MiscRegNum32(15, 4, 14), MISCREG_CNTVOFF },
512  { MiscRegNum32(15, 6, 2), MISCREG_VTTBR },
513  { MiscRegNum32(15, 6, 14), MISCREG_CNTHP_CVAL },
514 };
515 
516 }
517 
518 MiscRegIndex
519 decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
520 {
521  MiscRegNum32 cop_reg(14, opc1, crn, crm, opc2);
522  auto it = miscRegNum32ToIdx.find(cop_reg);
523  if (it != miscRegNum32ToIdx.end()) {
524  return it->second;
525  } else {
526  warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
527  crn, opc1, crm, opc2);
528  return MISCREG_UNKNOWN;
529  }
530 }
531 
532 MiscRegIndex
533 decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
534 {
535  MiscRegNum32 cop_reg(15, opc1, crn, crm, opc2);
536  auto it = miscRegNum32ToIdx.find(cop_reg);
537  if (it != miscRegNum32ToIdx.end()) {
538  return it->second;
539  } else {
540  if ((crn == 15) ||
541  (crn == 9 && (crm <= 2 || crm >= 5)) ||
542  (crn == 10 && opc1 == 0 && crm <= 1) ||
543  (crn == 11 && opc1 <= 7 && (crm <= 8 || crm ==15))) {
544  return MISCREG_IMPDEF_UNIMPL;
545  } else {
546  return MISCREG_UNKNOWN;
547  }
548  }
549 }
550 
551 MiscRegIndex
552 decodeCP15Reg64(unsigned crm, unsigned opc1)
553 {
554  MiscRegNum32 cop_reg(15, opc1, crm);
555  auto it = miscRegNum32ToIdx.find(cop_reg);
556  if (it != miscRegNum32ToIdx.end()) {
557  return it->second;
558  } else {
559  return MISCREG_UNKNOWN;
560  }
561 }
562 
563 std::tuple<bool, bool>
564 canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
565 {
566  bool secure = !scr.ns;
567  bool can_read = false;
568  bool undefined = false;
569  auto& miscreg_info = lookUpMiscReg[reg].info;
570 
571  switch (cpsr.mode) {
572  case MODE_USER:
573  can_read = secure ? miscreg_info[MISCREG_USR_S_RD] :
574  miscreg_info[MISCREG_USR_NS_RD];
575  break;
576  case MODE_FIQ:
577  case MODE_IRQ:
578  case MODE_SVC:
579  case MODE_ABORT:
580  case MODE_UNDEFINED:
581  case MODE_SYSTEM:
582  can_read = secure ? miscreg_info[MISCREG_PRI_S_RD] :
583  miscreg_info[MISCREG_PRI_NS_RD];
584  break;
585  case MODE_MON:
586  can_read = secure ? miscreg_info[MISCREG_MON_NS0_RD] :
587  miscreg_info[MISCREG_MON_NS1_RD];
588  break;
589  case MODE_HYP:
590  can_read = miscreg_info[MISCREG_HYP_NS_RD];
591  break;
592  default:
593  undefined = true;
594  }
595 
596  switch (reg) {
597  case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
598  if (!undefined)
599  undefined = AArch32isUndefinedGenericTimer(reg, tc);
600  break;
601  default:
602  break;
603  }
604 
605  // can't do permissions checkes on the root of a banked pair of regs
606  assert(!miscreg_info[MISCREG_BANKED]);
607  return std::make_tuple(can_read, undefined);
608 }
609 
610 std::tuple<bool, bool>
611 canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
612 {
613  bool secure = !scr.ns;
614  bool can_write = false;
615  bool undefined = false;
616  const auto& miscreg_info = lookUpMiscReg[reg].info;
617 
618  switch (cpsr.mode) {
619  case MODE_USER:
620  can_write = secure ? miscreg_info[MISCREG_USR_S_WR] :
621  miscreg_info[MISCREG_USR_NS_WR];
622  break;
623  case MODE_FIQ:
624  case MODE_IRQ:
625  case MODE_SVC:
626  case MODE_ABORT:
627  case MODE_UNDEFINED:
628  case MODE_SYSTEM:
629  can_write = secure ? miscreg_info[MISCREG_PRI_S_WR] :
630  miscreg_info[MISCREG_PRI_NS_WR];
631  break;
632  case MODE_MON:
633  can_write = secure ? miscreg_info[MISCREG_MON_NS0_WR] :
634  miscreg_info[MISCREG_MON_NS1_WR];
635  break;
636  case MODE_HYP:
637  can_write = miscreg_info[MISCREG_HYP_NS_WR];
638  break;
639  default:
640  undefined = true;
641  }
642 
643  switch (reg) {
644  case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
645  if (!undefined)
646  undefined = AArch32isUndefinedGenericTimer(reg, tc);
647  break;
648  default:
649  break;
650  }
651 
652  // can't do permissions checkes on the root of a banked pair of regs
653  assert(!miscreg_info[MISCREG_BANKED]);
654  return std::make_tuple(can_write, undefined);
655 }
656 
657 bool
658 AArch32isUndefinedGenericTimer(MiscRegIndex reg, ThreadContext *tc)
659 {
660  if (currEL(tc) == EL0 && ELIs32(tc, EL1)) {
661  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
662  bool trap_cond = condGenericTimerSystemAccessTrapEL1(reg, tc);
663  if (trap_cond && (!EL2Enabled(tc) || !hcr.tge))
664  return true;
665  }
666  return false;
667 }
668 
669 int
670 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
671 {
672  SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
673  return snsBankedIndex(reg, tc, scr.ns);
674 }
675 
676 int
677 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
678 {
679  int reg_as_int = static_cast<int>(reg);
680  if (lookUpMiscReg[reg].info[MISCREG_BANKED]) {
681  reg_as_int += (ArmSystem::haveEL(tc, EL3) &&
682  !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
683  }
684  return reg_as_int;
685 }
686 
687 int
688 snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc)
689 {
690  auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
691  SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
692  return isa->snsBankedIndex64(reg, scr.ns);
693 }
694 
703 int unflattenResultMiscReg[NUM_MISCREGS];
704 
705 void
706 preUnflattenMiscReg()
707 {
708  int reg = -1;
709  for (int i = 0 ; i < NUM_MISCREGS; i++){
710  if (lookUpMiscReg[i].info[MISCREG_BANKED])
711  reg = i;
712  if (lookUpMiscReg[i].info[MISCREG_BANKED_CHILD])
713  unflattenResultMiscReg[i] = reg;
714  else
715  unflattenResultMiscReg[i] = i;
716  // if this assert fails, no parent was found, and something is broken
717  assert(unflattenResultMiscReg[i] > -1);
718  }
719 }
720 
721 int
722 unflattenMiscReg(int reg)
723 {
724  return unflattenResultMiscReg[reg];
725 }
726 
727 Fault
728 checkFaultAccessAArch64SysReg(MiscRegIndex reg, CPSR cpsr,
729  ThreadContext *tc, const MiscRegOp64 &inst)
730 {
731  return lookUpMiscReg[reg].checkFault(tc, inst, currEL(cpsr));
732 }
733 
734 std::vector<struct MiscRegLUTEntry> lookUpMiscReg(NUM_MISCREGS);
735 
736 namespace {
737 
738 // The map is translating a MiscRegIndex into AArch64 system register
739 // numbers (op0, op1, crn, crm, op2)
740 std::unordered_map<MiscRegIndex, MiscRegNum64> idxToMiscRegNum;
741 
742 // The map is translating AArch64 system register numbers
743 // (op0, op1, crn, crm, op2) into a MiscRegIndex
744 std::unordered_map<MiscRegNum64, MiscRegIndex> miscRegNumToIdx{
745  { MiscRegNum64(1, 0, 7, 1, 0), MISCREG_IC_IALLUIS },
746  { MiscRegNum64(1, 0, 7, 5, 0), MISCREG_IC_IALLU },
747  { MiscRegNum64(1, 0, 7, 6, 1), MISCREG_DC_IVAC_Xt },
748  { MiscRegNum64(1, 0, 7, 6, 2), MISCREG_DC_ISW_Xt },
749  { MiscRegNum64(1, 0, 7, 8, 0), MISCREG_AT_S1E1R_Xt },
750  { MiscRegNum64(1, 0, 7, 8, 1), MISCREG_AT_S1E1W_Xt },
751  { MiscRegNum64(1, 0, 7, 8, 2), MISCREG_AT_S1E0R_Xt },
752  { MiscRegNum64(1, 0, 7, 8, 3), MISCREG_AT_S1E0W_Xt },
753  { MiscRegNum64(1, 0, 7, 10, 2), MISCREG_DC_CSW_Xt },
754  { MiscRegNum64(1, 0, 7, 14, 2), MISCREG_DC_CISW_Xt },
755  { MiscRegNum64(1, 0, 8, 3, 0), MISCREG_TLBI_VMALLE1IS },
756  { MiscRegNum64(1, 0, 8, 3, 1), MISCREG_TLBI_VAE1IS_Xt },
757  { MiscRegNum64(1, 0, 8, 3, 2), MISCREG_TLBI_ASIDE1IS_Xt },
758  { MiscRegNum64(1, 0, 8, 3, 3), MISCREG_TLBI_VAAE1IS_Xt },
759  { MiscRegNum64(1, 0, 8, 3, 5), MISCREG_TLBI_VALE1IS_Xt },
760  { MiscRegNum64(1, 0, 8, 3, 7), MISCREG_TLBI_VAALE1IS_Xt },
761  { MiscRegNum64(1, 0, 8, 7, 0), MISCREG_TLBI_VMALLE1 },
762  { MiscRegNum64(1, 0, 8, 7, 1), MISCREG_TLBI_VAE1_Xt },
763  { MiscRegNum64(1, 0, 8, 7, 2), MISCREG_TLBI_ASIDE1_Xt },
764  { MiscRegNum64(1, 0, 8, 7, 3), MISCREG_TLBI_VAAE1_Xt },
765  { MiscRegNum64(1, 0, 8, 7, 5), MISCREG_TLBI_VALE1_Xt },
766  { MiscRegNum64(1, 0, 8, 7, 7), MISCREG_TLBI_VAALE1_Xt },
767  { MiscRegNum64(1, 3, 7, 4, 1), MISCREG_DC_ZVA_Xt },
768  { MiscRegNum64(1, 3, 7, 5, 1), MISCREG_IC_IVAU_Xt },
769  { MiscRegNum64(1, 3, 7, 10, 1), MISCREG_DC_CVAC_Xt },
770  { MiscRegNum64(1, 3, 7, 11, 1), MISCREG_DC_CVAU_Xt },
771  { MiscRegNum64(1, 3, 7, 14, 1), MISCREG_DC_CIVAC_Xt },
772  { MiscRegNum64(1, 4, 7, 8, 0), MISCREG_AT_S1E2R_Xt },
773  { MiscRegNum64(1, 4, 7, 8, 1), MISCREG_AT_S1E2W_Xt },
774  { MiscRegNum64(1, 4, 7, 8, 4), MISCREG_AT_S12E1R_Xt },
775  { MiscRegNum64(1, 4, 7, 8, 5), MISCREG_AT_S12E1W_Xt },
776  { MiscRegNum64(1, 4, 7, 8, 6), MISCREG_AT_S12E0R_Xt },
777  { MiscRegNum64(1, 4, 7, 8, 7), MISCREG_AT_S12E0W_Xt },
778  { MiscRegNum64(1, 4, 8, 0, 1), MISCREG_TLBI_IPAS2E1IS_Xt },
779  { MiscRegNum64(1, 4, 8, 0, 5), MISCREG_TLBI_IPAS2LE1IS_Xt },
780  { MiscRegNum64(1, 4, 8, 3, 0), MISCREG_TLBI_ALLE2IS },
781  { MiscRegNum64(1, 4, 8, 3, 1), MISCREG_TLBI_VAE2IS_Xt },
782  { MiscRegNum64(1, 4, 8, 3, 4), MISCREG_TLBI_ALLE1IS },
783  { MiscRegNum64(1, 4, 8, 3, 5), MISCREG_TLBI_VALE2IS_Xt },
784  { MiscRegNum64(1, 4, 8, 3, 6), MISCREG_TLBI_VMALLS12E1IS },
785  { MiscRegNum64(1, 4, 8, 4, 1), MISCREG_TLBI_IPAS2E1_Xt },
786  { MiscRegNum64(1, 4, 8, 4, 5), MISCREG_TLBI_IPAS2LE1_Xt },
787  { MiscRegNum64(1, 4, 8, 7, 0), MISCREG_TLBI_ALLE2 },
788  { MiscRegNum64(1, 4, 8, 7, 1), MISCREG_TLBI_VAE2_Xt },
789  { MiscRegNum64(1, 4, 8, 7, 4), MISCREG_TLBI_ALLE1 },
790  { MiscRegNum64(1, 4, 8, 7, 5), MISCREG_TLBI_VALE2_Xt },
791  { MiscRegNum64(1, 4, 8, 7, 6), MISCREG_TLBI_VMALLS12E1 },
792  { MiscRegNum64(1, 6, 7, 8, 0), MISCREG_AT_S1E3R_Xt },
793  { MiscRegNum64(1, 6, 7, 8, 1), MISCREG_AT_S1E3W_Xt },
794  { MiscRegNum64(1, 6, 8, 3, 0), MISCREG_TLBI_ALLE3IS },
795  { MiscRegNum64(1, 6, 8, 3, 1), MISCREG_TLBI_VAE3IS_Xt },
796  { MiscRegNum64(1, 6, 8, 3, 5), MISCREG_TLBI_VALE3IS_Xt },
797  { MiscRegNum64(1, 6, 8, 7, 0), MISCREG_TLBI_ALLE3 },
798  { MiscRegNum64(1, 6, 8, 7, 1), MISCREG_TLBI_VAE3_Xt },
799  { MiscRegNum64(1, 6, 8, 7, 5), MISCREG_TLBI_VALE3_Xt },
800  { MiscRegNum64(2, 0, 0, 0, 2), MISCREG_OSDTRRX_EL1 },
801  { MiscRegNum64(2, 0, 0, 0, 4), MISCREG_DBGBVR0_EL1 },
802  { MiscRegNum64(2, 0, 0, 0, 5), MISCREG_DBGBCR0_EL1 },
803  { MiscRegNum64(2, 0, 0, 0, 6), MISCREG_DBGWVR0_EL1 },
804  { MiscRegNum64(2, 0, 0, 0, 7), MISCREG_DBGWCR0_EL1 },
805  { MiscRegNum64(2, 0, 0, 1, 4), MISCREG_DBGBVR1_EL1 },
806  { MiscRegNum64(2, 0, 0, 1, 5), MISCREG_DBGBCR1_EL1 },
807  { MiscRegNum64(2, 0, 0, 1, 6), MISCREG_DBGWVR1_EL1 },
808  { MiscRegNum64(2, 0, 0, 1, 7), MISCREG_DBGWCR1_EL1 },
809  { MiscRegNum64(2, 0, 0, 2, 0), MISCREG_MDCCINT_EL1 },
810  { MiscRegNum64(2, 0, 0, 2, 2), MISCREG_MDSCR_EL1 },
811  { MiscRegNum64(2, 0, 0, 2, 4), MISCREG_DBGBVR2_EL1 },
812  { MiscRegNum64(2, 0, 0, 2, 5), MISCREG_DBGBCR2_EL1 },
813  { MiscRegNum64(2, 0, 0, 2, 6), MISCREG_DBGWVR2_EL1 },
814  { MiscRegNum64(2, 0, 0, 2, 7), MISCREG_DBGWCR2_EL1 },
815  { MiscRegNum64(2, 0, 0, 3, 2), MISCREG_OSDTRTX_EL1 },
816  { MiscRegNum64(2, 0, 0, 3, 4), MISCREG_DBGBVR3_EL1 },
817  { MiscRegNum64(2, 0, 0, 3, 5), MISCREG_DBGBCR3_EL1 },
818  { MiscRegNum64(2, 0, 0, 3, 6), MISCREG_DBGWVR3_EL1 },
819  { MiscRegNum64(2, 0, 0, 3, 7), MISCREG_DBGWCR3_EL1 },
820  { MiscRegNum64(2, 0, 0, 4, 4), MISCREG_DBGBVR4_EL1 },
821  { MiscRegNum64(2, 0, 0, 4, 5), MISCREG_DBGBCR4_EL1 },
822  { MiscRegNum64(2, 0, 0, 4, 6), MISCREG_DBGWVR4_EL1 },
823  { MiscRegNum64(2, 0, 0, 4, 7), MISCREG_DBGWCR4_EL1 },
824  { MiscRegNum64(2, 0, 0, 5, 4), MISCREG_DBGBVR5_EL1 },
825  { MiscRegNum64(2, 0, 0, 5, 5), MISCREG_DBGBCR5_EL1 },
826  { MiscRegNum64(2, 0, 0, 5, 6), MISCREG_DBGWVR5_EL1 },
827  { MiscRegNum64(2, 0, 0, 5, 7), MISCREG_DBGWCR5_EL1 },
828  { MiscRegNum64(2, 0, 0, 6, 2), MISCREG_OSECCR_EL1 },
829  { MiscRegNum64(2, 0, 0, 6, 4), MISCREG_DBGBVR6_EL1 },
830  { MiscRegNum64(2, 0, 0, 6, 5), MISCREG_DBGBCR6_EL1 },
831  { MiscRegNum64(2, 0, 0, 6, 6), MISCREG_DBGWVR6_EL1 },
832  { MiscRegNum64(2, 0, 0, 6, 7), MISCREG_DBGWCR6_EL1 },
833  { MiscRegNum64(2, 0, 0, 7, 4), MISCREG_DBGBVR7_EL1 },
834  { MiscRegNum64(2, 0, 0, 7, 5), MISCREG_DBGBCR7_EL1 },
835  { MiscRegNum64(2, 0, 0, 7, 6), MISCREG_DBGWVR7_EL1 },
836  { MiscRegNum64(2, 0, 0, 7, 7), MISCREG_DBGWCR7_EL1 },
837  { MiscRegNum64(2, 0, 0, 8, 4), MISCREG_DBGBVR8_EL1 },
838  { MiscRegNum64(2, 0, 0, 8, 5), MISCREG_DBGBCR8_EL1 },
839  { MiscRegNum64(2, 0, 0, 8, 6), MISCREG_DBGWVR8_EL1 },
840  { MiscRegNum64(2, 0, 0, 8, 7), MISCREG_DBGWCR8_EL1 },
841  { MiscRegNum64(2, 0, 0, 9, 4), MISCREG_DBGBVR9_EL1 },
842  { MiscRegNum64(2, 0, 0, 9, 5), MISCREG_DBGBCR9_EL1 },
843  { MiscRegNum64(2, 0, 0, 9, 6), MISCREG_DBGWVR9_EL1 },
844  { MiscRegNum64(2, 0, 0, 9, 7), MISCREG_DBGWCR9_EL1 },
845  { MiscRegNum64(2, 0, 0, 10, 4), MISCREG_DBGBVR10_EL1 },
846  { MiscRegNum64(2, 0, 0, 10, 5), MISCREG_DBGBCR10_EL1 },
847  { MiscRegNum64(2, 0, 0, 10, 6), MISCREG_DBGWVR10_EL1 },
848  { MiscRegNum64(2, 0, 0, 10, 7), MISCREG_DBGWCR10_EL1 },
849  { MiscRegNum64(2, 0, 0, 11, 4), MISCREG_DBGBVR11_EL1 },
850  { MiscRegNum64(2, 0, 0, 11, 5), MISCREG_DBGBCR11_EL1 },
851  { MiscRegNum64(2, 0, 0, 11, 6), MISCREG_DBGWVR11_EL1 },
852  { MiscRegNum64(2, 0, 0, 11, 7), MISCREG_DBGWCR11_EL1 },
853  { MiscRegNum64(2, 0, 0, 12, 4), MISCREG_DBGBVR12_EL1 },
854  { MiscRegNum64(2, 0, 0, 12, 5), MISCREG_DBGBCR12_EL1 },
855  { MiscRegNum64(2, 0, 0, 12, 6), MISCREG_DBGWVR12_EL1 },
856  { MiscRegNum64(2, 0, 0, 12, 7), MISCREG_DBGWCR12_EL1 },
857  { MiscRegNum64(2, 0, 0, 13, 4), MISCREG_DBGBVR13_EL1 },
858  { MiscRegNum64(2, 0, 0, 13, 5), MISCREG_DBGBCR13_EL1 },
859  { MiscRegNum64(2, 0, 0, 13, 6), MISCREG_DBGWVR13_EL1 },
860  { MiscRegNum64(2, 0, 0, 13, 7), MISCREG_DBGWCR13_EL1 },
861  { MiscRegNum64(2, 0, 0, 14, 4), MISCREG_DBGBVR14_EL1 },
862  { MiscRegNum64(2, 0, 0, 14, 5), MISCREG_DBGBCR14_EL1 },
863  { MiscRegNum64(2, 0, 0, 14, 6), MISCREG_DBGWVR14_EL1 },
864  { MiscRegNum64(2, 0, 0, 14, 7), MISCREG_DBGWCR14_EL1 },
865  { MiscRegNum64(2, 0, 0, 15, 4), MISCREG_DBGBVR15_EL1 },
866  { MiscRegNum64(2, 0, 0, 15, 5), MISCREG_DBGBCR15_EL1 },
867  { MiscRegNum64(2, 0, 0, 15, 6), MISCREG_DBGWVR15_EL1 },
868  { MiscRegNum64(2, 0, 0, 15, 7), MISCREG_DBGWCR15_EL1 },
869  { MiscRegNum64(2, 0, 1, 0, 0), MISCREG_MDRAR_EL1 },
870  { MiscRegNum64(2, 0, 1, 0, 4), MISCREG_OSLAR_EL1 },
871  { MiscRegNum64(2, 0, 1, 1, 4), MISCREG_OSLSR_EL1 },
872  { MiscRegNum64(2, 0, 1, 3, 4), MISCREG_OSDLR_EL1 },
873  { MiscRegNum64(2, 0, 1, 4, 4), MISCREG_DBGPRCR_EL1 },
874  { MiscRegNum64(2, 0, 7, 8, 6), MISCREG_DBGCLAIMSET_EL1 },
875  { MiscRegNum64(2, 0, 7, 9, 6), MISCREG_DBGCLAIMCLR_EL1 },
876  { MiscRegNum64(2, 0, 7, 14, 6), MISCREG_DBGAUTHSTATUS_EL1 },
877  { MiscRegNum64(2, 2, 0, 0, 0), MISCREG_TEECR32_EL1 },
878  { MiscRegNum64(2, 2, 1, 0, 0), MISCREG_TEEHBR32_EL1 },
879  { MiscRegNum64(2, 3, 0, 1, 0), MISCREG_MDCCSR_EL0 },
880  { MiscRegNum64(2, 3, 0, 4, 0), MISCREG_MDDTR_EL0 },
881  { MiscRegNum64(2, 3, 0, 5, 0), MISCREG_MDDTRRX_EL0 },
882  { MiscRegNum64(2, 4, 0, 7, 0), MISCREG_DBGVCR32_EL2 },
883  { MiscRegNum64(3, 0, 0, 0, 0), MISCREG_MIDR_EL1 },
884  { MiscRegNum64(3, 0, 0, 0, 5), MISCREG_MPIDR_EL1 },
885  { MiscRegNum64(3, 0, 0, 0, 6), MISCREG_REVIDR_EL1 },
886  { MiscRegNum64(3, 0, 0, 1, 0), MISCREG_ID_PFR0_EL1 },
887  { MiscRegNum64(3, 0, 0, 1, 1), MISCREG_ID_PFR1_EL1 },
888  { MiscRegNum64(3, 0, 0, 1, 2), MISCREG_ID_DFR0_EL1 },
889  { MiscRegNum64(3, 0, 0, 1, 3), MISCREG_ID_AFR0_EL1 },
890  { MiscRegNum64(3, 0, 0, 1, 4), MISCREG_ID_MMFR0_EL1 },
891  { MiscRegNum64(3, 0, 0, 1, 5), MISCREG_ID_MMFR1_EL1 },
892  { MiscRegNum64(3, 0, 0, 1, 6), MISCREG_ID_MMFR2_EL1 },
893  { MiscRegNum64(3, 0, 0, 1, 7), MISCREG_ID_MMFR3_EL1 },
894  { MiscRegNum64(3, 0, 0, 2, 0), MISCREG_ID_ISAR0_EL1 },
895  { MiscRegNum64(3, 0, 0, 2, 1), MISCREG_ID_ISAR1_EL1 },
896  { MiscRegNum64(3, 0, 0, 2, 2), MISCREG_ID_ISAR2_EL1 },
897  { MiscRegNum64(3, 0, 0, 2, 3), MISCREG_ID_ISAR3_EL1 },
898  { MiscRegNum64(3, 0, 0, 2, 4), MISCREG_ID_ISAR4_EL1 },
899  { MiscRegNum64(3, 0, 0, 2, 5), MISCREG_ID_ISAR5_EL1 },
900  { MiscRegNum64(3, 0, 0, 2, 6), MISCREG_ID_MMFR4_EL1 },
901  { MiscRegNum64(3, 0, 0, 2, 7), MISCREG_ID_ISAR6_EL1 },
902  { MiscRegNum64(3, 0, 0, 3, 0), MISCREG_MVFR0_EL1 },
903  { MiscRegNum64(3, 0, 0, 3, 1), MISCREG_MVFR1_EL1 },
904  { MiscRegNum64(3, 0, 0, 3, 2), MISCREG_MVFR2_EL1 },
905  { MiscRegNum64(3, 0, 0, 3, 3), MISCREG_RAZ },
906  { MiscRegNum64(3, 0, 0, 3, 4), MISCREG_RAZ },
907  { MiscRegNum64(3, 0, 0, 3, 5), MISCREG_RAZ },
908  { MiscRegNum64(3, 0, 0, 3, 6), MISCREG_RAZ },
909  { MiscRegNum64(3, 0, 0, 3, 7), MISCREG_RAZ },
910  { MiscRegNum64(3, 0, 0, 4, 0), MISCREG_ID_AA64PFR0_EL1 },
911  { MiscRegNum64(3, 0, 0, 4, 1), MISCREG_ID_AA64PFR1_EL1 },
912  { MiscRegNum64(3, 0, 0, 4, 2), MISCREG_RAZ },
913  { MiscRegNum64(3, 0, 0, 4, 3), MISCREG_RAZ },
914  { MiscRegNum64(3, 0, 0, 4, 4), MISCREG_ID_AA64ZFR0_EL1 },
915  { MiscRegNum64(3, 0, 0, 4, 5), MISCREG_RAZ },
916  { MiscRegNum64(3, 0, 0, 4, 6), MISCREG_RAZ },
917  { MiscRegNum64(3, 0, 0, 4, 7), MISCREG_RAZ },
918  { MiscRegNum64(3, 0, 0, 5, 0), MISCREG_ID_AA64DFR0_EL1 },
919  { MiscRegNum64(3, 0, 0, 5, 1), MISCREG_ID_AA64DFR1_EL1 },
920  { MiscRegNum64(3, 0, 0, 5, 2), MISCREG_RAZ },
921  { MiscRegNum64(3, 0, 0, 5, 3), MISCREG_RAZ },
922  { MiscRegNum64(3, 0, 0, 5, 4), MISCREG_ID_AA64AFR0_EL1 },
923  { MiscRegNum64(3, 0, 0, 5, 5), MISCREG_ID_AA64AFR1_EL1 },
924  { MiscRegNum64(3, 0, 0, 5, 6), MISCREG_RAZ },
925  { MiscRegNum64(3, 0, 0, 5, 7), MISCREG_RAZ },
926  { MiscRegNum64(3, 0, 0, 6, 0), MISCREG_ID_AA64ISAR0_EL1 },
927  { MiscRegNum64(3, 0, 0, 6, 1), MISCREG_ID_AA64ISAR1_EL1 },
928  { MiscRegNum64(3, 0, 0, 6, 2), MISCREG_RAZ },
929  { MiscRegNum64(3, 0, 0, 6, 3), MISCREG_RAZ },
930  { MiscRegNum64(3, 0, 0, 6, 4), MISCREG_RAZ },
931  { MiscRegNum64(3, 0, 0, 6, 5), MISCREG_RAZ },
932  { MiscRegNum64(3, 0, 0, 6, 6), MISCREG_RAZ },
933  { MiscRegNum64(3, 0, 0, 6, 7), MISCREG_RAZ },
934  { MiscRegNum64(3, 0, 0, 7, 0), MISCREG_ID_AA64MMFR0_EL1 },
935  { MiscRegNum64(3, 0, 0, 7, 1), MISCREG_ID_AA64MMFR1_EL1 },
936  { MiscRegNum64(3, 0, 0, 7, 2), MISCREG_ID_AA64MMFR2_EL1 },
937  { MiscRegNum64(3, 0, 0, 7, 3), MISCREG_RAZ },
938  { MiscRegNum64(3, 0, 0, 7, 4), MISCREG_RAZ },
939  { MiscRegNum64(3, 0, 0, 7, 5), MISCREG_RAZ },
940  { MiscRegNum64(3, 0, 0, 7, 6), MISCREG_RAZ },
941  { MiscRegNum64(3, 0, 0, 7, 7), MISCREG_RAZ },
942  { MiscRegNum64(3, 0, 1, 0, 0), MISCREG_SCTLR_EL1 },
943  { MiscRegNum64(3, 0, 1, 0, 1), MISCREG_ACTLR_EL1 },
944  { MiscRegNum64(3, 0, 1, 0, 2), MISCREG_CPACR_EL1 },
945  { MiscRegNum64(3, 0, 1, 2, 0), MISCREG_ZCR_EL1 },
946  { MiscRegNum64(3, 0, 2, 0, 0), MISCREG_TTBR0_EL1 },
947  { MiscRegNum64(3, 0, 2, 0, 1), MISCREG_TTBR1_EL1 },
948  { MiscRegNum64(3, 0, 2, 0, 2), MISCREG_TCR_EL1 },
949  { MiscRegNum64(3, 0, 2, 1, 0), MISCREG_APIAKeyLo_EL1 },
950  { MiscRegNum64(3, 0, 2, 1, 1), MISCREG_APIAKeyHi_EL1 },
951  { MiscRegNum64(3, 0, 2, 1, 2), MISCREG_APIBKeyLo_EL1 },
952  { MiscRegNum64(3, 0, 2, 1, 3), MISCREG_APIBKeyHi_EL1 },
953  { MiscRegNum64(3, 0, 2, 2, 0), MISCREG_APDAKeyLo_EL1 },
954  { MiscRegNum64(3, 0, 2, 2, 1), MISCREG_APDAKeyHi_EL1 },
955  { MiscRegNum64(3, 0, 2, 2, 2), MISCREG_APDBKeyLo_EL1 },
956  { MiscRegNum64(3, 0, 2, 2, 3), MISCREG_APDBKeyHi_EL1 },
957  { MiscRegNum64(3, 0, 2, 3, 0), MISCREG_APGAKeyLo_EL1 },
958  { MiscRegNum64(3, 0, 2, 3, 1), MISCREG_APGAKeyHi_EL1 },
959  { MiscRegNum64(3, 0, 4, 0, 0), MISCREG_SPSR_EL1 },
960  { MiscRegNum64(3, 0, 4, 0, 1), MISCREG_ELR_EL1 },
961  { MiscRegNum64(3, 0, 4, 1, 0), MISCREG_SP_EL0 },
962  { MiscRegNum64(3, 0, 4, 2, 0), MISCREG_SPSEL },
963  { MiscRegNum64(3, 0, 4, 2, 2), MISCREG_CURRENTEL },
964  { MiscRegNum64(3, 0, 4, 2, 3), MISCREG_PAN },
965  { MiscRegNum64(3, 0, 4, 2, 4), MISCREG_UAO },
966  { MiscRegNum64(3, 0, 4, 6, 0), MISCREG_ICC_PMR_EL1 },
967  { MiscRegNum64(3, 0, 5, 1, 0), MISCREG_AFSR0_EL1 },
968  { MiscRegNum64(3, 0, 5, 1, 1), MISCREG_AFSR1_EL1 },
969  { MiscRegNum64(3, 0, 5, 2, 0), MISCREG_ESR_EL1 },
970  { MiscRegNum64(3, 0, 5, 3, 0), MISCREG_ERRIDR_EL1 },
971  { MiscRegNum64(3, 0, 5, 3, 1), MISCREG_ERRSELR_EL1 },
972  { MiscRegNum64(3, 0, 5, 4, 0), MISCREG_ERXFR_EL1 },
973  { MiscRegNum64(3, 0, 5, 4, 1), MISCREG_ERXCTLR_EL1 },
974  { MiscRegNum64(3, 0, 5, 4, 2), MISCREG_ERXSTATUS_EL1 },
975  { MiscRegNum64(3, 0, 5, 4, 3), MISCREG_ERXADDR_EL1 },
976  { MiscRegNum64(3, 0, 5, 5, 0), MISCREG_ERXMISC0_EL1 },
977  { MiscRegNum64(3, 0, 5, 5, 1), MISCREG_ERXMISC1_EL1 },
978  { MiscRegNum64(3, 0, 6, 0, 0), MISCREG_FAR_EL1 },
979  { MiscRegNum64(3, 0, 7, 4, 0), MISCREG_PAR_EL1 },
980  { MiscRegNum64(3, 0, 9, 14, 1), MISCREG_PMINTENSET_EL1 },
981  { MiscRegNum64(3, 0, 9, 14, 2), MISCREG_PMINTENCLR_EL1 },
982  { MiscRegNum64(3, 0, 10, 2, 0), MISCREG_MAIR_EL1 },
983  { MiscRegNum64(3, 0, 10, 3, 0), MISCREG_AMAIR_EL1 },
984  { MiscRegNum64(3, 0, 12, 0, 0), MISCREG_VBAR_EL1 },
985  { MiscRegNum64(3, 0, 12, 0, 1), MISCREG_RVBAR_EL1 },
986  { MiscRegNum64(3, 0, 12, 1, 0), MISCREG_ISR_EL1 },
987  { MiscRegNum64(3, 0, 12, 1, 1), MISCREG_DISR_EL1 },
988  { MiscRegNum64(3, 0, 12, 8, 0), MISCREG_ICC_IAR0_EL1 },
989  { MiscRegNum64(3, 0, 12, 8, 1), MISCREG_ICC_EOIR0_EL1 },
990  { MiscRegNum64(3, 0, 12, 8, 2), MISCREG_ICC_HPPIR0_EL1 },
991  { MiscRegNum64(3, 0, 12, 8, 3), MISCREG_ICC_BPR0_EL1 },
992  { MiscRegNum64(3, 0, 12, 8, 4), MISCREG_ICC_AP0R0_EL1 },
993  { MiscRegNum64(3, 0, 12, 8, 5), MISCREG_ICC_AP0R1_EL1 },
994  { MiscRegNum64(3, 0, 12, 8, 6), MISCREG_ICC_AP0R2_EL1 },
995  { MiscRegNum64(3, 0, 12, 8, 7), MISCREG_ICC_AP0R3_EL1 },
996  { MiscRegNum64(3, 0, 12, 9, 0), MISCREG_ICC_AP1R0_EL1 },
997  { MiscRegNum64(3, 0, 12, 9, 1), MISCREG_ICC_AP1R1_EL1 },
998  { MiscRegNum64(3, 0, 12, 9, 2), MISCREG_ICC_AP1R2_EL1 },
999  { MiscRegNum64(3, 0, 12, 9, 3), MISCREG_ICC_AP1R3_EL1 },
1000  { MiscRegNum64(3, 0, 12, 11, 1), MISCREG_ICC_DIR_EL1 },
1001  { MiscRegNum64(3, 0, 12, 11, 3), MISCREG_ICC_RPR_EL1 },
1002  { MiscRegNum64(3, 0, 12, 11, 5), MISCREG_ICC_SGI1R_EL1 },
1003  { MiscRegNum64(3, 0, 12, 11, 6), MISCREG_ICC_ASGI1R_EL1 },
1004  { MiscRegNum64(3, 0, 12, 11, 7), MISCREG_ICC_SGI0R_EL1 },
1005  { MiscRegNum64(3, 0, 12, 12, 0), MISCREG_ICC_IAR1_EL1 },
1006  { MiscRegNum64(3, 0, 12, 12, 1), MISCREG_ICC_EOIR1_EL1 },
1007  { MiscRegNum64(3, 0, 12, 12, 2), MISCREG_ICC_HPPIR1_EL1 },
1008  { MiscRegNum64(3, 0, 12, 12, 3), MISCREG_ICC_BPR1_EL1 },
1009  { MiscRegNum64(3, 0, 12, 12, 4), MISCREG_ICC_CTLR_EL1 },
1010  { MiscRegNum64(3, 0, 12, 12, 5), MISCREG_ICC_SRE_EL1 },
1011  { MiscRegNum64(3, 0, 12, 12, 6), MISCREG_ICC_IGRPEN0_EL1 },
1012  { MiscRegNum64(3, 0, 12, 12, 7), MISCREG_ICC_IGRPEN1_EL1 },
1013  { MiscRegNum64(3, 0, 13, 0, 1), MISCREG_CONTEXTIDR_EL1 },
1014  { MiscRegNum64(3, 0, 13, 0, 4), MISCREG_TPIDR_EL1 },
1015  { MiscRegNum64(3, 0, 14, 1, 0), MISCREG_CNTKCTL_EL1 },
1016  { MiscRegNum64(3, 0, 15, 0, 0), MISCREG_IL1DATA0_EL1 },
1017  { MiscRegNum64(3, 0, 15, 0, 1), MISCREG_IL1DATA1_EL1 },
1018  { MiscRegNum64(3, 0, 15, 0, 2), MISCREG_IL1DATA2_EL1 },
1019  { MiscRegNum64(3, 0, 15, 0, 3), MISCREG_IL1DATA3_EL1 },
1020  { MiscRegNum64(3, 0, 15, 1, 0), MISCREG_DL1DATA0_EL1 },
1021  { MiscRegNum64(3, 0, 15, 1, 1), MISCREG_DL1DATA1_EL1 },
1022  { MiscRegNum64(3, 0, 15, 1, 2), MISCREG_DL1DATA2_EL1 },
1023  { MiscRegNum64(3, 0, 15, 1, 3), MISCREG_DL1DATA3_EL1 },
1024  { MiscRegNum64(3, 0, 15, 1, 4), MISCREG_DL1DATA4_EL1 },
1025  { MiscRegNum64(3, 1, 0, 0, 0), MISCREG_CCSIDR_EL1 },
1026  { MiscRegNum64(3, 1, 0, 0, 1), MISCREG_CLIDR_EL1 },
1027  { MiscRegNum64(3, 1, 0, 0, 7), MISCREG_AIDR_EL1 },
1028  { MiscRegNum64(3, 1, 11, 0, 2), MISCREG_L2CTLR_EL1 },
1029  { MiscRegNum64(3, 1, 11, 0, 3), MISCREG_L2ECTLR_EL1 },
1030  { MiscRegNum64(3, 1, 15, 0, 0), MISCREG_L2ACTLR_EL1 },
1031  { MiscRegNum64(3, 1, 15, 2, 0), MISCREG_CPUACTLR_EL1 },
1032  { MiscRegNum64(3, 1, 15, 2, 1), MISCREG_CPUECTLR_EL1 },
1033  { MiscRegNum64(3, 1, 15, 2, 2), MISCREG_CPUMERRSR_EL1 },
1034  { MiscRegNum64(3, 1, 15, 2, 3), MISCREG_L2MERRSR_EL1 },
1035  { MiscRegNum64(3, 1, 15, 3, 0), MISCREG_CBAR_EL1 },
1036  { MiscRegNum64(3, 2, 0, 0, 0), MISCREG_CSSELR_EL1 },
1037  { MiscRegNum64(3, 3, 0, 0, 1), MISCREG_CTR_EL0 },
1038  { MiscRegNum64(3, 3, 0, 0, 7), MISCREG_DCZID_EL0 },
1039  { MiscRegNum64(3, 3, 4, 2, 0), MISCREG_NZCV },
1040  { MiscRegNum64(3, 3, 4, 2, 1), MISCREG_DAIF },
1041  { MiscRegNum64(3, 3, 4, 4, 0), MISCREG_FPCR },
1042  { MiscRegNum64(3, 3, 4, 4, 1), MISCREG_FPSR },
1043  { MiscRegNum64(3, 3, 4, 5, 0), MISCREG_DSPSR_EL0 },
1044  { MiscRegNum64(3, 3, 4, 5, 1), MISCREG_DLR_EL0 },
1045  { MiscRegNum64(3, 3, 9, 12, 0), MISCREG_PMCR_EL0 },
1046  { MiscRegNum64(3, 3, 9, 12, 1), MISCREG_PMCNTENSET_EL0 },
1047  { MiscRegNum64(3, 3, 9, 12, 2), MISCREG_PMCNTENCLR_EL0 },
1048  { MiscRegNum64(3, 3, 9, 12, 3), MISCREG_PMOVSCLR_EL0 },
1049  { MiscRegNum64(3, 3, 9, 12, 4), MISCREG_PMSWINC_EL0 },
1050  { MiscRegNum64(3, 3, 9, 12, 5), MISCREG_PMSELR_EL0 },
1051  { MiscRegNum64(3, 3, 9, 12, 6), MISCREG_PMCEID0_EL0 },
1052  { MiscRegNum64(3, 3, 9, 12, 7), MISCREG_PMCEID1_EL0 },
1053  { MiscRegNum64(3, 3, 9, 13, 0), MISCREG_PMCCNTR_EL0 },
1054  { MiscRegNum64(3, 3, 9, 13, 1), MISCREG_PMXEVTYPER_EL0 },
1055  { MiscRegNum64(3, 3, 9, 13, 2), MISCREG_PMXEVCNTR_EL0 },
1056  { MiscRegNum64(3, 3, 9, 14, 0), MISCREG_PMUSERENR_EL0 },
1057  { MiscRegNum64(3, 3, 9, 14, 3), MISCREG_PMOVSSET_EL0 },
1058  { MiscRegNum64(3, 3, 13, 0, 2), MISCREG_TPIDR_EL0 },
1059  { MiscRegNum64(3, 3, 13, 0, 3), MISCREG_TPIDRRO_EL0 },
1060  { MiscRegNum64(3, 3, 14, 0, 0), MISCREG_CNTFRQ_EL0 },
1061  { MiscRegNum64(3, 3, 14, 0, 1), MISCREG_CNTPCT_EL0 },
1062  { MiscRegNum64(3, 3, 14, 0, 2), MISCREG_CNTVCT_EL0 },
1063  { MiscRegNum64(3, 3, 14, 2, 0), MISCREG_CNTP_TVAL_EL0 },
1064  { MiscRegNum64(3, 3, 14, 2, 1), MISCREG_CNTP_CTL_EL0 },
1065  { MiscRegNum64(3, 3, 14, 2, 2), MISCREG_CNTP_CVAL_EL0 },
1066  { MiscRegNum64(3, 3, 14, 3, 0), MISCREG_CNTV_TVAL_EL0 },
1067  { MiscRegNum64(3, 3, 14, 3, 1), MISCREG_CNTV_CTL_EL0 },
1068  { MiscRegNum64(3, 3, 14, 3, 2), MISCREG_CNTV_CVAL_EL0 },
1069  { MiscRegNum64(3, 3, 14, 8, 0), MISCREG_PMEVCNTR0_EL0 },
1070  { MiscRegNum64(3, 3, 14, 8, 1), MISCREG_PMEVCNTR1_EL0 },
1071  { MiscRegNum64(3, 3, 14, 8, 2), MISCREG_PMEVCNTR2_EL0 },
1072  { MiscRegNum64(3, 3, 14, 8, 3), MISCREG_PMEVCNTR3_EL0 },
1073  { MiscRegNum64(3, 3, 14, 8, 4), MISCREG_PMEVCNTR4_EL0 },
1074  { MiscRegNum64(3, 3, 14, 8, 5), MISCREG_PMEVCNTR5_EL0 },
1075  { MiscRegNum64(3, 3, 14, 12, 0), MISCREG_PMEVTYPER0_EL0 },
1076  { MiscRegNum64(3, 3, 14, 12, 1), MISCREG_PMEVTYPER1_EL0 },
1077  { MiscRegNum64(3, 3, 14, 12, 2), MISCREG_PMEVTYPER2_EL0 },
1078  { MiscRegNum64(3, 3, 14, 12, 3), MISCREG_PMEVTYPER3_EL0 },
1079  { MiscRegNum64(3, 3, 14, 12, 4), MISCREG_PMEVTYPER4_EL0 },
1080  { MiscRegNum64(3, 3, 14, 12, 5), MISCREG_PMEVTYPER5_EL0 },
1081  { MiscRegNum64(3, 3, 14, 15, 7), MISCREG_PMCCFILTR_EL0 },
1082  { MiscRegNum64(3, 4, 0, 0, 0), MISCREG_VPIDR_EL2 },
1083  { MiscRegNum64(3, 4, 0, 0, 5), MISCREG_VMPIDR_EL2 },
1084  { MiscRegNum64(3, 4, 1, 0, 0), MISCREG_SCTLR_EL2 },
1085  { MiscRegNum64(3, 4, 1, 0, 1), MISCREG_ACTLR_EL2 },
1086  { MiscRegNum64(3, 4, 1, 1, 0), MISCREG_HCR_EL2 },
1087  { MiscRegNum64(3, 4, 1, 1, 1), MISCREG_MDCR_EL2 },
1088  { MiscRegNum64(3, 4, 1, 1, 2), MISCREG_CPTR_EL2 },
1089  { MiscRegNum64(3, 4, 1, 1, 3), MISCREG_HSTR_EL2 },
1090  { MiscRegNum64(3, 4, 1, 1, 7), MISCREG_HACR_EL2 },
1091  { MiscRegNum64(3, 4, 1, 2, 0), MISCREG_ZCR_EL2 },
1092  { MiscRegNum64(3, 4, 2, 0, 0), MISCREG_TTBR0_EL2 },
1093  { MiscRegNum64(3, 4, 2, 0, 1), MISCREG_TTBR1_EL2 },
1094  { MiscRegNum64(3, 4, 2, 0, 2), MISCREG_TCR_EL2 },
1095  { MiscRegNum64(3, 4, 2, 1, 0), MISCREG_VTTBR_EL2 },
1096  { MiscRegNum64(3, 4, 2, 1, 2), MISCREG_VTCR_EL2 },
1097  { MiscRegNum64(3, 4, 2, 6, 0), MISCREG_VSTTBR_EL2 },
1098  { MiscRegNum64(3, 4, 2, 6, 2), MISCREG_VSTCR_EL2 },
1099  { MiscRegNum64(3, 4, 3, 0, 0), MISCREG_DACR32_EL2 },
1100  { MiscRegNum64(3, 4, 4, 0, 0), MISCREG_SPSR_EL2 },
1101  { MiscRegNum64(3, 4, 4, 0, 1), MISCREG_ELR_EL2 },
1102  { MiscRegNum64(3, 4, 4, 1, 0), MISCREG_SP_EL1 },
1103  { MiscRegNum64(3, 4, 4, 3, 0), MISCREG_SPSR_IRQ_AA64 },
1104  { MiscRegNum64(3, 4, 4, 3, 1), MISCREG_SPSR_ABT_AA64 },
1105  { MiscRegNum64(3, 4, 4, 3, 2), MISCREG_SPSR_UND_AA64 },
1106  { MiscRegNum64(3, 4, 4, 3, 3), MISCREG_SPSR_FIQ_AA64 },
1107  { MiscRegNum64(3, 4, 5, 0, 1), MISCREG_IFSR32_EL2 },
1108  { MiscRegNum64(3, 4, 5, 1, 0), MISCREG_AFSR0_EL2 },
1109  { MiscRegNum64(3, 4, 5, 1, 1), MISCREG_AFSR1_EL2 },
1110  { MiscRegNum64(3, 4, 5, 2, 0), MISCREG_ESR_EL2 },
1111  { MiscRegNum64(3, 4, 5, 2, 3), MISCREG_VSESR_EL2 },
1112  { MiscRegNum64(3, 4, 5, 3, 0), MISCREG_FPEXC32_EL2 },
1113  { MiscRegNum64(3, 4, 6, 0, 0), MISCREG_FAR_EL2 },
1114  { MiscRegNum64(3, 4, 6, 0, 4), MISCREG_HPFAR_EL2 },
1115  { MiscRegNum64(3, 4, 10, 2, 0), MISCREG_MAIR_EL2 },
1116  { MiscRegNum64(3, 4, 10, 3, 0), MISCREG_AMAIR_EL2 },
1117  { MiscRegNum64(3, 4, 12, 0, 0), MISCREG_VBAR_EL2 },
1118  { MiscRegNum64(3, 4, 12, 0, 1), MISCREG_RVBAR_EL2 },
1119  { MiscRegNum64(3, 4, 12, 1, 1), MISCREG_VDISR_EL2 },
1120  { MiscRegNum64(3, 4, 12, 8, 0), MISCREG_ICH_AP0R0_EL2 },
1121  { MiscRegNum64(3, 4, 12, 8, 1), MISCREG_ICH_AP0R1_EL2 },
1122  { MiscRegNum64(3, 4, 12, 8, 2), MISCREG_ICH_AP0R2_EL2 },
1123  { MiscRegNum64(3, 4, 12, 8, 3), MISCREG_ICH_AP0R3_EL2 },
1124  { MiscRegNum64(3, 4, 12, 9, 0), MISCREG_ICH_AP1R0_EL2 },
1125  { MiscRegNum64(3, 4, 12, 9, 1), MISCREG_ICH_AP1R1_EL2 },
1126  { MiscRegNum64(3, 4, 12, 9, 2), MISCREG_ICH_AP1R2_EL2 },
1127  { MiscRegNum64(3, 4, 12, 9, 3), MISCREG_ICH_AP1R3_EL2 },
1128  { MiscRegNum64(3, 4, 12, 9, 5), MISCREG_ICC_SRE_EL2 },
1129  { MiscRegNum64(3, 4, 12, 11, 0), MISCREG_ICH_HCR_EL2 },
1130  { MiscRegNum64(3, 4, 12, 11, 1), MISCREG_ICH_VTR_EL2 },
1131  { MiscRegNum64(3, 4, 12, 11, 2), MISCREG_ICH_MISR_EL2 },
1132  { MiscRegNum64(3, 4, 12, 11, 3), MISCREG_ICH_EISR_EL2 },
1133  { MiscRegNum64(3, 4, 12, 11, 5), MISCREG_ICH_ELRSR_EL2 },
1134  { MiscRegNum64(3, 4, 12, 11, 7), MISCREG_ICH_VMCR_EL2 },
1135  { MiscRegNum64(3, 4, 12, 12, 0), MISCREG_ICH_LR0_EL2 },
1136  { MiscRegNum64(3, 4, 12, 12, 1), MISCREG_ICH_LR1_EL2 },
1137  { MiscRegNum64(3, 4, 12, 12, 2), MISCREG_ICH_LR2_EL2 },
1138  { MiscRegNum64(3, 4, 12, 12, 3), MISCREG_ICH_LR3_EL2 },
1139  { MiscRegNum64(3, 4, 12, 12, 4), MISCREG_ICH_LR4_EL2 },
1140  { MiscRegNum64(3, 4, 12, 12, 5), MISCREG_ICH_LR5_EL2 },
1141  { MiscRegNum64(3, 4, 12, 12, 6), MISCREG_ICH_LR6_EL2 },
1142  { MiscRegNum64(3, 4, 12, 12, 7), MISCREG_ICH_LR7_EL2 },
1143  { MiscRegNum64(3, 4, 12, 13, 0), MISCREG_ICH_LR8_EL2 },
1144  { MiscRegNum64(3, 4, 12, 13, 1), MISCREG_ICH_LR9_EL2 },
1145  { MiscRegNum64(3, 4, 12, 13, 2), MISCREG_ICH_LR10_EL2 },
1146  { MiscRegNum64(3, 4, 12, 13, 3), MISCREG_ICH_LR11_EL2 },
1147  { MiscRegNum64(3, 4, 12, 13, 4), MISCREG_ICH_LR12_EL2 },
1148  { MiscRegNum64(3, 4, 12, 13, 5), MISCREG_ICH_LR13_EL2 },
1149  { MiscRegNum64(3, 4, 12, 13, 6), MISCREG_ICH_LR14_EL2 },
1150  { MiscRegNum64(3, 4, 12, 13, 7), MISCREG_ICH_LR15_EL2 },
1151  { MiscRegNum64(3, 4, 13, 0, 1), MISCREG_CONTEXTIDR_EL2 },
1152  { MiscRegNum64(3, 4, 13, 0, 2), MISCREG_TPIDR_EL2 },
1153  { MiscRegNum64(3, 4, 14, 0, 3), MISCREG_CNTVOFF_EL2 },
1154  { MiscRegNum64(3, 4, 14, 1, 0), MISCREG_CNTHCTL_EL2 },
1155  { MiscRegNum64(3, 4, 14, 2, 0), MISCREG_CNTHP_TVAL_EL2 },
1156  { MiscRegNum64(3, 4, 14, 2, 1), MISCREG_CNTHP_CTL_EL2 },
1157  { MiscRegNum64(3, 4, 14, 2, 2), MISCREG_CNTHP_CVAL_EL2 },
1158  { MiscRegNum64(3, 4, 14, 3, 0), MISCREG_CNTHV_TVAL_EL2 },
1159  { MiscRegNum64(3, 4, 14, 3, 1), MISCREG_CNTHV_CTL_EL2 },
1160  { MiscRegNum64(3, 4, 14, 3, 2), MISCREG_CNTHV_CVAL_EL2 },
1161  { MiscRegNum64(3, 4, 14, 4, 0), MISCREG_CNTHVS_TVAL_EL2 },
1162  { MiscRegNum64(3, 4, 14, 4, 1), MISCREG_CNTHVS_CTL_EL2 },
1163  { MiscRegNum64(3, 4, 14, 4, 2), MISCREG_CNTHVS_CVAL_EL2 },
1164  { MiscRegNum64(3, 4, 14, 5, 0), MISCREG_CNTHPS_TVAL_EL2 },
1165  { MiscRegNum64(3, 4, 14, 5, 1), MISCREG_CNTHPS_CTL_EL2 },
1166  { MiscRegNum64(3, 4, 14, 5, 2), MISCREG_CNTHPS_CVAL_EL2 },
1167  { MiscRegNum64(3, 5, 1, 0, 0), MISCREG_SCTLR_EL12 },
1168  { MiscRegNum64(3, 5, 1, 0, 2), MISCREG_CPACR_EL12 },
1169  { MiscRegNum64(3, 5, 1, 2, 0), MISCREG_ZCR_EL12 },
1170  { MiscRegNum64(3, 5, 2, 0, 0), MISCREG_TTBR0_EL12 },
1171  { MiscRegNum64(3, 5, 2, 0, 1), MISCREG_TTBR1_EL12 },
1172  { MiscRegNum64(3, 5, 2, 0, 2), MISCREG_TCR_EL12 },
1173  { MiscRegNum64(3, 5, 4, 0, 0), MISCREG_SPSR_EL12 },
1174  { MiscRegNum64(3, 5, 4, 0, 1), MISCREG_ELR_EL12 },
1175  { MiscRegNum64(3, 5, 5, 1, 0), MISCREG_AFSR0_EL12 },
1176  { MiscRegNum64(3, 5, 5, 1, 1), MISCREG_AFSR1_EL12 },
1177  { MiscRegNum64(3, 5, 5, 2, 0), MISCREG_ESR_EL12 },
1178  { MiscRegNum64(3, 5, 6, 0, 0), MISCREG_FAR_EL12 },
1179  { MiscRegNum64(3, 5, 10, 2, 0), MISCREG_MAIR_EL12 },
1180  { MiscRegNum64(3, 5, 10, 3, 0), MISCREG_AMAIR_EL12 },
1181  { MiscRegNum64(3, 5, 12, 0, 0), MISCREG_VBAR_EL12 },
1182  { MiscRegNum64(3, 5, 13, 0, 1), MISCREG_CONTEXTIDR_EL12 },
1183  { MiscRegNum64(3, 5, 14, 1, 0), MISCREG_CNTKCTL_EL12 },
1184  { MiscRegNum64(3, 5, 14, 2, 0), MISCREG_CNTP_TVAL_EL02 },
1185  { MiscRegNum64(3, 5, 14, 2, 1), MISCREG_CNTP_CTL_EL02 },
1186  { MiscRegNum64(3, 5, 14, 2, 2), MISCREG_CNTP_CVAL_EL02 },
1187  { MiscRegNum64(3, 5, 14, 3, 0), MISCREG_CNTV_TVAL_EL02 },
1188  { MiscRegNum64(3, 5, 14, 3, 1), MISCREG_CNTV_CTL_EL02 },
1189  { MiscRegNum64(3, 5, 14, 3, 2), MISCREG_CNTV_CVAL_EL02 },
1190  { MiscRegNum64(3, 6, 1, 0, 0), MISCREG_SCTLR_EL3 },
1191  { MiscRegNum64(3, 6, 1, 0, 1), MISCREG_ACTLR_EL3 },
1192  { MiscRegNum64(3, 6, 1, 1, 0), MISCREG_SCR_EL3 },
1193  { MiscRegNum64(3, 6, 1, 1, 1), MISCREG_SDER32_EL3 },
1194  { MiscRegNum64(3, 6, 1, 1, 2), MISCREG_CPTR_EL3 },
1195  { MiscRegNum64(3, 6, 1, 2, 0), MISCREG_ZCR_EL3 },
1196  { MiscRegNum64(3, 6, 1, 3, 1), MISCREG_MDCR_EL3 },
1197  { MiscRegNum64(3, 6, 2, 0, 0), MISCREG_TTBR0_EL3 },
1198  { MiscRegNum64(3, 6, 2, 0, 2), MISCREG_TCR_EL3 },
1199  { MiscRegNum64(3, 6, 4, 0, 0), MISCREG_SPSR_EL3 },
1200  { MiscRegNum64(3, 6, 4, 0, 1), MISCREG_ELR_EL3 },
1201  { MiscRegNum64(3, 6, 4, 1, 0), MISCREG_SP_EL2 },
1202  { MiscRegNum64(3, 6, 5, 1, 0), MISCREG_AFSR0_EL3 },
1203  { MiscRegNum64(3, 6, 5, 1, 1), MISCREG_AFSR1_EL3 },
1204  { MiscRegNum64(3, 6, 5, 2, 0), MISCREG_ESR_EL3 },
1205  { MiscRegNum64(3, 6, 6, 0, 0), MISCREG_FAR_EL3 },
1206  { MiscRegNum64(3, 6, 10, 2, 0), MISCREG_MAIR_EL3 },
1207  { MiscRegNum64(3, 6, 10, 3, 0), MISCREG_AMAIR_EL3 },
1208  { MiscRegNum64(3, 6, 12, 0, 0), MISCREG_VBAR_EL3 },
1209  { MiscRegNum64(3, 6, 12, 0, 1), MISCREG_RVBAR_EL3 },
1210  { MiscRegNum64(3, 6, 12, 0, 2), MISCREG_RMR_EL3 },
1211  { MiscRegNum64(3, 6, 12, 12, 4), MISCREG_ICC_CTLR_EL3 },
1212  { MiscRegNum64(3, 6, 12, 12, 5), MISCREG_ICC_SRE_EL3 },
1213  { MiscRegNum64(3, 6, 12, 12, 7), MISCREG_ICC_IGRPEN1_EL3 },
1214  { MiscRegNum64(3, 6, 13, 0, 2), MISCREG_TPIDR_EL3 },
1215  { MiscRegNum64(3, 7, 14, 2, 0), MISCREG_CNTPS_TVAL_EL1 },
1216  { MiscRegNum64(3, 7, 14, 2, 1), MISCREG_CNTPS_CTL_EL1 },
1217  { MiscRegNum64(3, 7, 14, 2, 2), MISCREG_CNTPS_CVAL_EL1 }
1218 };
1219 
1220 Fault
1221 faultSpEL0(const MiscRegLUTEntry &entry, ThreadContext *tc,
1222  const MiscRegOp64 &inst)
1223 {
1224  if (tc->readMiscReg(MISCREG_SPSEL) == 0)
1225  return inst.undefined();
1226  else
1227  return NoFault;
1228 }
1229 
1230 Fault
1231 faultDaif(const MiscRegLUTEntry &entry, ThreadContext *tc,
1232  const MiscRegOp64 &inst)
1233 {
1234  const bool el2_enabled = EL2Enabled(tc);
1235  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1236  const SCTLR sctlr = tc->readMiscRegNoEffect(MISCREG_SCTLR_EL1);
1237  if ((el2_enabled && hcr.e2h && hcr.tge) || sctlr.uma == 0) {
1238  if (el2_enabled && hcr.tge) {
1239  return inst.generateTrap(EL2);
1240  } else {
1241  return inst.generateTrap(EL1);
1242  }
1243  } else {
1244  return NoFault;
1245  }
1246 }
1247 
1248 Fault
1249 faultDczvaEL0(const MiscRegLUTEntry &entry, ThreadContext *tc,
1250  const MiscRegOp64 &inst)
1251 {
1252  if (!FullSystem)
1253  return NoFault;
1254 
1255  const SCTLR sctlr = tc->readMiscRegNoEffect(MISCREG_SCTLR_EL1);
1256  const SCTLR sctlr2 = tc->readMiscRegNoEffect(MISCREG_SCTLR_EL2);
1257  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1258 
1259  const bool el2_enabled = EL2Enabled(tc);
1260  const bool in_host = hcr.e2h && hcr.tge;
1261  if (!(el2_enabled && in_host) && !sctlr.dze) {
1262  if (el2_enabled && hcr.tge) {
1263  return inst.generateTrap(EL2);
1264  } else {
1265  return inst.generateTrap(EL1);
1266  }
1267  } else if (el2_enabled && !in_host && hcr.tdz) {
1268  return inst.generateTrap(EL2);
1269  } else if (el2_enabled && in_host && !sctlr2.dze) {
1270  return inst.generateTrap(EL2);
1271  } else {
1272  return NoFault;
1273  }
1274 }
1275 
1276 Fault
1277 faultCvacEL0(const MiscRegLUTEntry &entry, ThreadContext *tc,
1278  const MiscRegOp64 &inst)
1279 {
1280  const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1281  const SCTLR sctlr2 = tc->readMiscReg(MISCREG_SCTLR_EL2);
1282  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1283 
1284  const bool el2_enabled = EL2Enabled(tc);
1285  const bool in_host = hcr.e2h && hcr.tge;
1286  if (!(el2_enabled && in_host) && !sctlr.uci) {
1287  if (el2_enabled && hcr.tge) {
1288  return inst.generateTrap(EL2);
1289  } else {
1290  return inst.generateTrap(EL1);
1291  }
1292  } else if (el2_enabled && !in_host && hcr.tpc) {
1293  return inst.generateTrap(EL2);
1294  } else if (el2_enabled && in_host && !sctlr2.uci) {
1295  return inst.generateTrap(EL2);
1296  } else {
1297  return NoFault;
1298  }
1299 }
1300 
1301 Fault
1302 faultFpcrEL0(const MiscRegLUTEntry &entry, ThreadContext *tc,
1303  const MiscRegOp64 &inst)
1304 {
1305  const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
1306  const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
1307  const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1308 
1309  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1310  const bool el2_enabled = EL2Enabled(tc);
1311  const bool in_host = hcr.e2h && hcr.tge;
1312  if (!(el2_enabled && in_host) && cpacr.fpen != 0b11) {
1313  if (el2_enabled && hcr.tge) {
1314  return inst.generateTrap(EL2, ExceptionClass::UNKNOWN, inst.iss());
1315  } else {
1316  return inst.generateTrap(EL1,
1317  ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1318  }
1319  } else if (el2_enabled && in_host && cptr_el2.fpen != 0b11) {
1320  return inst.generateTrap(EL2,
1321  ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1322  } else if (el2_enabled && hcr.e2h && ((cptr_el2.fpen & 0b1) == 0b0)) {
1323  return inst.generateTrap(EL2,
1324  ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1325  } else if (el2_enabled && !hcr.e2h && cptr_el2.tfp) {
1326  return inst.generateTrap(EL2,
1327  ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1328  } else if (ArmSystem::haveEL(tc, EL3) && cptr_el3.tfp) {
1329  return inst.generateTrap(EL3,
1330  ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1331  } else {
1332  return NoFault;
1333  }
1334 }
1335 
1336 Fault
1337 faultFpcrEL1(const MiscRegLUTEntry &entry, ThreadContext *tc,
1338  const MiscRegOp64 &inst)
1339 {
1340  const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
1341  const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
1342  const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1343 
1344  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1345  const bool el2_enabled = EL2Enabled(tc);
1346  if ((cpacr.fpen & 0b1) == 0b0) {
1347  return inst.generateTrap(EL1,
1348  ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1349  } else if (el2_enabled && !hcr.e2h && cptr_el2.tfp) {
1350  return inst.generateTrap(EL2,
1351  ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1352  } else if (el2_enabled && hcr.e2h && ((cptr_el2.fpen & 0b1) == 0b0)) {
1353  return inst.generateTrap(EL2,
1354  ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1355  } else if (ArmSystem::haveEL(tc, EL3) && cptr_el3.tfp) {
1356  return inst.generateTrap(EL3,
1357  ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1358  } else {
1359  return NoFault;
1360  }
1361 }
1362 
1363 Fault
1364 faultFpcrEL2(const MiscRegLUTEntry &entry, ThreadContext *tc,
1365  const MiscRegOp64 &inst)
1366 {
1367  const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
1368  const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1369 
1370  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1371  if (!hcr.e2h && cptr_el2.tfp) {
1372  return inst.generateTrap(EL2,
1373  ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1374  } else if (hcr.e2h && ((cptr_el2.fpen & 0b1) == 0b0)) {
1375  return inst.generateTrap(EL2,
1376  ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1377  } else if (ArmSystem::haveEL(tc, EL3) && cptr_el3.tfp) {
1378  return inst.generateTrap(EL3,
1379  ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1380  } else {
1381  return NoFault;
1382  }
1383 }
1384 
1385 Fault
1386 faultFpcrEL3(const MiscRegLUTEntry &entry,
1387  ThreadContext *tc, const MiscRegOp64 &inst)
1388 {
1389  const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1390  if (cptr_el3.tfp) {
1391  return inst.generateTrap(EL3,
1392  ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1393  } else {
1394  return NoFault;
1395  }
1396 }
1397 
1398 Fault
1399 faultPouEL0(const MiscRegLUTEntry &entry,
1400  ThreadContext *tc, const MiscRegOp64 &inst)
1401 {
1402  const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1403  const SCTLR sctlr2 = tc->readMiscReg(MISCREG_SCTLR_EL2);
1404  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1405 
1406  const bool el2_enabled = EL2Enabled(tc);
1407  const bool in_host = hcr.e2h && hcr.tge;
1408  if (!(el2_enabled && in_host) && !sctlr.uci) {
1409  if (el2_enabled && hcr.tge) {
1410  return inst.generateTrap(EL2);
1411  } else {
1412  return inst.generateTrap(EL1);
1413  }
1414  } else if (el2_enabled && !in_host && hcr.tpu) {
1415  return inst.generateTrap(EL2);
1416  } else if (el2_enabled && !in_host && hcr.tocu) {
1417  return inst.generateTrap(EL2);
1418  } else if (el2_enabled && in_host && !sctlr2.uci) {
1419  return inst.generateTrap(EL2);
1420  } else {
1421  return NoFault;
1422  }
1423 }
1424 
1425 Fault
1426 faultPouEL1(const MiscRegLUTEntry &entry,
1427  ThreadContext *tc, const MiscRegOp64 &inst)
1428 {
1429  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1430  const bool el2_enabled = EL2Enabled(tc);
1431  if (el2_enabled && hcr.tpu) {
1432  return inst.generateTrap(EL2);
1433  } else if (el2_enabled && hcr.tocu) {
1434  return inst.generateTrap(EL2);
1435  } else {
1436  return NoFault;
1437  }
1438 }
1439 
1440 Fault
1441 faultPouIsEL1(const MiscRegLUTEntry &entry,
1442  ThreadContext *tc, const MiscRegOp64 &inst)
1443 {
1444  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1445  const bool el2_enabled = EL2Enabled(tc);
1446  if (el2_enabled && hcr.tpu) {
1447  return inst.generateTrap(EL2);
1448  } else if (el2_enabled && hcr.ticab) {
1449  return inst.generateTrap(EL2);
1450  } else {
1451  return NoFault;
1452  }
1453 }
1454 
1455 Fault
1456 faultCtrEL0(const MiscRegLUTEntry &entry,
1457  ThreadContext *tc, const MiscRegOp64 &inst)
1458 {
1459  const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1460  const SCTLR sctlr2 = tc->readMiscReg(MISCREG_SCTLR_EL2);
1461  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1462 
1463  const bool el2_enabled = EL2Enabled(tc);
1464  const bool in_host = hcr.e2h && hcr.tge;
1465  if (!(el2_enabled && in_host) && !sctlr.uct) {
1466  if (el2_enabled && hcr.tge) {
1467  return inst.generateTrap(EL2);
1468  } else {
1469  return inst.generateTrap(EL1);
1470  }
1471  } else if (el2_enabled && !in_host && hcr.tid2) {
1472  return inst.generateTrap(EL2);
1473  } else if (el2_enabled && in_host && !sctlr2.uct) {
1474  return inst.generateTrap(EL2);
1475  } else {
1476  return NoFault;
1477  }
1478 }
1479 
1480 Fault
1481 faultMdccsrEL0(const MiscRegLUTEntry &entry,
1482  ThreadContext *tc, const MiscRegOp64 &inst)
1483 {
1484  const DBGDS32 mdscr = tc->readMiscReg(MISCREG_MDSCR_EL1);
1485  const HDCR mdcr_el2 = tc->readMiscReg(MISCREG_MDCR_EL2);
1486  const HDCR mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
1487 
1488  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1489  const bool el2_enabled = EL2Enabled(tc);
1490  if (mdscr.tdcc) {
1491  if (el2_enabled && hcr.tge) {
1492  return inst.generateTrap(EL2);
1493  } else {
1494  return inst.generateTrap(EL1);
1495  }
1496  } else if (el2_enabled && mdcr_el2.tdcc) {
1497  return inst.generateTrap(EL2);
1498  } else if (el2_enabled && (hcr.tge || (mdcr_el2.tde || mdcr_el2.tda))) {
1499  return inst.generateTrap(EL2);
1500  } else if (ArmSystem::haveEL(tc, EL3) && (mdcr_el3.tdcc || mdcr_el3.tda)) {
1501  return inst.generateTrap(EL3);
1502  } else {
1503  return NoFault;
1504  }
1505 }
1506 
1507 Fault
1508 faultMdccsrEL1(const MiscRegLUTEntry &entry,
1509  ThreadContext *tc, const MiscRegOp64 &inst)
1510 {
1511  const HDCR mdcr_el2 = tc->readMiscReg(MISCREG_MDCR_EL2);
1512  const HDCR mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
1513 
1514  const bool el2_enabled = EL2Enabled(tc);
1515  if (el2_enabled && mdcr_el2.tdcc) {
1516  return inst.generateTrap(EL2);
1517  } else if (el2_enabled && (mdcr_el2.tde || mdcr_el2.tda)) {
1518  return inst.generateTrap(EL2);
1519  } else if (ArmSystem::haveEL(tc, EL3) && (mdcr_el3.tdcc || mdcr_el3.tda)) {
1520  return inst.generateTrap(EL3);
1521  } else {
1522  return NoFault;
1523  }
1524 }
1525 
1526 Fault
1527 faultMdccsrEL2(const MiscRegLUTEntry &entry,
1528  ThreadContext *tc, const MiscRegOp64 &inst)
1529 {
1530  const HDCR mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
1531  if (ArmSystem::haveEL(tc, EL3) && (mdcr_el3.tdcc || mdcr_el3.tda)) {
1532  return inst.generateTrap(EL3);
1533  } else {
1534  return NoFault;
1535  }
1536 }
1537 
1538 Fault
1539 faultDebugEL1(const MiscRegLUTEntry &entry,
1540  ThreadContext *tc, const MiscRegOp64 &inst)
1541 {
1542  const HDCR mdcr_el2 = tc->readMiscReg(MISCREG_MDCR_EL2);
1543  const HDCR mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
1544 
1545  const bool el2_enabled = EL2Enabled(tc);
1546  if (el2_enabled && (mdcr_el2.tde || mdcr_el2.tda)) {
1547  return inst.generateTrap(EL2);
1548  } else if (ArmSystem::haveEL(tc, EL3) && mdcr_el3.tda) {
1549  return inst.generateTrap(EL3);
1550  } else {
1551  return NoFault;
1552  }
1553 }
1554 
1555 Fault
1556 faultDebugEL2(const MiscRegLUTEntry &entry,
1557  ThreadContext *tc, const MiscRegOp64 &inst)
1558 {
1559  const HDCR mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
1560  if (ArmSystem::haveEL(tc, EL3) && mdcr_el3.tda) {
1561  return inst.generateTrap(EL3);
1562  } else {
1563  return NoFault;
1564  }
1565 }
1566 
1567 Fault
1568 faultZcrEL1(const MiscRegLUTEntry &entry,
1569  ThreadContext *tc, const MiscRegOp64 &inst)
1570 {
1571  const CPACR cpacr_el1 = tc->readMiscReg(MISCREG_CPACR_EL1);
1572  const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
1573  const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1574 
1575  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1576  const bool el2_enabled = EL2Enabled(tc);
1577  if (!(cpacr_el1.zen & 0x1)) {
1578  return inst.generateTrap(EL1, ExceptionClass::TRAPPED_SVE, 0);
1579  } else if (el2_enabled && !hcr.e2h && cptr_el2.tz) {
1580  return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SVE, 0);
1581  } else if (el2_enabled && hcr.e2h && !(cptr_el2.zen & 0x1)) {
1582  return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SVE, 0);
1583  } else if (ArmSystem::haveEL(tc, EL3) && !cptr_el3.ez) {
1584  return inst.generateTrap(EL3, ExceptionClass::TRAPPED_SVE, 0);
1585  } else {
1586  return NoFault;
1587  }
1588 }
1589 
1590 Fault
1591 faultZcrEL2(const MiscRegLUTEntry &entry,
1592  ThreadContext *tc, const MiscRegOp64 &inst)
1593 {
1594  const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
1595  const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1596 
1597  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1598  if (!hcr.e2h && cptr_el2.tz) {
1599  return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SVE, 0);
1600  } else if (hcr.e2h && !(cptr_el2.zen & 0x1)) {
1601  return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SVE, 0);
1602  } else if (ArmSystem::haveEL(tc, EL3) && !cptr_el3.ez) {
1603  return inst.generateTrap(EL3, ExceptionClass::TRAPPED_SVE, 0);
1604  } else {
1605  return NoFault;
1606  }
1607 }
1608 
1609 Fault
1610 faultZcrEL3(const MiscRegLUTEntry &entry,
1611  ThreadContext *tc, const MiscRegOp64 &inst)
1612 {
1613  const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1614  if (!cptr_el3.ez) {
1615  return inst.generateTrap(EL3, ExceptionClass::TRAPPED_SVE, 0);
1616  } else {
1617  return NoFault;
1618  }
1619 }
1620 
1621 Fault
1622 faultGicv3(const MiscRegLUTEntry &entry,
1623  ThreadContext *tc, const MiscRegOp64 &inst)
1624 {
1625  auto gic = static_cast<ArmSystem*>(tc->getSystemPtr())->getGIC();
1626  if (!gic->supportsVersion(BaseGic::GicVersion::GIC_V3)) {
1627  return inst.undefined();
1628  } else {
1629  return NoFault;
1630  }
1631 }
1632 
1633 Fault
1634 faultIccSgiEL1(const MiscRegLUTEntry &entry,
1635  ThreadContext *tc, const MiscRegOp64 &inst)
1636 {
1637  if (auto fault = faultGicv3(entry, tc, inst); fault != NoFault) {
1638  return fault;
1639  }
1640 
1641  const Gicv3CPUInterface::ICH_HCR_EL2 ich_hcr =
1642  tc->readMiscReg(MISCREG_ICH_HCR_EL2);
1643  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1644  const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
1645  if (EL2Enabled(tc) && (hcr.fmo || hcr.imo || ich_hcr.TC)) {
1646  return inst.generateTrap(EL2);
1647  } else if (ArmSystem::haveEL(tc, EL3) && scr.irq && scr.fiq) {
1648  return inst.generateTrap(EL3);
1649  } else {
1650  return NoFault;
1651  }
1652 }
1653 
1654 Fault
1655 faultIccSgiEL2(const MiscRegLUTEntry &entry,
1656  ThreadContext *tc, const MiscRegOp64 &inst)
1657 {
1658  if (auto fault = faultGicv3(entry, tc, inst); fault != NoFault) {
1659  return fault;
1660  }
1661 
1662  const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
1663  if (ArmSystem::haveEL(tc, EL3) && scr.irq && scr.fiq) {
1664  return inst.generateTrap(EL3);
1665  } else {
1666  return NoFault;
1667  }
1668 }
1669 
1670 Fault
1671 faultCpacrEL1(const MiscRegLUTEntry &entry,
1672  ThreadContext *tc, const MiscRegOp64 &inst)
1673 {
1674  const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
1675  const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1676  if (EL2Enabled(tc) && cptr_el2.tcpac) {
1677  return inst.generateTrap(EL2);
1678  } else if (ArmSystem::haveEL(tc, EL3) && cptr_el3.tcpac) {
1679  return inst.generateTrap(EL3);
1680  } else {
1681  return NoFault;
1682  }
1683 }
1684 
1685 Fault
1686 faultCpacrEL2(const MiscRegLUTEntry &entry,
1687  ThreadContext *tc, const MiscRegOp64 &inst)
1688 {
1689  const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1690  if (ArmSystem::haveEL(tc, EL3) && cptr_el3.tcpac) {
1691  return inst.generateTrap(EL3);
1692  } else {
1693  return NoFault;
1694  }
1695 }
1696 
1697 Fault
1698 faultCpacrVheEL2(const MiscRegLUTEntry &entry,
1699  ThreadContext *tc, const MiscRegOp64 &inst)
1700 {
1701  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1702  if (hcr.e2h) {
1703  return faultCpacrEL2(entry, tc, inst);
1704  } else {
1705  return inst.undefined();
1706  }
1707 }
1708 
1709 #define HCR_TRAP(bitfield) [] (const MiscRegLUTEntry &entry, \
1710  ThreadContext *tc, const MiscRegOp64 &inst) -> Fault \
1711 { \
1712  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); \
1713  if (EL2Enabled(tc) && hcr.bitfield) { \
1714  return inst.generateTrap(EL2); \
1715  } else { \
1716  return NoFault; \
1717  } \
1718 }
1719 
1720 Fault
1721 faultPauthEL1(const MiscRegLUTEntry &entry,
1722  ThreadContext *tc, const MiscRegOp64 &inst)
1723 {
1724  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1725  const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
1726  if (EL2Enabled(tc) && !hcr.apk) {
1727  return inst.generateTrap(EL2);
1728  } else if (ArmSystem::haveEL(tc, EL3) && !scr.apk) {
1729  return inst.generateTrap(EL3);
1730  } else {
1731  return NoFault;
1732  }
1733 }
1734 
1735 Fault
1736 faultPauthEL2(const MiscRegLUTEntry &entry,
1737  ThreadContext *tc, const MiscRegOp64 &inst)
1738 {
1739  const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
1740  if (ArmSystem::haveEL(tc, EL3) && !scr.apk) {
1741  return inst.generateTrap(EL3);
1742  } else {
1743  return NoFault;
1744  }
1745 }
1746 
1747 Fault
1748 faultGenericTimerEL0(const MiscRegLUTEntry &entry,
1749  ThreadContext *tc, const MiscRegOp64 &inst)
1750 {
1751  const bool el2_enabled = EL2Enabled(tc);
1752  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1753  const bool in_host = el2_enabled && hcr.e2h && hcr.tge;
1754  const CNTKCTL cntkctl_el1 = tc->readMiscReg(MISCREG_CNTKCTL_EL1);
1755  const CNTHCTL_E2H cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1756  if (!(in_host) && !cntkctl_el1.el0pcten && !cntkctl_el1.el0vcten) {
1757  if (el2_enabled && hcr.tge)
1758  return inst.generateTrap(EL2);
1759  else
1760  return inst.generateTrap(EL1);
1761  } else if (in_host && !cnthctl_el2.el0pcten && !cnthctl_el2.el0vcten) {
1762  return inst.generateTrap(EL2);
1763  } else {
1764  return NoFault;
1765  }
1766 }
1767 
1768 Fault
1769 faultCntpctEL0(const MiscRegLUTEntry &entry,
1770  ThreadContext *tc, const MiscRegOp64 &inst)
1771 {
1772  const bool el2_enabled = EL2Enabled(tc);
1773  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1774  const bool in_host = el2_enabled && hcr.e2h && hcr.tge;
1775  const CNTKCTL cntkctl_el1 = tc->readMiscReg(MISCREG_CNTKCTL_EL1);
1776  const RegVal cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1777  if (!(in_host) && !cntkctl_el1.el0pcten) {
1778  if (el2_enabled && hcr.tge)
1779  return inst.generateTrap(EL2);
1780  else
1781  return inst.generateTrap(EL1);
1782  } else if (el2_enabled && !hcr.e2h &&
1783  !static_cast<CNTHCTL>(cnthctl_el2).el1pcten) {
1784  return inst.generateTrap(EL2);
1785  } else if (el2_enabled && hcr.e2h && !hcr.tge &&
1786  !static_cast<CNTHCTL_E2H>(cnthctl_el2).el1pcten) {
1787  return inst.generateTrap(EL2);
1788  } else if (in_host &&
1789  !static_cast<CNTHCTL_E2H>(cnthctl_el2).el0pcten) {
1790  return inst.generateTrap(EL2);
1791  } else {
1792  return NoFault;
1793  }
1794 }
1795 
1796 Fault
1797 faultCntpctEL1(const MiscRegLUTEntry &entry,
1798  ThreadContext *tc, const MiscRegOp64 &inst)
1799 {
1800  const bool el2_enabled = EL2Enabled(tc);
1801  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1802  const RegVal cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1803  if (el2_enabled && hcr.e2h &&
1804  !static_cast<CNTHCTL_E2H>(cnthctl_el2).el1pcten) {
1805  return inst.generateTrap(EL2);
1806  } else if (el2_enabled && !hcr.e2h &&
1807  !static_cast<CNTHCTL>(cnthctl_el2).el1pcten) {
1808  return inst.generateTrap(EL2);
1809  } else {
1810  return NoFault;
1811  }
1812 }
1813 
1814 Fault
1815 faultCntvctEL0(const MiscRegLUTEntry &entry,
1816  ThreadContext *tc, const MiscRegOp64 &inst)
1817 {
1818  const bool el2_enabled = EL2Enabled(tc);
1819  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1820  const bool in_host = el2_enabled && hcr.e2h && hcr.tge;
1821  const CNTKCTL cntkctl_el1 = tc->readMiscReg(MISCREG_CNTKCTL_EL1);
1822  const CNTHCTL_E2H cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1823  if (!(in_host) && !cntkctl_el1.el0vcten) {
1824  if (el2_enabled && hcr.tge)
1825  return inst.generateTrap(EL2);
1826  else
1827  return inst.generateTrap(EL1);
1828  } else if (in_host && !cnthctl_el2.el0vcten) {
1829  return inst.generateTrap(EL2);
1830  } else if (el2_enabled && !(hcr.e2h && hcr.tge) && cnthctl_el2.el1tvct) {
1831  return inst.generateTrap(EL2);
1832  } else {
1833  return NoFault;
1834  }
1835 }
1836 
1837 Fault
1838 faultCntvctEL1(const MiscRegLUTEntry &entry,
1839  ThreadContext *tc, const MiscRegOp64 &inst)
1840 {
1841  const CNTHCTL cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1842  if (EL2Enabled(tc) && cnthctl_el2.el1tvct) {
1843  return inst.generateTrap(EL2);
1844  } else {
1845  return NoFault;
1846  }
1847 }
1848 
1849 //TODO: See faultCntpctEL0
1850 Fault
1851 faultCntpCtlEL0(const MiscRegLUTEntry &entry,
1852  ThreadContext *tc, const MiscRegOp64 &inst)
1853 {
1854  const bool el2_enabled = EL2Enabled(tc);
1855  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1856  const bool in_host = el2_enabled && hcr.e2h && hcr.tge;
1857  const CNTKCTL cntkctl_el1 = tc->readMiscReg(MISCREG_CNTKCTL_EL1);
1858  const RegVal cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1859  if (!(in_host) && !cntkctl_el1.el0pten) {
1860  if (el2_enabled && hcr.tge)
1861  return inst.generateTrap(EL2);
1862  else
1863  return inst.generateTrap(EL1);
1864  } else if (el2_enabled && !hcr.e2h &&
1865  !static_cast<CNTHCTL>(cnthctl_el2).el1pcen) {
1866  return inst.generateTrap(EL2);
1867  } else if (el2_enabled && hcr.e2h && !hcr.tge &&
1868  !static_cast<CNTHCTL_E2H>(cnthctl_el2).el1pten) {
1869  return inst.generateTrap(EL2);
1870  } else if (in_host &&
1871  !static_cast<CNTHCTL_E2H>(cnthctl_el2).el0pten) {
1872  return inst.generateTrap(EL2);
1873  } else {
1874  return NoFault;
1875  }
1876 }
1877 
1878 Fault
1879 faultCntpCtlEL1(const MiscRegLUTEntry &entry,
1880  ThreadContext *tc, const MiscRegOp64 &inst)
1881 {
1882  const bool el2_enabled = EL2Enabled(tc);
1883  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1884  const RegVal cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1885  if (el2_enabled && !hcr.e2h &&
1886  !static_cast<CNTHCTL>(cnthctl_el2).el1pcen) {
1887  return inst.generateTrap(EL2);
1888  } else if (el2_enabled && hcr.e2h &&
1889  !static_cast<CNTHCTL_E2H>(cnthctl_el2).el1pten) {
1890  return inst.generateTrap(EL2);
1891  } else {
1892  return NoFault;
1893  }
1894 }
1895 
1896 // TODO: see faultCntvctEL0
1897 Fault
1898 faultCntvCtlEL0(const MiscRegLUTEntry &entry,
1899  ThreadContext *tc, const MiscRegOp64 &inst)
1900 {
1901  const bool el2_enabled = EL2Enabled(tc);
1902  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1903  const bool in_host = el2_enabled && hcr.e2h && hcr.tge;
1904  const CNTKCTL cntkctl_el1 = tc->readMiscReg(MISCREG_CNTKCTL_EL1);
1905  const CNTHCTL_E2H cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1906  if (!(in_host) && !cntkctl_el1.el0vten) {
1907  if (el2_enabled && hcr.tge)
1908  return inst.generateTrap(EL2);
1909  else
1910  return inst.generateTrap(EL1);
1911  } else if (in_host && !cnthctl_el2.el0vten) {
1912  return inst.generateTrap(EL2);
1913  } else if (el2_enabled && !(hcr.e2h && hcr.tge) && cnthctl_el2.el1tvt) {
1914  return inst.generateTrap(EL2);
1915  } else {
1916  return NoFault;
1917  }
1918 }
1919 
1920 Fault
1921 faultCntvCtlEL1(const MiscRegLUTEntry &entry,
1922  ThreadContext *tc, const MiscRegOp64 &inst)
1923 {
1924  const CNTHCTL cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1925  if (EL2Enabled(tc) && cnthctl_el2.el1tvt) {
1926  return inst.generateTrap(EL2);
1927  } else {
1928  return NoFault;
1929  }
1930 }
1931 
1932 Fault
1933 faultCntpsCtlEL1(const MiscRegLUTEntry &entry,
1934  ThreadContext *tc, const MiscRegOp64 &inst)
1935 {
1936  const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
1937  if (ArmSystem::haveEL(tc, EL3) && !scr.ns) {
1938  if (scr.eel2)
1939  return inst.undefined();
1940  else if (!scr.st)
1941  return inst.generateTrap(EL3);
1942  else
1943  return NoFault;
1944  } else {
1945  return inst.undefined();
1946  }
1947 }
1948 
1949 Fault
1950 faultUnimplemented(const MiscRegLUTEntry &entry,
1951  ThreadContext *tc, const MiscRegOp64 &inst)
1952 {
1953  if (entry.info[MISCREG_WARN_NOT_FAIL]) {
1954  return NoFault;
1955  } else {
1956  return inst.undefined();
1957  }
1958 }
1959 
1960 Fault
1961 faultImpdefUnimplEL1(const MiscRegLUTEntry &entry,
1962  ThreadContext *tc, const MiscRegOp64 &inst)
1963 {
1964  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1965  if (EL2Enabled(tc) && hcr.tidcp) {
1966  return inst.generateTrap(EL2);
1967  } else {
1968  return faultUnimplemented(entry, tc, inst);
1969  }
1970 }
1971 
1972 }
1973 
1974 MiscRegIndex
1975 decodeAArch64SysReg(unsigned op0, unsigned op1,
1976  unsigned crn, unsigned crm,
1977  unsigned op2)
1978 {
1979  MiscRegNum64 sys_reg(op0, op1, crn, crm, op2);
1980  return decodeAArch64SysReg(sys_reg);
1981 }
1982 
1983 MiscRegIndex
1984 decodeAArch64SysReg(const MiscRegNum64 &sys_reg)
1985 {
1986  auto it = miscRegNumToIdx.find(sys_reg);
1987  if (it != miscRegNumToIdx.end()) {
1988  return it->second;
1989  } else {
1990  // Check for a pseudo register before returning MISCREG_UNKNOWN
1991  if ((sys_reg.op0 == 1 || sys_reg.op0 == 3) &&
1992  (sys_reg.crn == 11 || sys_reg.crn == 15)) {
1993  return MISCREG_IMPDEF_UNIMPL;
1994  } else {
1995  return MISCREG_UNKNOWN;
1996  }
1997  }
1998 }
1999 
2000 MiscRegNum64
2001 encodeAArch64SysReg(MiscRegIndex misc_reg)
2002 {
2003  if (auto it = idxToMiscRegNum.find(misc_reg);
2004  it != idxToMiscRegNum.end()) {
2005  return it->second;
2006  } else {
2007  panic("Invalid MiscRegIndex: %d\n", misc_reg);
2008  }
2009 }
2010 
2011 Fault
2012 MiscRegLUTEntry::checkFault(ThreadContext *tc,
2013  const MiscRegOp64 &inst, ExceptionLevel el)
2014 {
2015  return !inst.miscRead() ? faultWrite[el](*this, tc, inst) :
2016  faultRead[el](*this, tc, inst);
2017 }
2018 
2019 template <MiscRegInfo Sec, MiscRegInfo NonSec>
2020 Fault
2021 MiscRegLUTEntry::defaultFault(const MiscRegLUTEntry &entry,
2022  ThreadContext *tc, const MiscRegOp64 &inst)
2023 {
2024  if (isSecureBelowEL3(tc) ? entry.info[Sec] : entry.info[NonSec]) {
2025  return NoFault;
2026  } else {
2027  return inst.undefined();
2028  }
2029 }
2030 
2031 static Fault
2032 defaultFaultE2H_EL2(const MiscRegLUTEntry &entry,
2033  ThreadContext *tc, const MiscRegOp64 &inst)
2034 {
2035  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
2036  if (hcr.e2h) {
2037  return NoFault;
2038  } else {
2039  return inst.undefined();
2040  }
2041 }
2042 
2043 static Fault
2044 defaultFaultE2H_EL3(const MiscRegLUTEntry &entry,
2045  ThreadContext *tc, const MiscRegOp64 &inst)
2046 {
2047  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
2048  const bool el2_host = EL2Enabled(tc) && hcr.e2h;
2049  if (el2_host) {
2050  return NoFault;
2051  } else {
2052  return inst.undefined();
2053  }
2054 }
2055 
2056 MiscRegLUTEntryInitializer::chain
2057 MiscRegLUTEntryInitializer::highest(ArmSystem *const sys) const
2058 {
2059  switch (FullSystem ? sys->highestEL() : EL1) {
2060  case EL0:
2061  case EL1: priv(); break;
2062  case EL2: hyp(); break;
2063  case EL3: mon(); break;
2064  }
2065  return *this;
2066 }
2067 
2068 
2069 void
2070 ISA::initializeMiscRegMetadata()
2071 {
2072  // the MiscReg metadata tables are shared across all instances of the
2073  // ISA object, so there's no need to initialize them multiple times.
2074  static bool completed = false;
2075  if (completed)
2076  return;
2077 
2078  // This boolean variable specifies if the system is running in aarch32 at
2079  // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
2080  // is running in aarch64 (aarch32EL3 = false)
2081  bool aarch32EL3 = release->has(ArmExtension::SECURITY) && !highestELIs64;
2082 
2083  // Set Privileged Access Never on taking an exception to EL1 (Arm 8.1+),
2084  // unsupported
2085  bool SPAN = false;
2086 
2087  // Implicit error synchronization event enable (Arm 8.2+), unsupported
2088  bool IESB = false;
2089 
2090  // Load Multiple and Store Multiple Atomicity and Ordering (Arm 8.2+),
2091  // unsupported
2092  bool LSMAOE = false;
2093 
2094  // No Trap Load Multiple and Store Multiple (Arm 8.2+), unsupported
2095  bool nTLSMD = false;
2096 
2097  // Pointer authentication (Arm 8.3+), unsupported
2098  bool EnDA = true; // using APDAKey_EL1 key of instr addrs in ELs 0,1
2099  bool EnDB = true; // using APDBKey_EL1 key of instr addrs in ELs 0,1
2100  bool EnIA = true; // using APIAKey_EL1 key of instr addrs in ELs 0,1
2101  bool EnIB = true; // using APIBKey_EL1 key of instr addrs in ELs 0,1
2102 
2103  const bool vhe_implemented = release->has(ArmExtension::FEAT_VHE);
2104  const bool sel2_implemented = release->has(ArmExtension::FEAT_SEL2);
2105 
2106 
2120  InitReg(MISCREG_CPSR)
2121  .allPrivileges();
2122  InitReg(MISCREG_SPSR)
2123  .allPrivileges();
2124  InitReg(MISCREG_SPSR_FIQ)
2125  .allPrivileges();
2126  InitReg(MISCREG_SPSR_IRQ)
2127  .allPrivileges();
2128  InitReg(MISCREG_SPSR_SVC)
2129  .allPrivileges();
2130  InitReg(MISCREG_SPSR_MON)
2131  .allPrivileges();
2132  InitReg(MISCREG_SPSR_ABT)
2133  .allPrivileges();
2134  InitReg(MISCREG_SPSR_HYP)
2135  .allPrivileges();
2136  InitReg(MISCREG_SPSR_UND)
2137  .allPrivileges();
2138  InitReg(MISCREG_ELR_HYP)
2139  .allPrivileges();
2140  InitReg(MISCREG_FPSID)
2141  .allPrivileges();
2142  InitReg(MISCREG_FPSCR)
2143  .allPrivileges();
2144  InitReg(MISCREG_MVFR1)
2145  .allPrivileges();
2146  InitReg(MISCREG_MVFR0)
2147  .allPrivileges();
2148  InitReg(MISCREG_FPEXC)
2149  .allPrivileges();
2150 
2151  // Helper registers
2152  InitReg(MISCREG_CPSR_MODE)
2153  .allPrivileges();
2154  InitReg(MISCREG_CPSR_Q)
2155  .allPrivileges();
2156  InitReg(MISCREG_FPSCR_EXC)
2157  .allPrivileges();
2158  InitReg(MISCREG_FPSCR_QC)
2159  .allPrivileges();
2160  InitReg(MISCREG_LOCKADDR)
2161  .allPrivileges();
2162  InitReg(MISCREG_LOCKFLAG)
2163  .allPrivileges();
2164  InitReg(MISCREG_PRRR_MAIR0)
2165  .mutex()
2166  .banked();
2167  InitReg(MISCREG_PRRR_MAIR0_NS)
2168  .mutex()
2169  .privSecure(!aarch32EL3)
2170  .bankedChild();
2171  InitReg(MISCREG_PRRR_MAIR0_S)
2172  .mutex()
2173  .bankedChild();
2174  InitReg(MISCREG_NMRR_MAIR1)
2175  .mutex()
2176  .banked();
2177  InitReg(MISCREG_NMRR_MAIR1_NS)
2178  .mutex()
2179  .privSecure(!aarch32EL3)
2180  .bankedChild();
2181  InitReg(MISCREG_NMRR_MAIR1_S)
2182  .mutex()
2183  .bankedChild();
2184  InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
2185  .mutex();
2186  InitReg(MISCREG_SCTLR_RST)
2187  .allPrivileges();
2188  InitReg(MISCREG_SEV_MAILBOX)
2189  .allPrivileges();
2190  InitReg(MISCREG_TLBINEEDSYNC)
2191  .allPrivileges().exceptUserMode();
2192 
2193  // AArch32 CP14 registers
2194  InitReg(MISCREG_DBGDIDR)
2195  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2196  InitReg(MISCREG_DBGDSCRint)
2197  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2198  InitReg(MISCREG_DBGDCCINT)
2199  .unimplemented()
2200  .allPrivileges();
2201  InitReg(MISCREG_DBGDTRTXint)
2202  .unimplemented()
2203  .allPrivileges();
2204  InitReg(MISCREG_DBGDTRRXint)
2205  .unimplemented()
2206  .allPrivileges();
2207  InitReg(MISCREG_DBGWFAR)
2208  .unimplemented()
2209  .allPrivileges();
2210  InitReg(MISCREG_DBGVCR)
2211  .allPrivileges().exceptUserMode();
2212  InitReg(MISCREG_DBGDTRRXext)
2213  .unimplemented()
2214  .allPrivileges();
2215  InitReg(MISCREG_DBGDSCRext)
2216  .allPrivileges();
2217  InitReg(MISCREG_DBGDTRTXext)
2218  .unimplemented()
2219  .allPrivileges();
2220  InitReg(MISCREG_DBGOSECCR)
2221  .unimplemented()
2222  .allPrivileges();
2223  InitReg(MISCREG_DBGBVR0)
2224  .allPrivileges().exceptUserMode();
2225  InitReg(MISCREG_DBGBVR1)
2226  .allPrivileges().exceptUserMode();
2227  InitReg(MISCREG_DBGBVR2)
2228  .allPrivileges().exceptUserMode();
2229  InitReg(MISCREG_DBGBVR3)
2230  .allPrivileges().exceptUserMode();
2231  InitReg(MISCREG_DBGBVR4)
2232  .allPrivileges().exceptUserMode();
2233  InitReg(MISCREG_DBGBVR5)
2234  .allPrivileges().exceptUserMode();
2235  InitReg(MISCREG_DBGBVR6)
2236  .allPrivileges().exceptUserMode();
2237  InitReg(MISCREG_DBGBVR7)
2238  .allPrivileges().exceptUserMode();
2239  InitReg(MISCREG_DBGBVR8)
2240  .allPrivileges().exceptUserMode();
2241  InitReg(MISCREG_DBGBVR9)
2242  .allPrivileges().exceptUserMode();
2243  InitReg(MISCREG_DBGBVR10)
2244  .allPrivileges().exceptUserMode();
2245  InitReg(MISCREG_DBGBVR11)
2246  .allPrivileges().exceptUserMode();
2247  InitReg(MISCREG_DBGBVR12)
2248  .allPrivileges().exceptUserMode();
2249  InitReg(MISCREG_DBGBVR13)
2250  .allPrivileges().exceptUserMode();
2251  InitReg(MISCREG_DBGBVR14)
2252  .allPrivileges().exceptUserMode();
2253  InitReg(MISCREG_DBGBVR15)
2254  .allPrivileges().exceptUserMode();
2255  InitReg(MISCREG_DBGBCR0)
2256  .allPrivileges().exceptUserMode();
2257  InitReg(MISCREG_DBGBCR1)
2258  .allPrivileges().exceptUserMode();
2259  InitReg(MISCREG_DBGBCR2)
2260  .allPrivileges().exceptUserMode();
2261  InitReg(MISCREG_DBGBCR3)
2262  .allPrivileges().exceptUserMode();
2263  InitReg(MISCREG_DBGBCR4)
2264  .allPrivileges().exceptUserMode();
2265  InitReg(MISCREG_DBGBCR5)
2266  .allPrivileges().exceptUserMode();
2267  InitReg(MISCREG_DBGBCR6)
2268  .allPrivileges().exceptUserMode();
2269  InitReg(MISCREG_DBGBCR7)
2270  .allPrivileges().exceptUserMode();
2271  InitReg(MISCREG_DBGBCR8)
2272  .allPrivileges().exceptUserMode();
2273  InitReg(MISCREG_DBGBCR9)
2274  .allPrivileges().exceptUserMode();
2275  InitReg(MISCREG_DBGBCR10)
2276  .allPrivileges().exceptUserMode();
2277  InitReg(MISCREG_DBGBCR11)
2278  .allPrivileges().exceptUserMode();
2279  InitReg(MISCREG_DBGBCR12)
2280  .allPrivileges().exceptUserMode();
2281  InitReg(MISCREG_DBGBCR13)
2282  .allPrivileges().exceptUserMode();
2283  InitReg(MISCREG_DBGBCR14)
2284  .allPrivileges().exceptUserMode();
2285  InitReg(MISCREG_DBGBCR15)
2286  .allPrivileges().exceptUserMode();
2287  InitReg(MISCREG_DBGWVR0)
2288  .allPrivileges().exceptUserMode();
2289  InitReg(MISCREG_DBGWVR1)
2290  .allPrivileges().exceptUserMode();
2291  InitReg(MISCREG_DBGWVR2)
2292  .allPrivileges().exceptUserMode();
2293  InitReg(MISCREG_DBGWVR3)
2294  .allPrivileges().exceptUserMode();
2295  InitReg(MISCREG_DBGWVR4)
2296  .allPrivileges().exceptUserMode();
2297  InitReg(MISCREG_DBGWVR5)
2298  .allPrivileges().exceptUserMode();
2299  InitReg(MISCREG_DBGWVR6)
2300  .allPrivileges().exceptUserMode();
2301  InitReg(MISCREG_DBGWVR7)
2302  .allPrivileges().exceptUserMode();
2303  InitReg(MISCREG_DBGWVR8)
2304  .allPrivileges().exceptUserMode();
2305  InitReg(MISCREG_DBGWVR9)
2306  .allPrivileges().exceptUserMode();
2307  InitReg(MISCREG_DBGWVR10)
2308  .allPrivileges().exceptUserMode();
2309  InitReg(MISCREG_DBGWVR11)
2310  .allPrivileges().exceptUserMode();
2311  InitReg(MISCREG_DBGWVR12)
2312  .allPrivileges().exceptUserMode();
2313  InitReg(MISCREG_DBGWVR13)
2314  .allPrivileges().exceptUserMode();
2315  InitReg(MISCREG_DBGWVR14)
2316  .allPrivileges().exceptUserMode();
2317  InitReg(MISCREG_DBGWVR15)
2318  .allPrivileges().exceptUserMode();
2319  InitReg(MISCREG_DBGWCR0)
2320  .allPrivileges().exceptUserMode();
2321  InitReg(MISCREG_DBGWCR1)
2322  .allPrivileges().exceptUserMode();
2323  InitReg(MISCREG_DBGWCR2)
2324  .allPrivileges().exceptUserMode();
2325  InitReg(MISCREG_DBGWCR3)
2326  .allPrivileges().exceptUserMode();
2327  InitReg(MISCREG_DBGWCR4)
2328  .allPrivileges().exceptUserMode();
2329  InitReg(MISCREG_DBGWCR5)
2330  .allPrivileges().exceptUserMode();
2331  InitReg(MISCREG_DBGWCR6)
2332  .allPrivileges().exceptUserMode();
2333  InitReg(MISCREG_DBGWCR7)
2334  .allPrivileges().exceptUserMode();
2335  InitReg(MISCREG_DBGWCR8)
2336  .allPrivileges().exceptUserMode();
2337  InitReg(MISCREG_DBGWCR9)
2338  .allPrivileges().exceptUserMode();
2339  InitReg(MISCREG_DBGWCR10)
2340  .allPrivileges().exceptUserMode();
2341  InitReg(MISCREG_DBGWCR11)
2342  .allPrivileges().exceptUserMode();
2343  InitReg(MISCREG_DBGWCR12)
2344  .allPrivileges().exceptUserMode();
2345  InitReg(MISCREG_DBGWCR13)
2346  .allPrivileges().exceptUserMode();
2347  InitReg(MISCREG_DBGWCR14)
2348  .allPrivileges().exceptUserMode();
2349  InitReg(MISCREG_DBGWCR15)
2350  .allPrivileges().exceptUserMode();
2351  InitReg(MISCREG_DBGDRAR)
2352  .unimplemented()
2353  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2354  InitReg(MISCREG_DBGBXVR0)
2355  .allPrivileges().exceptUserMode();
2356  InitReg(MISCREG_DBGBXVR1)
2357  .allPrivileges().exceptUserMode();
2358  InitReg(MISCREG_DBGBXVR2)
2359  .allPrivileges().exceptUserMode();
2360  InitReg(MISCREG_DBGBXVR3)
2361  .allPrivileges().exceptUserMode();
2362  InitReg(MISCREG_DBGBXVR4)
2363  .allPrivileges().exceptUserMode();
2364  InitReg(MISCREG_DBGBXVR5)
2365  .allPrivileges().exceptUserMode();
2366  InitReg(MISCREG_DBGBXVR0)
2367  .allPrivileges().exceptUserMode();
2368  InitReg(MISCREG_DBGBXVR6)
2369  .allPrivileges().exceptUserMode();
2370  InitReg(MISCREG_DBGBXVR7)
2371  .allPrivileges().exceptUserMode();
2372  InitReg(MISCREG_DBGBXVR8)
2373  .allPrivileges().exceptUserMode();
2374  InitReg(MISCREG_DBGBXVR9)
2375  .allPrivileges().exceptUserMode();
2376  InitReg(MISCREG_DBGBXVR10)
2377  .allPrivileges().exceptUserMode();
2378  InitReg(MISCREG_DBGBXVR11)
2379  .allPrivileges().exceptUserMode();
2380  InitReg(MISCREG_DBGBXVR12)
2381  .allPrivileges().exceptUserMode();
2382  InitReg(MISCREG_DBGBXVR13)
2383  .allPrivileges().exceptUserMode();
2384  InitReg(MISCREG_DBGBXVR14)
2385  .allPrivileges().exceptUserMode();
2386  InitReg(MISCREG_DBGBXVR15)
2387  .allPrivileges().exceptUserMode();
2388  InitReg(MISCREG_DBGOSLAR)
2389  .allPrivileges().monSecureRead(0).monNonSecureRead(0);
2390  InitReg(MISCREG_DBGOSLSR)
2391  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2392  InitReg(MISCREG_DBGOSDLR)
2393  .unimplemented()
2394  .warnNotFail()
2395  .allPrivileges();
2396  InitReg(MISCREG_DBGPRCR)
2397  .unimplemented()
2398  .allPrivileges();
2399  InitReg(MISCREG_DBGDSAR)
2400  .unimplemented()
2401  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2402  InitReg(MISCREG_DBGCLAIMSET)
2403  .unimplemented()
2404  .allPrivileges();
2405  InitReg(MISCREG_DBGCLAIMCLR)
2406  .unimplemented()
2407  .allPrivileges();
2408  InitReg(MISCREG_DBGAUTHSTATUS)
2409  .unimplemented()
2410  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2411  InitReg(MISCREG_DBGDEVID2)
2412  .unimplemented()
2413  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2414  InitReg(MISCREG_DBGDEVID1)
2415  .unimplemented()
2416  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2417  InitReg(MISCREG_DBGDEVID0)
2418  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2419  InitReg(MISCREG_TEECR)
2420  .unimplemented()
2421  .allPrivileges();
2422  InitReg(MISCREG_JIDR)
2423  .allPrivileges();
2424  InitReg(MISCREG_TEEHBR)
2425  .allPrivileges();
2426  InitReg(MISCREG_JOSCR)
2427  .allPrivileges();
2428  InitReg(MISCREG_JMCR)
2429  .allPrivileges();
2430 
2431  // AArch32 CP15 registers
2432  InitReg(MISCREG_MIDR)
2433  .allPrivileges().exceptUserMode().writes(0);
2434  InitReg(MISCREG_CTR)
2435  .allPrivileges().exceptUserMode().writes(0);
2436  InitReg(MISCREG_TCMTR)
2437  .allPrivileges().exceptUserMode().writes(0);
2438  InitReg(MISCREG_TLBTR)
2439  .allPrivileges().exceptUserMode().writes(0);
2440  InitReg(MISCREG_MPIDR)
2441  .allPrivileges().exceptUserMode().writes(0);
2442  InitReg(MISCREG_REVIDR)
2443  .unimplemented()
2444  .warnNotFail()
2445  .allPrivileges().exceptUserMode().writes(0);
2446  InitReg(MISCREG_ID_PFR0)
2447  .allPrivileges().exceptUserMode().writes(0);
2448  InitReg(MISCREG_ID_PFR1)
2449  .allPrivileges().exceptUserMode().writes(0);
2450  InitReg(MISCREG_ID_DFR0)
2451  .allPrivileges().exceptUserMode().writes(0);
2452  InitReg(MISCREG_ID_AFR0)
2453  .allPrivileges().exceptUserMode().writes(0);
2454  InitReg(MISCREG_ID_MMFR0)
2455  .allPrivileges().exceptUserMode().writes(0);
2456  InitReg(MISCREG_ID_MMFR1)
2457  .allPrivileges().exceptUserMode().writes(0);
2458  InitReg(MISCREG_ID_MMFR2)
2459  .allPrivileges().exceptUserMode().writes(0);
2460  InitReg(MISCREG_ID_MMFR3)
2461  .allPrivileges().exceptUserMode().writes(0);
2462  InitReg(MISCREG_ID_MMFR4)
2463  .allPrivileges().exceptUserMode().writes(0);
2464  InitReg(MISCREG_ID_ISAR0)
2465  .allPrivileges().exceptUserMode().writes(0);
2466  InitReg(MISCREG_ID_ISAR1)
2467  .allPrivileges().exceptUserMode().writes(0);
2468  InitReg(MISCREG_ID_ISAR2)
2469  .allPrivileges().exceptUserMode().writes(0);
2470  InitReg(MISCREG_ID_ISAR3)
2471  .allPrivileges().exceptUserMode().writes(0);
2472  InitReg(MISCREG_ID_ISAR4)
2473  .allPrivileges().exceptUserMode().writes(0);
2474  InitReg(MISCREG_ID_ISAR5)
2475  .allPrivileges().exceptUserMode().writes(0);
2476  InitReg(MISCREG_ID_ISAR6)
2477  .allPrivileges().exceptUserMode().writes(0);
2478  InitReg(MISCREG_CCSIDR)
2479  .allPrivileges().exceptUserMode().writes(0);
2480  InitReg(MISCREG_CLIDR)
2481  .allPrivileges().exceptUserMode().writes(0);
2482  InitReg(MISCREG_AIDR)
2483  .allPrivileges().exceptUserMode().writes(0);
2484  InitReg(MISCREG_CSSELR)
2485  .banked();
2486  InitReg(MISCREG_CSSELR_NS)
2487  .bankedChild()
2488  .privSecure(!aarch32EL3)
2489  .nonSecure().exceptUserMode();
2490  InitReg(MISCREG_CSSELR_S)
2491  .bankedChild()
2492  .secure().exceptUserMode();
2493  InitReg(MISCREG_VPIDR)
2494  .hyp().monNonSecure();
2495  InitReg(MISCREG_VMPIDR)
2496  .hyp().monNonSecure();
2497  InitReg(MISCREG_SCTLR)
2498  .banked()
2499  // readMiscRegNoEffect() uses this metadata
2500  // despite using children (below) as backing store
2501  .res0(0x8d22c600)
2502  .res1(0x00400800 | (SPAN ? 0 : 0x800000)
2503  | (LSMAOE ? 0 : 0x10)
2504  | (nTLSMD ? 0 : 0x8));
2505  InitReg(MISCREG_SCTLR_NS)
2506  .bankedChild()
2507  .privSecure(!aarch32EL3)
2508  .nonSecure().exceptUserMode();
2509  InitReg(MISCREG_SCTLR_S)
2510  .bankedChild()
2511  .secure().exceptUserMode();
2512  InitReg(MISCREG_ACTLR)
2513  .banked();
2514  InitReg(MISCREG_ACTLR_NS)
2515  .bankedChild()
2516  .privSecure(!aarch32EL3)
2517  .nonSecure().exceptUserMode();
2518  InitReg(MISCREG_ACTLR_S)
2519  .bankedChild()
2520  .secure().exceptUserMode();
2521  InitReg(MISCREG_CPACR)
2522  .allPrivileges().exceptUserMode();
2523  InitReg(MISCREG_SDCR)
2524  .mon();
2525  InitReg(MISCREG_SCR)
2526  .mon().secure().exceptUserMode()
2527  .res0(0xff40) // [31:16], [6]
2528  .res1(0x0030); // [5:4]
2529  InitReg(MISCREG_SDER)
2530  .mon();
2531  InitReg(MISCREG_NSACR)
2532  .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
2533  InitReg(MISCREG_HSCTLR)
2534  .hyp().monNonSecure()
2535  .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
2536  | (IESB ? 0 : 0x200000)
2537  | (EnDA ? 0 : 0x8000000)
2538  | (EnIB ? 0 : 0x40000000)
2539  | (EnIA ? 0 : 0x80000000))
2540  .res1(0x30c50830);
2541  InitReg(MISCREG_HACTLR)
2542  .hyp().monNonSecure();
2543  InitReg(MISCREG_HCR)
2544  .hyp().monNonSecure()
2545  .res0(0x90000000);
2546  InitReg(MISCREG_HCR2)
2547  .hyp().monNonSecure()
2548  .res0(0xffa9ff8c);
2549  InitReg(MISCREG_HDCR)
2550  .hyp().monNonSecure();
2551  InitReg(MISCREG_HCPTR)
2552  .hyp().monNonSecure();
2553  InitReg(MISCREG_HSTR)
2554  .hyp().monNonSecure();
2555  InitReg(MISCREG_HACR)
2556  .unimplemented()
2557  .warnNotFail()
2558  .hyp().monNonSecure();
2559  InitReg(MISCREG_TTBR0)
2560  .banked();
2561  InitReg(MISCREG_TTBR0_NS)
2562  .bankedChild()
2563  .privSecure(!aarch32EL3)
2564  .nonSecure().exceptUserMode();
2565  InitReg(MISCREG_TTBR0_S)
2566  .bankedChild()
2567  .secure().exceptUserMode();
2568  InitReg(MISCREG_TTBR1)
2569  .banked();
2570  InitReg(MISCREG_TTBR1_NS)
2571  .bankedChild()
2572  .privSecure(!aarch32EL3)
2573  .nonSecure().exceptUserMode();
2574  InitReg(MISCREG_TTBR1_S)
2575  .bankedChild()
2576  .secure().exceptUserMode();
2577  InitReg(MISCREG_TTBCR)
2578  .banked();
2579  InitReg(MISCREG_TTBCR_NS)
2580  .bankedChild()
2581  .privSecure(!aarch32EL3)
2582  .nonSecure().exceptUserMode();
2583  InitReg(MISCREG_TTBCR_S)
2584  .bankedChild()
2585  .secure().exceptUserMode();
2586  InitReg(MISCREG_HTCR)
2587  .hyp().monNonSecure();
2588  InitReg(MISCREG_VTCR)
2589  .hyp().monNonSecure();
2590  InitReg(MISCREG_DACR)
2591  .banked();
2592  InitReg(MISCREG_DACR_NS)
2593  .bankedChild()
2594  .privSecure(!aarch32EL3)
2595  .nonSecure().exceptUserMode();
2596  InitReg(MISCREG_DACR_S)
2597  .bankedChild()
2598  .secure().exceptUserMode();
2599  InitReg(MISCREG_DFSR)
2600  .banked();
2601  InitReg(MISCREG_DFSR_NS)
2602  .bankedChild()
2603  .privSecure(!aarch32EL3)
2604  .nonSecure().exceptUserMode();
2605  InitReg(MISCREG_DFSR_S)
2606  .bankedChild()
2607  .secure().exceptUserMode();
2608  InitReg(MISCREG_IFSR)
2609  .banked();
2610  InitReg(MISCREG_IFSR_NS)
2611  .bankedChild()
2612  .privSecure(!aarch32EL3)
2613  .nonSecure().exceptUserMode();
2614  InitReg(MISCREG_IFSR_S)
2615  .bankedChild()
2616  .secure().exceptUserMode();
2617  InitReg(MISCREG_ADFSR)
2618  .unimplemented()
2619  .warnNotFail()
2620  .banked();
2621  InitReg(MISCREG_ADFSR_NS)
2622  .unimplemented()
2623  .warnNotFail()
2624  .bankedChild()
2625  .privSecure(!aarch32EL3)
2626  .nonSecure().exceptUserMode();
2627  InitReg(MISCREG_ADFSR_S)
2628  .unimplemented()
2629  .warnNotFail()
2630  .bankedChild()
2631  .secure().exceptUserMode();
2632  InitReg(MISCREG_AIFSR)
2633  .unimplemented()
2634  .warnNotFail()
2635  .banked();
2636  InitReg(MISCREG_AIFSR_NS)
2637  .unimplemented()
2638  .warnNotFail()
2639  .bankedChild()
2640  .privSecure(!aarch32EL3)
2641  .nonSecure().exceptUserMode();
2642  InitReg(MISCREG_AIFSR_S)
2643  .unimplemented()
2644  .warnNotFail()
2645  .bankedChild()
2646  .secure().exceptUserMode();
2647  InitReg(MISCREG_HADFSR)
2648  .hyp().monNonSecure();
2649  InitReg(MISCREG_HAIFSR)
2650  .hyp().monNonSecure();
2651  InitReg(MISCREG_HSR)
2652  .hyp().monNonSecure();
2653  InitReg(MISCREG_DFAR)
2654  .banked();
2655  InitReg(MISCREG_DFAR_NS)
2656  .bankedChild()
2657  .privSecure(!aarch32EL3)
2658  .nonSecure().exceptUserMode();
2659  InitReg(MISCREG_DFAR_S)
2660  .bankedChild()
2661  .secure().exceptUserMode();
2662  InitReg(MISCREG_IFAR)
2663  .banked();
2664  InitReg(MISCREG_IFAR_NS)
2665  .bankedChild()
2666  .privSecure(!aarch32EL3)
2667  .nonSecure().exceptUserMode();
2668  InitReg(MISCREG_IFAR_S)
2669  .bankedChild()
2670  .secure().exceptUserMode();
2671  InitReg(MISCREG_HDFAR)
2672  .hyp().monNonSecure();
2673  InitReg(MISCREG_HIFAR)
2674  .hyp().monNonSecure();
2675  InitReg(MISCREG_HPFAR)
2676  .hyp().monNonSecure();
2677  InitReg(MISCREG_ICIALLUIS)
2678  .unimplemented()
2679  .warnNotFail()
2680  .writes(1).exceptUserMode();
2681  InitReg(MISCREG_BPIALLIS)
2682  .unimplemented()
2683  .warnNotFail()
2684  .writes(1).exceptUserMode();
2685  InitReg(MISCREG_PAR)
2686  .banked();
2687  InitReg(MISCREG_PAR_NS)
2688  .bankedChild()
2689  .privSecure(!aarch32EL3)
2690  .nonSecure().exceptUserMode();
2691  InitReg(MISCREG_PAR_S)
2692  .bankedChild()
2693  .secure().exceptUserMode();
2694  InitReg(MISCREG_ICIALLU)
2695  .writes(1).exceptUserMode();
2696  InitReg(MISCREG_ICIMVAU)
2697  .unimplemented()
2698  .warnNotFail()
2699  .writes(1).exceptUserMode();
2700  InitReg(MISCREG_CP15ISB)
2701  .writes(1);
2702  InitReg(MISCREG_BPIALL)
2703  .unimplemented()
2704  .warnNotFail()
2705  .writes(1).exceptUserMode();
2706  InitReg(MISCREG_BPIMVA)
2707  .unimplemented()
2708  .warnNotFail()
2709  .writes(1).exceptUserMode();
2710  InitReg(MISCREG_DCIMVAC)
2711  .unimplemented()
2712  .warnNotFail()
2713  .writes(1).exceptUserMode();
2714  InitReg(MISCREG_DCISW)
2715  .unimplemented()
2716  .warnNotFail()
2717  .writes(1).exceptUserMode();
2718  InitReg(MISCREG_ATS1CPR)
2719  .writes(1).exceptUserMode();
2720  InitReg(MISCREG_ATS1CPW)
2721  .writes(1).exceptUserMode();
2722  InitReg(MISCREG_ATS1CUR)
2723  .writes(1).exceptUserMode();
2724  InitReg(MISCREG_ATS1CUW)
2725  .writes(1).exceptUserMode();
2726  InitReg(MISCREG_ATS12NSOPR)
2727  .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2728  InitReg(MISCREG_ATS12NSOPW)
2729  .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2730  InitReg(MISCREG_ATS12NSOUR)
2731  .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2732  InitReg(MISCREG_ATS12NSOUW)
2733  .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2734  InitReg(MISCREG_DCCMVAC)
2735  .writes(1).exceptUserMode();
2736  InitReg(MISCREG_DCCSW)
2737  .unimplemented()
2738  .warnNotFail()
2739  .writes(1).exceptUserMode();
2740  InitReg(MISCREG_CP15DSB)
2741  .writes(1);
2742  InitReg(MISCREG_CP15DMB)
2743  .writes(1);
2744  InitReg(MISCREG_DCCMVAU)
2745  .unimplemented()
2746  .warnNotFail()
2747  .writes(1).exceptUserMode();
2748  InitReg(MISCREG_DCCIMVAC)
2749  .unimplemented()
2750  .warnNotFail()
2751  .writes(1).exceptUserMode();
2752  InitReg(MISCREG_DCCISW)
2753  .unimplemented()
2754  .warnNotFail()
2755  .writes(1).exceptUserMode();
2756  InitReg(MISCREG_ATS1HR)
2757  .monNonSecureWrite().hypWrite();
2758  InitReg(MISCREG_ATS1HW)
2759  .monNonSecureWrite().hypWrite();
2760  InitReg(MISCREG_TLBIALLIS)
2761  .writes(1).exceptUserMode();
2762  InitReg(MISCREG_TLBIMVAIS)
2763  .writes(1).exceptUserMode();
2764  InitReg(MISCREG_TLBIASIDIS)
2765  .writes(1).exceptUserMode();
2766  InitReg(MISCREG_TLBIMVAAIS)
2767  .writes(1).exceptUserMode();
2768  InitReg(MISCREG_TLBIMVALIS)
2769  .writes(1).exceptUserMode();
2770  InitReg(MISCREG_TLBIMVAALIS)
2771  .writes(1).exceptUserMode();
2772  InitReg(MISCREG_ITLBIALL)
2773  .writes(1).exceptUserMode();
2774  InitReg(MISCREG_ITLBIMVA)
2775  .writes(1).exceptUserMode();
2776  InitReg(MISCREG_ITLBIASID)
2777  .writes(1).exceptUserMode();
2778  InitReg(MISCREG_DTLBIALL)
2779  .writes(1).exceptUserMode();
2780  InitReg(MISCREG_DTLBIMVA)
2781  .writes(1).exceptUserMode();
2782  InitReg(MISCREG_DTLBIASID)
2783  .writes(1).exceptUserMode();
2784  InitReg(MISCREG_TLBIALL)
2785  .writes(1).exceptUserMode();
2786  InitReg(MISCREG_TLBIMVA)
2787  .writes(1).exceptUserMode();
2788  InitReg(MISCREG_TLBIASID)
2789  .writes(1).exceptUserMode();
2790  InitReg(MISCREG_TLBIMVAA)
2791  .writes(1).exceptUserMode();
2792  InitReg(MISCREG_TLBIMVAL)
2793  .writes(1).exceptUserMode();
2794  InitReg(MISCREG_TLBIMVAAL)
2795  .writes(1).exceptUserMode();
2796  InitReg(MISCREG_TLBIIPAS2IS)
2797  .monNonSecureWrite().hypWrite();
2798  InitReg(MISCREG_TLBIIPAS2LIS)
2799  .monNonSecureWrite().hypWrite();
2800  InitReg(MISCREG_TLBIALLHIS)
2801  .monNonSecureWrite().hypWrite();
2802  InitReg(MISCREG_TLBIMVAHIS)
2803  .monNonSecureWrite().hypWrite();
2804  InitReg(MISCREG_TLBIALLNSNHIS)
2805  .monNonSecureWrite().hypWrite();
2806  InitReg(MISCREG_TLBIMVALHIS)
2807  .monNonSecureWrite().hypWrite();
2808  InitReg(MISCREG_TLBIIPAS2)
2809  .monNonSecureWrite().hypWrite();
2810  InitReg(MISCREG_TLBIIPAS2L)
2811  .monNonSecureWrite().hypWrite();
2812  InitReg(MISCREG_TLBIALLH)
2813  .monNonSecureWrite().hypWrite();
2814  InitReg(MISCREG_TLBIMVAH)
2815  .monNonSecureWrite().hypWrite();
2816  InitReg(MISCREG_TLBIALLNSNH)
2817  .monNonSecureWrite().hypWrite();
2818  InitReg(MISCREG_TLBIMVALH)
2819  .monNonSecureWrite().hypWrite();
2820  InitReg(MISCREG_PMCR)
2821  .allPrivileges();
2822  InitReg(MISCREG_PMCNTENSET)
2823  .allPrivileges();
2824  InitReg(MISCREG_PMCNTENCLR)
2825  .allPrivileges();
2826  InitReg(MISCREG_PMOVSR)
2827  .allPrivileges();
2828  InitReg(MISCREG_PMSWINC)
2829  .allPrivileges();
2830  InitReg(MISCREG_PMSELR)
2831  .allPrivileges();
2832  InitReg(MISCREG_PMCEID0)
2833  .allPrivileges();
2834  InitReg(MISCREG_PMCEID1)
2835  .allPrivileges();
2836  InitReg(MISCREG_PMCCNTR)
2837  .allPrivileges();
2838  InitReg(MISCREG_PMXEVTYPER)
2839  .allPrivileges();
2840  InitReg(MISCREG_PMCCFILTR)
2841  .allPrivileges();
2842  InitReg(MISCREG_PMXEVCNTR)
2843  .allPrivileges();
2844  InitReg(MISCREG_PMUSERENR)
2845  .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
2846  InitReg(MISCREG_PMINTENSET)
2847  .allPrivileges().exceptUserMode();
2848  InitReg(MISCREG_PMINTENCLR)
2849  .allPrivileges().exceptUserMode();
2850  InitReg(MISCREG_PMOVSSET)
2851  .unimplemented()
2852  .allPrivileges();
2853  InitReg(MISCREG_L2CTLR)
2854  .allPrivileges().exceptUserMode();
2855  InitReg(MISCREG_L2ECTLR)
2856  .unimplemented()
2857  .allPrivileges().exceptUserMode();
2858  InitReg(MISCREG_PRRR)
2859  .banked();
2860  InitReg(MISCREG_PRRR_NS)
2861  .bankedChild()
2862  .privSecure(!aarch32EL3)
2863  .nonSecure().exceptUserMode();
2864  InitReg(MISCREG_PRRR_S)
2865  .bankedChild()
2866  .secure().exceptUserMode();
2867  InitReg(MISCREG_MAIR0)
2868  .banked();
2869  InitReg(MISCREG_MAIR0_NS)
2870  .bankedChild()
2871  .privSecure(!aarch32EL3)
2872  .nonSecure().exceptUserMode();
2873  InitReg(MISCREG_MAIR0_S)
2874  .bankedChild()
2875  .secure().exceptUserMode();
2876  InitReg(MISCREG_NMRR)
2877  .banked();
2878  InitReg(MISCREG_NMRR_NS)
2879  .bankedChild()
2880  .privSecure(!aarch32EL3)
2881  .nonSecure().exceptUserMode();
2882  InitReg(MISCREG_NMRR_S)
2883  .bankedChild()
2884  .secure().exceptUserMode();
2885  InitReg(MISCREG_MAIR1)
2886  .banked();
2887  InitReg(MISCREG_MAIR1_NS)
2888  .bankedChild()
2889  .privSecure(!aarch32EL3)
2890  .nonSecure().exceptUserMode();
2891  InitReg(MISCREG_MAIR1_S)
2892  .bankedChild()
2893  .secure().exceptUserMode();
2894  InitReg(MISCREG_AMAIR0)
2895  .banked();
2896  InitReg(MISCREG_AMAIR0_NS)
2897  .bankedChild()
2898  .privSecure(!aarch32EL3)
2899  .nonSecure().exceptUserMode();
2900  InitReg(MISCREG_AMAIR0_S)
2901  .bankedChild()
2902  .secure().exceptUserMode();
2903  InitReg(MISCREG_AMAIR1)
2904  .banked();
2905  InitReg(MISCREG_AMAIR1_NS)
2906  .bankedChild()
2907  .privSecure(!aarch32EL3)
2908  .nonSecure().exceptUserMode();
2909  InitReg(MISCREG_AMAIR1_S)
2910  .bankedChild()
2911  .secure().exceptUserMode();
2912  InitReg(MISCREG_HMAIR0)
2913  .hyp().monNonSecure();
2914  InitReg(MISCREG_HMAIR1)
2915  .hyp().monNonSecure();
2916  InitReg(MISCREG_HAMAIR0)
2917  .unimplemented()
2918  .warnNotFail()
2919  .hyp().monNonSecure();
2920  InitReg(MISCREG_HAMAIR1)
2921  .unimplemented()
2922  .warnNotFail()
2923  .hyp().monNonSecure();
2924  InitReg(MISCREG_VBAR)
2925  .banked();
2926  InitReg(MISCREG_VBAR_NS)
2927  .bankedChild()
2928  .privSecure(!aarch32EL3)
2929  .nonSecure().exceptUserMode();
2930  InitReg(MISCREG_VBAR_S)
2931  .bankedChild()
2932  .secure().exceptUserMode();
2933  InitReg(MISCREG_MVBAR)
2934  .mon().secure()
2935  .hypRead(FullSystem && system->highestEL() == EL2)
2936  .privRead(FullSystem && system->highestEL() == EL1)
2937  .exceptUserMode();
2938  InitReg(MISCREG_RMR)
2939  .unimplemented()
2940  .mon().secure().exceptUserMode();
2941  InitReg(MISCREG_ISR)
2942  .allPrivileges().exceptUserMode().writes(0);
2943  InitReg(MISCREG_HVBAR)
2944  .hyp().monNonSecure()
2945  .res0(0x1f);
2946  InitReg(MISCREG_FCSEIDR)
2947  .unimplemented()
2948  .warnNotFail()
2949  .allPrivileges().exceptUserMode();
2950  InitReg(MISCREG_CONTEXTIDR)
2951  .banked();
2952  InitReg(MISCREG_CONTEXTIDR_NS)
2953  .bankedChild()
2954  .privSecure(!aarch32EL3)
2955  .nonSecure().exceptUserMode();
2956  InitReg(MISCREG_CONTEXTIDR_S)
2957  .bankedChild()
2958  .secure().exceptUserMode();
2959  InitReg(MISCREG_TPIDRURW)
2960  .banked();
2961  InitReg(MISCREG_TPIDRURW_NS)
2962  .bankedChild()
2963  .allPrivileges()
2964  .privSecure(!aarch32EL3)
2965  .monSecure(0);
2966  InitReg(MISCREG_TPIDRURW_S)
2967  .bankedChild()
2968  .secure();
2969  InitReg(MISCREG_TPIDRURO)
2970  .banked();
2971  InitReg(MISCREG_TPIDRURO_NS)
2972  .bankedChild()
2973  .allPrivileges()
2974  .userNonSecureWrite(0).userSecureRead(1)
2975  .privSecure(!aarch32EL3)
2976  .monSecure(0);
2977  InitReg(MISCREG_TPIDRURO_S)
2978  .bankedChild()
2979  .secure().userSecureWrite(0);
2980  InitReg(MISCREG_TPIDRPRW)
2981  .banked();
2982  InitReg(MISCREG_TPIDRPRW_NS)
2983  .bankedChild()
2984  .nonSecure().exceptUserMode()
2985  .privSecure(!aarch32EL3);
2986  InitReg(MISCREG_TPIDRPRW_S)
2987  .bankedChild()
2988  .secure().exceptUserMode();
2989  InitReg(MISCREG_HTPIDR)
2990  .hyp().monNonSecure();
2991  // BEGIN Generic Timer (AArch32)
2992  InitReg(MISCREG_CNTFRQ)
2993  .reads(1)
2994  .highest(system)
2995  .privSecureWrite(aarch32EL3);
2996  InitReg(MISCREG_CNTPCT)
2997  .unverifiable()
2998  .reads(1);
2999  InitReg(MISCREG_CNTVCT)
3000  .unverifiable()
3001  .reads(1);
3002  InitReg(MISCREG_CNTP_CTL)
3003  .banked();
3004  InitReg(MISCREG_CNTP_CTL_NS)
3005  .bankedChild()
3006  .nonSecure()
3007  .privSecure(!aarch32EL3)
3008  .userSecureRead(!aarch32EL3)
3009  .userSecureWrite(!aarch32EL3)
3010  .res0(0xfffffff8);
3011  InitReg(MISCREG_CNTP_CTL_S)
3012  .bankedChild()
3013  .secure()
3014  .privSecure(aarch32EL3)
3015  .res0(0xfffffff8);
3016  InitReg(MISCREG_CNTP_CVAL)
3017  .banked();
3018  InitReg(MISCREG_CNTP_CVAL_NS)
3019  .bankedChild()
3020  .nonSecure()
3021  .privSecure(!aarch32EL3)
3022  .userSecureRead(!aarch32EL3)
3023  .userSecureWrite(!aarch32EL3);
3024  InitReg(MISCREG_CNTP_CVAL_S)
3025  .bankedChild()
3026  .secure()
3027  .privSecure(aarch32EL3);
3028  InitReg(MISCREG_CNTP_TVAL)
3029  .banked();
3030  InitReg(MISCREG_CNTP_TVAL_NS)
3031  .bankedChild()
3032  .nonSecure()
3033  .privSecure(!aarch32EL3)
3034  .userSecureRead(!aarch32EL3)
3035  .userSecureWrite(!aarch32EL3);
3036  InitReg(MISCREG_CNTP_TVAL_S)
3037  .bankedChild()
3038  .secure()
3039  .privSecure(aarch32EL3);
3040  InitReg(MISCREG_CNTV_CTL)
3041  .allPrivileges()
3042  .res0(0xfffffff8);
3043  InitReg(MISCREG_CNTV_CVAL)
3044  .allPrivileges();
3045  InitReg(MISCREG_CNTV_TVAL)
3046  .allPrivileges();
3047  InitReg(MISCREG_CNTKCTL)
3048  .allPrivileges()
3049  .exceptUserMode()
3050  .res0(0xfffdfc00);
3051  InitReg(MISCREG_CNTHCTL)
3052  .monNonSecure()
3053  .hyp()
3054  .res0(0xfffdff00);
3055  InitReg(MISCREG_CNTHP_CTL)
3056  .monNonSecure()
3057  .hyp()
3058  .res0(0xfffffff8);
3059  InitReg(MISCREG_CNTHP_CVAL)
3060  .monNonSecure()
3061  .hyp();
3062  InitReg(MISCREG_CNTHP_TVAL)
3063  .monNonSecure()
3064  .hyp();
3065  InitReg(MISCREG_CNTVOFF)
3066  .monNonSecure()
3067  .hyp();
3068  // END Generic Timer (AArch32)
3069  InitReg(MISCREG_IL1DATA0)
3070  .unimplemented()
3071  .allPrivileges().exceptUserMode();
3072  InitReg(MISCREG_IL1DATA1)
3073  .unimplemented()
3074  .allPrivileges().exceptUserMode();
3075  InitReg(MISCREG_IL1DATA2)
3076  .unimplemented()
3077  .allPrivileges().exceptUserMode();
3078  InitReg(MISCREG_IL1DATA3)
3079  .unimplemented()
3080  .allPrivileges().exceptUserMode();
3081  InitReg(MISCREG_DL1DATA0)
3082  .unimplemented()
3083  .allPrivileges().exceptUserMode();
3084  InitReg(MISCREG_DL1DATA1)
3085  .unimplemented()
3086  .allPrivileges().exceptUserMode();
3087  InitReg(MISCREG_DL1DATA2)
3088  .unimplemented()
3089  .allPrivileges().exceptUserMode();
3090  InitReg(MISCREG_DL1DATA3)
3091  .unimplemented()
3092  .allPrivileges().exceptUserMode();
3093  InitReg(MISCREG_DL1DATA4)
3094  .unimplemented()
3095  .allPrivileges().exceptUserMode();
3096  InitReg(MISCREG_RAMINDEX)
3097  .unimplemented()
3098  .writes(1).exceptUserMode();
3099  InitReg(MISCREG_L2ACTLR)
3100  .unimplemented()
3101  .allPrivileges().exceptUserMode();
3102  InitReg(MISCREG_CBAR)
3103  .unimplemented()
3104  .allPrivileges().exceptUserMode().writes(0);
3105  InitReg(MISCREG_HTTBR)
3106  .hyp().monNonSecure();
3107  InitReg(MISCREG_VTTBR)
3108  .hyp().monNonSecure();
3109  InitReg(MISCREG_CPUMERRSR)
3110  .unimplemented()
3111  .allPrivileges().exceptUserMode();
3112  InitReg(MISCREG_L2MERRSR)
3113  .unimplemented()
3114  .warnNotFail()
3115  .allPrivileges().exceptUserMode();
3116 
3117  // AArch64 registers (Op0=2);
3118  InitReg(MISCREG_MDCCINT_EL1)
3119  .fault(EL1, faultMdccsrEL1)
3120  .fault(EL2, faultMdccsrEL2)
3121  .allPrivileges();
3122  InitReg(MISCREG_OSDTRRX_EL1)
3123  .allPrivileges()
3124  .mapsTo(MISCREG_DBGDTRRXext);
3125  InitReg(MISCREG_MDSCR_EL1)
3126  .allPrivileges()
3127  .mapsTo(MISCREG_DBGDSCRext);
3128  InitReg(MISCREG_OSDTRTX_EL1)
3129  .allPrivileges()
3130  .mapsTo(MISCREG_DBGDTRTXext);
3131  InitReg(MISCREG_OSECCR_EL1)
3132  .allPrivileges()
3133  .mapsTo(MISCREG_DBGOSECCR);
3134  InitReg(MISCREG_DBGBVR0_EL1)
3135  .allPrivileges().exceptUserMode()
3136  .fault(EL1, faultDebugEL1)
3137  .fault(EL2, faultDebugEL2)
3138  .mapsTo(MISCREG_DBGBVR0, MISCREG_DBGBXVR0);
3139  InitReg(MISCREG_DBGBVR1_EL1)
3140  .allPrivileges().exceptUserMode()
3141  .fault(EL1, faultDebugEL1)
3142  .fault(EL2, faultDebugEL2)
3143  .mapsTo(MISCREG_DBGBVR1, MISCREG_DBGBXVR1);
3144  InitReg(MISCREG_DBGBVR2_EL1)
3145  .allPrivileges().exceptUserMode()
3146  .fault(EL1, faultDebugEL1)
3147  .fault(EL2, faultDebugEL2)
3148  .mapsTo(MISCREG_DBGBVR2, MISCREG_DBGBXVR2);
3149  InitReg(MISCREG_DBGBVR3_EL1)
3150  .allPrivileges().exceptUserMode()
3151  .fault(EL1, faultDebugEL1)
3152  .fault(EL2, faultDebugEL2)
3153  .mapsTo(MISCREG_DBGBVR3, MISCREG_DBGBXVR3);
3154  InitReg(MISCREG_DBGBVR4_EL1)
3155  .allPrivileges().exceptUserMode()
3156  .fault(EL1, faultDebugEL1)
3157  .fault(EL2, faultDebugEL2)
3158  .mapsTo(MISCREG_DBGBVR4, MISCREG_DBGBXVR4);
3159  InitReg(MISCREG_DBGBVR5_EL1)
3160  .allPrivileges().exceptUserMode()
3161  .fault(EL1, faultDebugEL1)
3162  .fault(EL2, faultDebugEL2)
3163  .mapsTo(MISCREG_DBGBVR5, MISCREG_DBGBXVR5);
3164  InitReg(MISCREG_DBGBVR6_EL1)
3165  .allPrivileges().exceptUserMode()
3166  .fault(EL1, faultDebugEL1)
3167  .fault(EL2, faultDebugEL2)
3168  .mapsTo(MISCREG_DBGBVR6, MISCREG_DBGBXVR6);
3169  InitReg(MISCREG_DBGBVR7_EL1)
3170  .allPrivileges().exceptUserMode()
3171  .fault(EL1, faultDebugEL1)
3172  .fault(EL2, faultDebugEL2)
3173  .mapsTo(MISCREG_DBGBVR7, MISCREG_DBGBXVR7);
3174  InitReg(MISCREG_DBGBVR8_EL1)
3175  .allPrivileges().exceptUserMode()
3176  .fault(EL1, faultDebugEL1)
3177  .fault(EL2, faultDebugEL2)
3178  .mapsTo(MISCREG_DBGBVR8, MISCREG_DBGBXVR8);
3179  InitReg(MISCREG_DBGBVR9_EL1)
3180  .allPrivileges().exceptUserMode()
3181  .fault(EL1, faultDebugEL1)
3182  .fault(EL2, faultDebugEL2)
3183  .mapsTo(MISCREG_DBGBVR9, MISCREG_DBGBXVR9);
3184  InitReg(MISCREG_DBGBVR10_EL1)
3185  .allPrivileges().exceptUserMode()
3186  .fault(EL1, faultDebugEL1)
3187  .fault(EL2, faultDebugEL2)
3188  .mapsTo(MISCREG_DBGBVR10, MISCREG_DBGBXVR10);
3189  InitReg(MISCREG_DBGBVR11_EL1)
3190  .allPrivileges().exceptUserMode()
3191  .fault(EL1, faultDebugEL1)
3192  .fault(EL2, faultDebugEL2)
3193  .mapsTo(MISCREG_DBGBVR11, MISCREG_DBGBXVR11);
3194  InitReg(MISCREG_DBGBVR12_EL1)
3195  .allPrivileges().exceptUserMode()
3196  .fault(EL1, faultDebugEL1)
3197  .fault(EL2, faultDebugEL2)
3198  .mapsTo(MISCREG_DBGBVR12, MISCREG_DBGBXVR12);
3199  InitReg(MISCREG_DBGBVR13_EL1)
3200  .allPrivileges().exceptUserMode()
3201  .fault(EL1, faultDebugEL1)
3202  .fault(EL2, faultDebugEL2)
3203  .mapsTo(MISCREG_DBGBVR13, MISCREG_DBGBXVR13);
3204  InitReg(MISCREG_DBGBVR14_EL1)
3205  .allPrivileges().exceptUserMode()
3206  .fault(EL1, faultDebugEL1)
3207  .fault(EL2, faultDebugEL2)
3208  .mapsTo(MISCREG_DBGBVR14, MISCREG_DBGBXVR14);
3209  InitReg(MISCREG_DBGBVR15_EL1)
3210  .allPrivileges().exceptUserMode()
3211  .fault(EL1, faultDebugEL1)
3212  .fault(EL2, faultDebugEL2)
3213  .mapsTo(MISCREG_DBGBVR15, MISCREG_DBGBXVR15);
3214  InitReg(MISCREG_DBGBCR0_EL1)
3215  .allPrivileges().exceptUserMode()
3216  .fault(EL1, faultDebugEL1)
3217  .fault(EL2, faultDebugEL2)
3218  .mapsTo(MISCREG_DBGBCR0);
3219  InitReg(MISCREG_DBGBCR1_EL1)
3220  .allPrivileges().exceptUserMode()
3221  .fault(EL1, faultDebugEL1)
3222  .fault(EL2, faultDebugEL2)
3223  .mapsTo(MISCREG_DBGBCR1);
3224  InitReg(MISCREG_DBGBCR2_EL1)
3225  .allPrivileges().exceptUserMode()
3226  .fault(EL1, faultDebugEL1)
3227  .fault(EL2, faultDebugEL2)
3228  .mapsTo(MISCREG_DBGBCR2);
3229  InitReg(MISCREG_DBGBCR3_EL1)
3230  .allPrivileges().exceptUserMode()
3231  .fault(EL1, faultDebugEL1)
3232  .fault(EL2, faultDebugEL2)
3233  .mapsTo(MISCREG_DBGBCR3);
3234  InitReg(MISCREG_DBGBCR4_EL1)
3235  .allPrivileges().exceptUserMode()
3236  .fault(EL1, faultDebugEL1)
3237  .fault(EL2, faultDebugEL2)
3238  .mapsTo(MISCREG_DBGBCR4);
3239  InitReg(MISCREG_DBGBCR5_EL1)
3240  .allPrivileges().exceptUserMode()
3241  .fault(EL1, faultDebugEL1)
3242  .fault(EL2, faultDebugEL2)
3243  .mapsTo(MISCREG_DBGBCR5);
3244  InitReg(MISCREG_DBGBCR6_EL1)
3245  .allPrivileges().exceptUserMode()
3246  .fault(EL1, faultDebugEL1)
3247  .fault(EL2, faultDebugEL2)
3248  .mapsTo(MISCREG_DBGBCR6);
3249  InitReg(MISCREG_DBGBCR7_EL1)
3250  .allPrivileges().exceptUserMode()
3251  .fault(EL1, faultDebugEL1)
3252  .fault(EL2, faultDebugEL2)
3253  .mapsTo(MISCREG_DBGBCR7);
3254  InitReg(MISCREG_DBGBCR8_EL1)
3255  .allPrivileges().exceptUserMode()
3256  .fault(EL1, faultDebugEL1)
3257  .fault(EL2, faultDebugEL2)
3258  .mapsTo(MISCREG_DBGBCR8);
3259  InitReg(MISCREG_DBGBCR9_EL1)
3260  .allPrivileges().exceptUserMode()
3261  .fault(EL1, faultDebugEL1)
3262  .fault(EL2, faultDebugEL2)
3263  .mapsTo(MISCREG_DBGBCR9);
3264  InitReg(MISCREG_DBGBCR10_EL1)
3265  .allPrivileges().exceptUserMode()
3266  .fault(EL1, faultDebugEL1)
3267  .fault(EL2, faultDebugEL2)
3268  .mapsTo(MISCREG_DBGBCR10);
3269  InitReg(MISCREG_DBGBCR11_EL1)
3270  .allPrivileges().exceptUserMode()
3271  .fault(EL1, faultDebugEL1)
3272  .fault(EL2, faultDebugEL2)
3273  .mapsTo(MISCREG_DBGBCR11);
3274  InitReg(MISCREG_DBGBCR12_EL1)
3275  .allPrivileges().exceptUserMode()
3276  .fault(EL1, faultDebugEL1)
3277  .fault(EL2, faultDebugEL2)
3278  .mapsTo(MISCREG_DBGBCR12);
3279  InitReg(MISCREG_DBGBCR13_EL1)
3280  .allPrivileges().exceptUserMode()
3281  .fault(EL1, faultDebugEL1)
3282  .fault(EL2, faultDebugEL2)
3283  .mapsTo(MISCREG_DBGBCR13);
3284  InitReg(MISCREG_DBGBCR14_EL1)
3285  .allPrivileges().exceptUserMode()
3286  .fault(EL1, faultDebugEL1)
3287  .fault(EL2, faultDebugEL2)
3288  .mapsTo(MISCREG_DBGBCR14);
3289  InitReg(MISCREG_DBGBCR15_EL1)
3290  .allPrivileges().exceptUserMode()
3291  .fault(EL1, faultDebugEL1)
3292  .fault(EL2, faultDebugEL2)
3293  .mapsTo(MISCREG_DBGBCR15);
3294  InitReg(MISCREG_DBGWVR0_EL1)
3295  .allPrivileges().exceptUserMode()
3296  .fault(EL1, faultDebugEL1)
3297  .fault(EL2, faultDebugEL2)
3298  .mapsTo(MISCREG_DBGWVR0);
3299  InitReg(MISCREG_DBGWVR1_EL1)
3300  .allPrivileges().exceptUserMode()
3301  .fault(EL1, faultDebugEL1)
3302  .fault(EL2, faultDebugEL2)
3303  .mapsTo(MISCREG_DBGWVR1);
3304  InitReg(MISCREG_DBGWVR2_EL1)
3305  .allPrivileges().exceptUserMode()
3306  .fault(EL1, faultDebugEL1)
3307  .fault(EL2, faultDebugEL2)
3308  .mapsTo(MISCREG_DBGWVR2);
3309  InitReg(MISCREG_DBGWVR3_EL1)
3310  .allPrivileges().exceptUserMode()
3311  .fault(EL1, faultDebugEL1)
3312  .fault(EL2, faultDebugEL2)
3313  .mapsTo(MISCREG_DBGWVR3);
3314  InitReg(MISCREG_DBGWVR4_EL1)
3315  .allPrivileges().exceptUserMode()
3316  .fault(EL1, faultDebugEL1)
3317  .fault(EL2, faultDebugEL2)
3318  .mapsTo(MISCREG_DBGWVR4);
3319  InitReg(MISCREG_DBGWVR5_EL1)
3320  .allPrivileges().exceptUserMode()
3321  .fault(EL1, faultDebugEL1)
3322  .fault(EL2, faultDebugEL2)
3323  .mapsTo(MISCREG_DBGWVR5);
3324  InitReg(MISCREG_DBGWVR6_EL1)
3325  .allPrivileges().exceptUserMode()
3326  .fault(EL1, faultDebugEL1)
3327  .fault(EL2, faultDebugEL2)
3328  .mapsTo(MISCREG_DBGWVR6);
3329  InitReg(MISCREG_DBGWVR7_EL1)
3330  .allPrivileges().exceptUserMode()
3331  .fault(EL1, faultDebugEL1)
3332  .fault(EL2, faultDebugEL2)
3333  .mapsTo(MISCREG_DBGWVR7);
3334  InitReg(MISCREG_DBGWVR8_EL1)
3335  .allPrivileges().exceptUserMode()
3336  .fault(EL1, faultDebugEL1)
3337  .fault(EL2, faultDebugEL2)
3338  .mapsTo(MISCREG_DBGWVR8);
3339  InitReg(MISCREG_DBGWVR9_EL1)
3340  .allPrivileges().exceptUserMode()
3341  .fault(EL1, faultDebugEL1)
3342  .fault(EL2, faultDebugEL2)
3343  .mapsTo(MISCREG_DBGWVR9);
3344  InitReg(MISCREG_DBGWVR10_EL1)
3345  .allPrivileges().exceptUserMode()
3346  .fault(EL1, faultDebugEL1)
3347  .fault(EL2, faultDebugEL2)
3348  .mapsTo(MISCREG_DBGWVR10);
3349  InitReg(MISCREG_DBGWVR11_EL1)
3350  .allPrivileges().exceptUserMode()
3351  .fault(EL1, faultDebugEL1)
3352  .fault(EL2, faultDebugEL2)
3353  .mapsTo(MISCREG_DBGWVR11);
3354  InitReg(MISCREG_DBGWVR12_EL1)
3355  .allPrivileges().exceptUserMode()
3356  .fault(EL1, faultDebugEL1)
3357  .fault(EL2, faultDebugEL2)
3358  .mapsTo(MISCREG_DBGWVR12);
3359  InitReg(MISCREG_DBGWVR13_EL1)
3360  .allPrivileges().exceptUserMode()
3361  .fault(EL1, faultDebugEL1)
3362  .fault(EL2, faultDebugEL2)
3363  .mapsTo(MISCREG_DBGWVR13);
3364  InitReg(MISCREG_DBGWVR14_EL1)
3365  .allPrivileges().exceptUserMode()
3366  .fault(EL1, faultDebugEL1)
3367  .fault(EL2, faultDebugEL2)
3368  .mapsTo(MISCREG_DBGWVR14);
3369  InitReg(MISCREG_DBGWVR15_EL1)
3370  .allPrivileges().exceptUserMode()
3371  .fault(EL1, faultDebugEL1)
3372  .fault(EL2, faultDebugEL2)
3373  .mapsTo(MISCREG_DBGWVR15);
3374  InitReg(MISCREG_DBGWCR0_EL1)
3375  .allPrivileges().exceptUserMode()
3376  .fault(EL1, faultDebugEL1)
3377  .fault(EL2, faultDebugEL2)
3378  .mapsTo(MISCREG_DBGWCR0);
3379  InitReg(MISCREG_DBGWCR1_EL1)
3380  .allPrivileges().exceptUserMode()
3381  .fault(EL1, faultDebugEL1)
3382  .fault(EL2, faultDebugEL2)
3383  .mapsTo(MISCREG_DBGWCR1);
3384  InitReg(MISCREG_DBGWCR2_EL1)
3385  .allPrivileges().exceptUserMode()
3386  .fault(EL1, faultDebugEL1)
3387  .fault(EL2, faultDebugEL2)
3388  .mapsTo(MISCREG_DBGWCR2);
3389  InitReg(MISCREG_DBGWCR3_EL1)
3390  .allPrivileges().exceptUserMode()
3391  .fault(EL1, faultDebugEL1)
3392  .fault(EL2, faultDebugEL2)
3393  .mapsTo(MISCREG_DBGWCR3);
3394  InitReg(MISCREG_DBGWCR4_EL1)
3395  .allPrivileges().exceptUserMode()
3396  .fault(EL1, faultDebugEL1)
3397  .fault(EL2, faultDebugEL2)
3398  .mapsTo(MISCREG_DBGWCR4);
3399  InitReg(MISCREG_DBGWCR5_EL1)
3400  .allPrivileges().exceptUserMode()
3401  .fault(EL1, faultDebugEL1)
3402  .fault(EL2, faultDebugEL2)
3403  .mapsTo(MISCREG_DBGWCR5);
3404  InitReg(MISCREG_DBGWCR6_EL1)
3405  .allPrivileges().exceptUserMode()
3406  .fault(EL1, faultDebugEL1)
3407  .fault(EL2, faultDebugEL2)
3408  .mapsTo(MISCREG_DBGWCR6);
3409  InitReg(MISCREG_DBGWCR7_EL1)
3410  .allPrivileges().exceptUserMode()
3411  .fault(EL1, faultDebugEL1)
3412  .fault(EL2, faultDebugEL2)
3413  .mapsTo(MISCREG_DBGWCR7);
3414  InitReg(MISCREG_DBGWCR8_EL1)
3415  .allPrivileges().exceptUserMode()
3416  .fault(EL1, faultDebugEL1)
3417  .fault(EL2, faultDebugEL2)
3418  .mapsTo(MISCREG_DBGWCR8);
3419  InitReg(MISCREG_DBGWCR9_EL1)
3420  .allPrivileges().exceptUserMode()
3421  .fault(EL1, faultDebugEL1)
3422  .fault(EL2, faultDebugEL2)
3423  .mapsTo(MISCREG_DBGWCR9);
3424  InitReg(MISCREG_DBGWCR10_EL1)
3425  .allPrivileges().exceptUserMode()
3426  .fault(EL1, faultDebugEL1)
3427  .fault(EL2, faultDebugEL2)
3428  .mapsTo(MISCREG_DBGWCR10);
3429  InitReg(MISCREG_DBGWCR11_EL1)
3430  .allPrivileges().exceptUserMode()
3431  .fault(EL1, faultDebugEL1)
3432  .fault(EL2, faultDebugEL2)
3433  .mapsTo(MISCREG_DBGWCR11);
3434  InitReg(MISCREG_DBGWCR12_EL1)
3435  .allPrivileges().exceptUserMode()
3436  .fault(EL1, faultDebugEL1)
3437  .fault(EL2, faultDebugEL2)
3438  .mapsTo(MISCREG_DBGWCR12);
3439  InitReg(MISCREG_DBGWCR13_EL1)
3440  .allPrivileges().exceptUserMode()
3441  .fault(EL1, faultDebugEL1)
3442  .fault(EL2, faultDebugEL2)
3443  .mapsTo(MISCREG_DBGWCR13);
3444  InitReg(MISCREG_DBGWCR14_EL1)
3445  .allPrivileges().exceptUserMode()
3446  .fault(EL1, faultDebugEL1)
3447  .fault(EL2, faultDebugEL2)
3448  .mapsTo(MISCREG_DBGWCR14);
3449  InitReg(MISCREG_DBGWCR15_EL1)
3450  .allPrivileges().exceptUserMode()
3451  .fault(EL1, faultDebugEL1)
3452  .fault(EL2, faultDebugEL2)
3453  .mapsTo(MISCREG_DBGWCR15);
3454  InitReg(MISCREG_MDCCSR_EL0)
3455  .allPrivileges().writes(0)
3456  .faultRead(EL0, faultMdccsrEL0)
3457  .faultRead(EL1, faultMdccsrEL1)
3458  .faultRead(EL2, faultMdccsrEL2)
3459  .mapsTo(MISCREG_DBGDSCRint);
3460  InitReg(MISCREG_MDDTR_EL0)
3461  .allPrivileges();
3462  InitReg(MISCREG_MDDTRTX_EL0)
3463  .allPrivileges();
3464  InitReg(MISCREG_MDDTRRX_EL0)
3465  .allPrivileges();
3466  InitReg(MISCREG_DBGVCR32_EL2)
3467  .hyp().mon()
3468  .fault(EL2, faultDebugEL2)
3469  .mapsTo(MISCREG_DBGVCR);
3470  InitReg(MISCREG_MDRAR_EL1)
3471  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3472  .mapsTo(MISCREG_DBGDRAR);
3473  InitReg(MISCREG_OSLAR_EL1)
3474  .allPrivileges().monSecureRead(0).monNonSecureRead(0)
3475  .mapsTo(MISCREG_DBGOSLAR);
3476  InitReg(MISCREG_OSLSR_EL1)
3477  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3478  .mapsTo(MISCREG_DBGOSLSR);
3479  InitReg(MISCREG_OSDLR_EL1)
3480  .allPrivileges()
3481  .mapsTo(MISCREG_DBGOSDLR);
3482  InitReg(MISCREG_DBGPRCR_EL1)
3483  .allPrivileges()
3484  .mapsTo(MISCREG_DBGPRCR);
3485  InitReg(MISCREG_DBGCLAIMSET_EL1)
3486  .allPrivileges()
3487  .mapsTo(MISCREG_DBGCLAIMSET);
3488  InitReg(MISCREG_DBGCLAIMCLR_EL1)
3489  .allPrivileges()
3490  .mapsTo(MISCREG_DBGCLAIMCLR);
3491  InitReg(MISCREG_DBGAUTHSTATUS_EL1)
3492  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3493  .mapsTo(MISCREG_DBGAUTHSTATUS);
3494  InitReg(MISCREG_TEECR32_EL1);
3495  InitReg(MISCREG_TEEHBR32_EL1);
3496 
3497  // AArch64 registers (Op0=1,3);
3498  InitReg(MISCREG_MIDR_EL1)
3499  .allPrivileges().exceptUserMode().writes(0);
3500  InitReg(MISCREG_MPIDR_EL1)
3501  .allPrivileges().exceptUserMode().writes(0);
3502  InitReg(MISCREG_REVIDR_EL1)
3503  .faultRead(EL1, HCR_TRAP(tid1))
3504  .allPrivileges().exceptUserMode().writes(0);
3505  InitReg(MISCREG_ID_PFR0_EL1)
3506  .allPrivileges().exceptUserMode().writes(0)
3507  .faultRead(EL1, HCR_TRAP(tid3))
3508  .mapsTo(MISCREG_ID_PFR0);
3509  InitReg(MISCREG_ID_PFR1_EL1)
3510  .allPrivileges().exceptUserMode().writes(0)
3511  .faultRead(EL1, HCR_TRAP(tid3))
3512  .mapsTo(MISCREG_ID_PFR1);
3513  InitReg(MISCREG_ID_DFR0_EL1)
3514  .allPrivileges().exceptUserMode().writes(0)
3515  .faultRead(EL1, HCR_TRAP(tid3))
3516  .mapsTo(MISCREG_ID_DFR0);
3517  InitReg(MISCREG_ID_AFR0_EL1)
3518  .allPrivileges().exceptUserMode().writes(0)
3519  .faultRead(EL1, HCR_TRAP(tid3))
3520  .mapsTo(MISCREG_ID_AFR0);
3521  InitReg(MISCREG_ID_MMFR0_EL1)
3522  .allPrivileges().exceptUserMode().writes(0)
3523  .faultRead(EL1, HCR_TRAP(tid3))
3524  .mapsTo(MISCREG_ID_MMFR0);
3525  InitReg(MISCREG_ID_MMFR1_EL1)
3526  .allPrivileges().exceptUserMode().writes(0)
3527  .faultRead(EL1, HCR_TRAP(tid3))
3528  .mapsTo(MISCREG_ID_MMFR1);
3529  InitReg(MISCREG_ID_MMFR2_EL1)
3530  .allPrivileges().exceptUserMode().writes(0)
3531  .faultRead(EL1, HCR_TRAP(tid3))
3532  .mapsTo(MISCREG_ID_MMFR2);
3533  InitReg(MISCREG_ID_MMFR3_EL1)
3534  .allPrivileges().exceptUserMode().writes(0)
3535  .faultRead(EL1, HCR_TRAP(tid3))
3536  .mapsTo(MISCREG_ID_MMFR3);
3537  InitReg(MISCREG_ID_MMFR4_EL1)
3538  .allPrivileges().exceptUserMode().writes(0)
3539  .faultRead(EL1, HCR_TRAP(tid3))
3540  .mapsTo(MISCREG_ID_MMFR4);
3541  InitReg(MISCREG_ID_ISAR0_EL1)
3542  .allPrivileges().exceptUserMode().writes(0)
3543  .faultRead(EL1, HCR_TRAP(tid3))
3544  .mapsTo(MISCREG_ID_ISAR0);
3545  InitReg(MISCREG_ID_ISAR1_EL1)
3546  .allPrivileges().exceptUserMode().writes(0)
3547  .faultRead(EL1, HCR_TRAP(tid3))
3548  .mapsTo(MISCREG_ID_ISAR1);
3549  InitReg(MISCREG_ID_ISAR2_EL1)
3550  .allPrivileges().exceptUserMode().writes(0)
3551  .faultRead(EL1, HCR_TRAP(tid3))
3552  .mapsTo(MISCREG_ID_ISAR2);
3553  InitReg(MISCREG_ID_ISAR3_EL1)
3554  .allPrivileges().exceptUserMode().writes(0)
3555  .faultRead(EL1, HCR_TRAP(tid3))
3556  .mapsTo(MISCREG_ID_ISAR3);
3557  InitReg(MISCREG_ID_ISAR4_EL1)
3558  .allPrivileges().exceptUserMode().writes(0)
3559  .faultRead(EL1, HCR_TRAP(tid3))
3560  .mapsTo(MISCREG_ID_ISAR4);
3561  InitReg(MISCREG_ID_ISAR5_EL1)
3562  .allPrivileges().exceptUserMode().writes(0)
3563  .faultRead(EL1, HCR_TRAP(tid3))
3564  .mapsTo(MISCREG_ID_ISAR5);
3565  InitReg(MISCREG_ID_ISAR6_EL1)
3566  .allPrivileges().exceptUserMode().writes(0)
3567  .faultRead(EL1, HCR_TRAP(tid3))
3568  .mapsTo(MISCREG_ID_ISAR6);
3569  InitReg(MISCREG_MVFR0_EL1)
3570  .faultRead(EL1, HCR_TRAP(tid3))
3571  .allPrivileges().exceptUserMode().writes(0);
3572  InitReg(MISCREG_MVFR1_EL1)
3573  .faultRead(EL1, HCR_TRAP(tid3))
3574  .allPrivileges().exceptUserMode().writes(0);
3575  InitReg(MISCREG_MVFR2_EL1)
3576  .faultRead(EL1, HCR_TRAP(tid3))
3577  .allPrivileges().exceptUserMode().writes(0);
3578  InitReg(MISCREG_ID_AA64PFR0_EL1)
3579  .faultRead(EL1, HCR_TRAP(tid3))
3580  .allPrivileges().exceptUserMode().writes(0);
3581  InitReg(MISCREG_ID_AA64PFR1_EL1)
3582  .faultRead(EL1, HCR_TRAP(tid3))
3583  .allPrivileges().exceptUserMode().writes(0);
3584  InitReg(MISCREG_ID_AA64DFR0_EL1)
3585  .faultRead(EL1, HCR_TRAP(tid3))
3586  .allPrivileges().exceptUserMode().writes(0);
3587  InitReg(MISCREG_ID_AA64DFR1_EL1)
3588  .faultRead(EL1, HCR_TRAP(tid3))
3589  .allPrivileges().exceptUserMode().writes(0);
3590  InitReg(MISCREG_ID_AA64AFR0_EL1)
3591  .faultRead(EL1, HCR_TRAP(tid3))
3592  .allPrivileges().exceptUserMode().writes(0);
3593  InitReg(MISCREG_ID_AA64AFR1_EL1)
3594  .faultRead(EL1, HCR_TRAP(tid3))
3595  .allPrivileges().exceptUserMode().writes(0);
3596  InitReg(MISCREG_ID_AA64ISAR0_EL1)
3597  .faultRead(EL1, HCR_TRAP(tid3))
3598  .allPrivileges().exceptUserMode().writes(0);
3599  InitReg(MISCREG_ID_AA64ISAR1_EL1)
3600  .faultRead(EL1, HCR_TRAP(tid3))
3601  .allPrivileges().exceptUserMode().writes(0);
3602  InitReg(MISCREG_ID_AA64MMFR0_EL1)
3603  .faultRead(EL1, HCR_TRAP(tid3))
3604  .allPrivileges().exceptUserMode().writes(0);
3605  InitReg(MISCREG_ID_AA64MMFR1_EL1)
3606  .faultRead(EL1, HCR_TRAP(tid3))
3607  .allPrivileges().exceptUserMode().writes(0);
3608  InitReg(MISCREG_ID_AA64MMFR2_EL1)
3609  .faultRead(EL1, HCR_TRAP(tid3))
3610  .allPrivileges().exceptUserMode().writes(0);
3611 
3612  InitReg(MISCREG_APDAKeyHi_EL1)
3613  .fault(EL1, faultPauthEL1)
3614  .fault(EL2, faultPauthEL2)
3615  .allPrivileges().exceptUserMode();
3616  InitReg(MISCREG_APDAKeyLo_EL1)
3617  .fault(EL1, faultPauthEL1)
3618  .fault(EL2, faultPauthEL2)
3619  .allPrivileges().exceptUserMode();
3620  InitReg(MISCREG_APDBKeyHi_EL1)
3621  .fault(EL1, faultPauthEL1)
3622  .fault(EL2, faultPauthEL2)
3623  .allPrivileges().exceptUserMode();
3624  InitReg(MISCREG_APDBKeyLo_EL1)
3625  .fault(EL1, faultPauthEL1)
3626  .fault(EL2, faultPauthEL2)
3627  .allPrivileges().exceptUserMode();
3628  InitReg(MISCREG_APGAKeyHi_EL1)
3629  .fault(EL1, faultPauthEL1)
3630  .fault(EL2, faultPauthEL2)
3631  .allPrivileges().exceptUserMode();
3632  InitReg(MISCREG_APGAKeyLo_EL1)
3633  .fault(EL1, faultPauthEL1)
3634  .fault(EL2, faultPauthEL2)
3635  .allPrivileges().exceptUserMode();
3636  InitReg(MISCREG_APIAKeyHi_EL1)
3637  .fault(EL1, faultPauthEL1)
3638  .fault(EL2, faultPauthEL2)
3639  .allPrivileges().exceptUserMode();
3640  InitReg(MISCREG_APIAKeyLo_EL1)
3641  .fault(EL1, faultPauthEL1)
3642  .fault(EL2, faultPauthEL2)
3643  .allPrivileges().exceptUserMode();
3644  InitReg(MISCREG_APIBKeyHi_EL1)
3645  .fault(EL1, faultPauthEL1)
3646  .fault(EL2, faultPauthEL2)
3647  .allPrivileges().exceptUserMode();
3648  InitReg(MISCREG_APIBKeyLo_EL1)
3649  .fault(EL1, faultPauthEL1)
3650  .fault(EL2, faultPauthEL2)
3651  .allPrivileges().exceptUserMode();
3652 
3653  InitReg(MISCREG_CCSIDR_EL1)
3654  .faultRead(EL1, HCR_TRAP(tid2))
3655  .allPrivileges().exceptUserMode().writes(0);
3656  InitReg(MISCREG_CLIDR_EL1)
3657  .faultRead(EL1, HCR_TRAP(tid2))
3658  .allPrivileges().exceptUserMode().writes(0);
3659  InitReg(MISCREG_AIDR_EL1)
3660  .faultRead(EL1, HCR_TRAP(tid1))
3661  .allPrivileges().exceptUserMode().writes(0);
3662  InitReg(MISCREG_CSSELR_EL1)
3663  .allPrivileges().exceptUserMode()
3664  .fault(EL1, HCR_TRAP(tid2))
3665  .mapsTo(MISCREG_CSSELR_NS);
3666  InitReg(MISCREG_CTR_EL0)
3667  .faultRead(EL0, faultCtrEL0)
3668  .faultRead(EL1, HCR_TRAP(tid2))
3669  .reads(1);
3670  InitReg(MISCREG_DCZID_EL0)
3671  .reads(1);
3672  InitReg(MISCREG_VPIDR_EL2)
3673  .hyp().mon()
3674  .mapsTo(MISCREG_VPIDR);
3675  InitReg(MISCREG_VMPIDR_EL2)
3676  .hyp().mon()
3677  .mapsTo(MISCREG_VMPIDR);
3678  InitReg(MISCREG_SCTLR_EL1)
3679  .allPrivileges().exceptUserMode()
3680  .faultRead(EL1, HCR_TRAP(trvm))
3681  .faultWrite(EL1, HCR_TRAP(tvm))
3682  .res0( 0x20440 | (EnDB ? 0 : 0x2000)
3683  | (IESB ? 0 : 0x200000)
3684  | (EnDA ? 0 : 0x8000000)
3685  | (EnIB ? 0 : 0x40000000)
3686  | (EnIA ? 0 : 0x80000000))
3687  .res1(0x500800 | (SPAN ? 0 : 0x800000)
3688  | (nTLSMD ? 0 : 0x8000000)
3689  | (LSMAOE ? 0 : 0x10000000))
3690  .mapsTo(MISCREG_SCTLR_NS);
3691  InitReg(MISCREG_SCTLR_EL12)
3692  .fault(EL2, defaultFaultE2H_EL2)
3693  .fault(EL3, defaultFaultE2H_EL3)
3694  .res0( 0x20440 | (EnDB ? 0 : 0x2000)
3695  | (IESB ? 0 : 0x200000)
3696  | (EnDA ? 0 : 0x8000000)
3697  | (EnIB ? 0 : 0x40000000)
3698  | (EnIA ? 0 : 0x80000000))
3699  .res1(0x500800 | (SPAN ? 0 : 0x800000)
3700  | (nTLSMD ? 0 : 0x8000000)
3701  | (LSMAOE ? 0 : 0x10000000))
3702  .mapsTo(MISCREG_SCTLR_EL1);
3703  InitReg(MISCREG_ACTLR_EL1)
3704  .allPrivileges().exceptUserMode()
3705  .fault(EL1, HCR_TRAP(tacr))
3706  .mapsTo(MISCREG_ACTLR_NS);
3707  InitReg(MISCREG_CPACR_EL1)
3708  .allPrivileges().exceptUserMode()
3709  .fault(EL1, faultCpacrEL1)
3710  .fault(EL2, faultCpacrEL2)
3711  .mapsTo(MISCREG_CPACR);
3712  InitReg(MISCREG_CPACR_EL12)
3713  .fault(EL2, faultCpacrVheEL2)
3714  .fault(EL3, defaultFaultE2H_EL3)
3715  .mapsTo(MISCREG_CPACR_EL1);
3716  InitReg(MISCREG_SCTLR_EL2)
3717  .hyp().mon()
3718  .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
3719  | (IESB ? 0 : 0x200000)
3720  | (EnDA ? 0 : 0x8000000)
3721  | (EnIB ? 0 : 0x40000000)
3722  | (EnIA ? 0 : 0x80000000))
3723  .res1(0x30c50830)
3724  .mapsTo(MISCREG_HSCTLR);
3725  InitReg(MISCREG_ACTLR_EL2)
3726  .hyp().mon()
3727  .mapsTo(MISCREG_HACTLR);
3728  InitReg(MISCREG_HCR_EL2)
3729  .hyp().mon()
3730  .mapsTo(MISCREG_HCR, MISCREG_HCR2);
3731  InitReg(MISCREG_MDCR_EL2)
3732  .hyp().mon()
3733  .fault(EL2, faultDebugEL2)
3734  .mapsTo(MISCREG_HDCR);
3735  InitReg(MISCREG_CPTR_EL2)
3736  .hyp().mon()
3737  .fault(EL2, faultCpacrEL2)
3738  .mapsTo(MISCREG_HCPTR);
3739  InitReg(MISCREG_HSTR_EL2)
3740  .hyp().mon()
3741  .mapsTo(MISCREG_HSTR);
3742  InitReg(MISCREG_HACR_EL2)
3743  .hyp().mon()
3744  .mapsTo(MISCREG_HACR);
3745  InitReg(MISCREG_SCTLR_EL3)
3746  .mon()
3747  .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
3748  | (IESB ? 0 : 0x200000)
3749  | (EnDA ? 0 : 0x8000000)
3750  | (EnIB ? 0 : 0x40000000)
3751  | (EnIA ? 0 : 0x80000000))
3752  .res1(0x30c50830);
3753  InitReg(MISCREG_ACTLR_EL3)
3754  .mon();
3755  InitReg(MISCREG_SCR_EL3)
3756  .mon()
3757  .mapsTo(MISCREG_SCR); // NAM D7-2005
3758  InitReg(MISCREG_SDER32_EL3)
3759  .mon()
3760  .mapsTo(MISCREG_SDER);
3761  InitReg(MISCREG_CPTR_EL3)
3762  .mon();
3763  InitReg(MISCREG_MDCR_EL3)
3764  .mon()
3765  .mapsTo(MISCREG_SDCR);
3766  InitReg(MISCREG_TTBR0_EL1)
3767  .allPrivileges().exceptUserMode()
3768  .faultRead(EL1, HCR_TRAP(trvm))
3769  .faultWrite(EL1, HCR_TRAP(tvm))
3770  .mapsTo(MISCREG_TTBR0_NS);
3771  InitReg(MISCREG_TTBR0_EL12)
3772  .fault(EL2, defaultFaultE2H_EL2)
3773  .fault(EL3, defaultFaultE2H_EL3)
3774  .mapsTo(MISCREG_TTBR0_EL1);
3775  InitReg(MISCREG_TTBR1_EL1)
3776  .allPrivileges().exceptUserMode()
3777  .faultRead(EL1, HCR_TRAP(trvm))
3778  .faultWrite(EL1, HCR_TRAP(tvm))
3779  .mapsTo(MISCREG_TTBR1_NS);
3780  InitReg(MISCREG_TTBR1_EL12)
3781  .fault(EL2, defaultFaultE2H_EL2)
3782  .fault(EL3, defaultFaultE2H_EL3)
3783  .mapsTo(MISCREG_TTBR1_EL1);
3784  InitReg(MISCREG_TCR_EL1)
3785  .allPrivileges().exceptUserMode()
3786  .faultRead(EL1, HCR_TRAP(trvm))
3787  .faultWrite(EL1, HCR_TRAP(tvm))
3788  .mapsTo(MISCREG_TTBCR_NS);
3789  InitReg(MISCREG_TCR_EL12)
3790  .fault(EL2, defaultFaultE2H_EL2)
3791  .fault(EL3, defaultFaultE2H_EL3)
3792  .mapsTo(MISCREG_TTBCR_NS);
3793  InitReg(MISCREG_TTBR0_EL2)
3794  .hyp().mon()
3795  .mapsTo(MISCREG_HTTBR);
3796  InitReg(MISCREG_TTBR1_EL2)
3797  .hyp().mon();
3798  InitReg(MISCREG_TCR_EL2)
3799  .hyp().mon()
3800  .mapsTo(MISCREG_HTCR);
3801  InitReg(MISCREG_VTTBR_EL2)
3802  .hyp().mon()
3803  .mapsTo(MISCREG_VTTBR);
3804  InitReg(MISCREG_VTCR_EL2)
3805  .hyp().mon()
3806  .mapsTo(MISCREG_VTCR);
3807  InitReg(MISCREG_VSTTBR_EL2)
3808  .hypSecure().mon();
3809  InitReg(MISCREG_VSTCR_EL2)
3810  .hypSecure().mon();
3811  InitReg(MISCREG_TTBR0_EL3)
3812  .mon();
3813  InitReg(MISCREG_TCR_EL3)
3814  .mon();
3815  InitReg(MISCREG_DACR32_EL2)
3816  .hyp().mon()
3817  .mapsTo(MISCREG_DACR_NS);
3818  InitReg(MISCREG_SPSR_EL1)
3819  .allPrivileges().exceptUserMode()
3820  .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
3821  InitReg(MISCREG_SPSR_EL12)
3822  .fault(EL2, defaultFaultE2H_EL2)
3823  .fault(EL3, defaultFaultE2H_EL3)
3824  .mapsTo(MISCREG_SPSR_SVC);
3825  InitReg(MISCREG_ELR_EL1)
3826  .allPrivileges().exceptUserMode();
3827  InitReg(MISCREG_ELR_EL12)
3828  .fault(EL2, defaultFaultE2H_EL2)
3829  .fault(EL3, defaultFaultE2H_EL3)
3830  .mapsTo(MISCREG_ELR_EL1);
3831  InitReg(MISCREG_SP_EL0)
3832  .allPrivileges().exceptUserMode()
3833  .fault(EL1, faultSpEL0)
3834  .fault(EL2, faultSpEL0)
3835  .fault(EL3, faultSpEL0);
3836  InitReg(MISCREG_SPSEL)
3837  .allPrivileges().exceptUserMode();
3838  InitReg(MISCREG_CURRENTEL)
3839  .allPrivileges().exceptUserMode().writes(0);
3840  InitReg(MISCREG_PAN)
3841  .allPrivileges(release->has(ArmExtension::FEAT_PAN))
3842  .exceptUserMode();
3843  InitReg(MISCREG_UAO)
3844  .allPrivileges().exceptUserMode();
3845  InitReg(MISCREG_NZCV)
3846  .allPrivileges();
3847  InitReg(MISCREG_DAIF)
3848  .allPrivileges()
3849  .fault(EL0, faultDaif);
3850  InitReg(MISCREG_FPCR)
3851  .allPrivileges()
3852  .fault(EL0, faultFpcrEL0)
3853  .fault(EL1, faultFpcrEL1)
3854  .fault(EL2, faultFpcrEL2)
3855  .fault(EL3, faultFpcrEL3);
3856  InitReg(MISCREG_FPSR)
3857  .allPrivileges()
3858  .fault(EL0, faultFpcrEL0)
3859  .fault(EL1, faultFpcrEL1)
3860  .fault(EL2, faultFpcrEL2)
3861  .fault(EL3, faultFpcrEL3);
3862  InitReg(MISCREG_DSPSR_EL0)
3863  .allPrivileges();
3864  InitReg(MISCREG_DLR_EL0)
3865  .allPrivileges();
3866  InitReg(MISCREG_SPSR_EL2)
3867  .hyp().mon()
3868  .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2
3869  InitReg(MISCREG_ELR_EL2)
3870  .hyp().mon();
3871  InitReg(MISCREG_SP_EL1)
3872  .hyp().mon();
3873  InitReg(MISCREG_SPSR_IRQ_AA64)
3874  .hyp().mon();
3875  InitReg(MISCREG_SPSR_ABT_AA64)
3876  .hyp().mon();
3877  InitReg(MISCREG_SPSR_UND_AA64)
3878  .hyp().mon();
3879  InitReg(MISCREG_SPSR_FIQ_AA64)
3880  .hyp().mon();
3881  InitReg(MISCREG_SPSR_EL3)
3882  .mon()
3883  .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3
3884  InitReg(MISCREG_ELR_EL3)
3885  .mon();
3886  InitReg(MISCREG_SP_EL2)
3887  .mon();
3888  InitReg(MISCREG_AFSR0_EL1)
3889  .allPrivileges().exceptUserMode()
3890  .faultRead(EL1, HCR_TRAP(trvm))
3891  .faultWrite(EL1, HCR_TRAP(tvm))
3892  .mapsTo(MISCREG_ADFSR_NS);
3893  InitReg(MISCREG_AFSR0_EL12)
3894  .fault(EL2, defaultFaultE2H_EL2)
3895  .fault(EL3, defaultFaultE2H_EL3)
3896  .mapsTo(MISCREG_ADFSR_NS);
3897  InitReg(MISCREG_AFSR1_EL1)
3898  .allPrivileges().exceptUserMode()
3899  .faultRead(EL1, HCR_TRAP(trvm))
3900  .faultWrite(EL1, HCR_TRAP(tvm))
3901  .mapsTo(MISCREG_AIFSR_NS);
3902  InitReg(MISCREG_AFSR1_EL12)
3903  .fault(EL2, defaultFaultE2H_EL2)
3904  .fault(EL3, defaultFaultE2H_EL3)
3905  .mapsTo(MISCREG_AIFSR_NS);
3906  InitReg(MISCREG_ESR_EL1)
3907  .faultRead(EL1, HCR_TRAP(trvm))
3908  .faultWrite(EL1, HCR_TRAP(tvm))
3909  .allPrivileges().exceptUserMode();
3910  InitReg(MISCREG_ESR_EL12)
3911  .fault(EL2, defaultFaultE2H_EL2)
3912  .fault(EL3, defaultFaultE2H_EL3)
3913  .mapsTo(MISCREG_ESR_EL1);
3914  InitReg(MISCREG_IFSR32_EL2)
3915  .hyp().mon()
3916  .mapsTo(MISCREG_IFSR_NS);
3917  InitReg(MISCREG_AFSR0_EL2)
3918  .hyp().mon()
3919  .mapsTo(MISCREG_HADFSR);
3920  InitReg(MISCREG_AFSR1_EL2)
3921  .hyp().mon()
3922  .mapsTo(MISCREG_HAIFSR);
3923  InitReg(MISCREG_ESR_EL2)
3924  .hyp().mon()
3925  .mapsTo(MISCREG_HSR);
3926  InitReg(MISCREG_FPEXC32_EL2)
3927  .fault(EL2, faultFpcrEL2)
3928  .fault(EL3, faultFpcrEL3)
3929  .mapsTo(MISCREG_FPEXC);
3930  InitReg(MISCREG_AFSR0_EL3)
3931  .mon();
3932  InitReg(MISCREG_AFSR1_EL3)
3933  .mon();
3934  InitReg(MISCREG_ESR_EL3)
3935  .mon();
3936  InitReg(MISCREG_FAR_EL1)
3937  .allPrivileges().exceptUserMode()
3938  .faultRead(EL1, HCR_TRAP(trvm))
3939  .faultWrite(EL1, HCR_TRAP(tvm))
3940  .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
3941  InitReg(MISCREG_FAR_EL12)
3942  .fault(EL2, defaultFaultE2H_EL2)
3943  .fault(EL3, defaultFaultE2H_EL3)
3944  .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
3945  InitReg(MISCREG_FAR_EL2)
3946  .hyp().mon()
3947  .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR);
3948  InitReg(MISCREG_HPFAR_EL2)
3949  .hyp().mon()
3950  .mapsTo(MISCREG_HPFAR);
3951  InitReg(MISCREG_FAR_EL3)
3952  .mon();
3953  InitReg(MISCREG_IC_IALLUIS)
3954  .warnNotFail()
3955  .faultWrite(EL1, faultPouIsEL1)
3956  .writes(1).exceptUserMode();
3957  InitReg(MISCREG_PAR_EL1)
3958  .allPrivileges().exceptUserMode()
3959  .mapsTo(MISCREG_PAR_NS);
3960  InitReg(MISCREG_IC_IALLU)
3961  .warnNotFail()
3962  .faultWrite(EL1, faultPouEL1)
3963  .writes(1).exceptUserMode();
3964  InitReg(MISCREG_DC_IVAC_Xt)
3965  .faultWrite(EL1, HCR_TRAP(tpc))
3966  .writes(1).exceptUserMode();
3967  InitReg(MISCREG_DC_ISW_Xt)
3968  .warnNotFail()
3969  .faultWrite(EL1, HCR_TRAP(tsw))
3970  .writes(1).exceptUserMode();
3971  InitReg(MISCREG_AT_S1E1R_Xt)
3972  .faultWrite(EL1, HCR_TRAP(at))
3973  .writes(1).exceptUserMode();
3974  InitReg(MISCREG_AT_S1E1W_Xt)
3975  .faultWrite(EL1, HCR_TRAP(at))
3976  .writes(1).exceptUserMode();
3977  InitReg(MISCREG_AT_S1E0R_Xt)
3978  .faultWrite(EL1, HCR_TRAP(at))
3979  .writes(1).exceptUserMode();
3980  InitReg(MISCREG_AT_S1E0W_Xt)
3981  .faultWrite(EL1, HCR_TRAP(at))
3982  .writes(1).exceptUserMode();
3983  InitReg(MISCREG_DC_CSW_Xt)
3984  .warnNotFail()
3985  .faultWrite(EL1, HCR_TRAP(tsw))
3986  .writes(1).exceptUserMode();
3987  InitReg(MISCREG_DC_CISW_Xt)
3988  .warnNotFail()
3989  .faultWrite(EL1, HCR_TRAP(tsw))
3990  .writes(1).exceptUserMode();
3991  InitReg(MISCREG_DC_ZVA_Xt)
3992  .writes(1)
3993  .faultWrite(EL0, faultDczvaEL0)
3994  .faultWrite(EL1, HCR_TRAP(tdz));
3995  InitReg(MISCREG_IC_IVAU_Xt)
3996  .faultWrite(EL0, faultPouEL0)
3997  .faultWrite(EL1, faultPouEL1)
3998  .writes(1);
3999  InitReg(MISCREG_DC_CVAC_Xt)
4000  .faultWrite(EL0, faultCvacEL0)
4001  .faultWrite(EL1, HCR_TRAP(tpc))
4002  .writes(1);
4003  InitReg(MISCREG_DC_CVAU_Xt)
4004  .faultWrite(EL0, faultPouEL0)
4005  .faultWrite(EL1, faultPouEL1)
4006  .writes(1);
4007  InitReg(MISCREG_DC_CIVAC_Xt)
4008  .faultWrite(EL0, faultCvacEL0)
4009  .faultWrite(EL1, HCR_TRAP(tpc))
4010  .writes(1);
4011  InitReg(MISCREG_AT_S1E2R_Xt)
4012  .monNonSecureWrite().hypWrite();
4013  InitReg(MISCREG_AT_S1E2W_Xt)
4014  .monNonSecureWrite().hypWrite();
4015  InitReg(MISCREG_AT_S12E1R_Xt)
4016  .hypWrite().monSecureWrite().monNonSecureWrite();
4017  InitReg(MISCREG_AT_S12E1W_Xt)
4018  .hypWrite().monSecureWrite().monNonSecureWrite();
4019  InitReg(MISCREG_AT_S12E0R_Xt)
4020  .hypWrite().monSecureWrite().monNonSecureWrite();
4021  InitReg(MISCREG_AT_S12E0W_Xt)
4022  .hypWrite().monSecureWrite().monNonSecureWrite();
4023  InitReg(MISCREG_AT_S1E3R_Xt)
4024  .monSecureWrite().monNonSecureWrite();
4025  InitReg(MISCREG_AT_S1E3W_Xt)
4026  .monSecureWrite().monNonSecureWrite();
4027  InitReg(MISCREG_TLBI_VMALLE1IS)
4028  .faultWrite(EL1, HCR_TRAP(ttlb))
4029  .writes(1).exceptUserMode();
4030  InitReg(MISCREG_TLBI_VAE1IS_Xt)
4031  .faultWrite(EL1, HCR_TRAP(ttlb))
4032  .writes(1).exceptUserMode();
4033  InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
4034  .faultWrite(EL1, HCR_TRAP(ttlb))
4035  .writes(1).exceptUserMode();
4036  InitReg(MISCREG_TLBI_VAAE1IS_Xt)
4037  .faultWrite(EL1, HCR_TRAP(ttlb))
4038  .writes(1).exceptUserMode();
4039  InitReg(MISCREG_TLBI_VALE1IS_Xt)
4040  .faultWrite(EL1, HCR_TRAP(ttlb))
4041  .writes(1).exceptUserMode();
4042  InitReg(MISCREG_TLBI_VAALE1IS_Xt)
4043  .faultWrite(EL1, HCR_TRAP(ttlb))
4044  .writes(1).exceptUserMode();
4045  InitReg(MISCREG_TLBI_VMALLE1)
4046  .faultWrite(EL1, HCR_TRAP(ttlb))
4047  .writes(1).exceptUserMode();
4048  InitReg(MISCREG_TLBI_VAE1_Xt)
4049  .faultWrite(EL1, HCR_TRAP(ttlb))
4050  .writes(1).exceptUserMode();
4051  InitReg(MISCREG_TLBI_ASIDE1_Xt)
4052  .faultWrite(EL1, HCR_TRAP(ttlb))
4053  .writes(1).exceptUserMode();
4054  InitReg(MISCREG_TLBI_VAAE1_Xt)
4055  .faultWrite(EL1, HCR_TRAP(ttlb))
4056  .writes(1).exceptUserMode();
4057  InitReg(MISCREG_TLBI_VALE1_Xt)
4058  .faultWrite(EL1, HCR_TRAP(ttlb))
4059  .writes(1).exceptUserMode();
4060  InitReg(MISCREG_TLBI_VAALE1_Xt)
4061  .faultWrite(EL1, HCR_TRAP(ttlb))
4062  .writes(1).exceptUserMode();
4063  InitReg(MISCREG_TLBI_IPAS2E1IS_Xt)
4064  .hypWrite().monSecureWrite().monNonSecureWrite();
4065  InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt)
4066  .hypWrite().monSecureWrite().monNonSecureWrite();
4067  InitReg(MISCREG_TLBI_ALLE2IS)
4068  .monNonSecureWrite().hypWrite();
4069  InitReg(MISCREG_TLBI_VAE2IS_Xt)
4070  .monNonSecureWrite().hypWrite();
4071  InitReg(MISCREG_TLBI_ALLE1IS)
4072  .hypWrite().monSecureWrite().monNonSecureWrite();
4073  InitReg(MISCREG_TLBI_VALE2IS_Xt)
4074  .monNonSecureWrite().hypWrite();
4075  InitReg(MISCREG_TLBI_VMALLS12E1IS)
4076  .hypWrite().monSecureWrite().monNonSecureWrite();
4077  InitReg(MISCREG_TLBI_IPAS2E1_Xt)
4078  .hypWrite().monSecureWrite().monNonSecureWrite();
4079  InitReg(MISCREG_TLBI_IPAS2LE1_Xt)
4080  .hypWrite().monSecureWrite().monNonSecureWrite();
4081  InitReg(MISCREG_TLBI_ALLE2)
4082  .monNonSecureWrite().hypWrite();
4083  InitReg(MISCREG_TLBI_VAE2_Xt)
4084  .monNonSecureWrite().hypWrite();
4085  InitReg(MISCREG_TLBI_ALLE1)
4086  .hypWrite().monSecureWrite().monNonSecureWrite();
4087  InitReg(MISCREG_TLBI_VALE2_Xt)
4088  .monNonSecureWrite().hypWrite();
4089  InitReg(MISCREG_TLBI_VMALLS12E1)
4090  .hypWrite().monSecureWrite().monNonSecureWrite();
4091  InitReg(MISCREG_TLBI_ALLE3IS)
4092  .monSecureWrite().monNonSecureWrite();
4093  InitReg(MISCREG_TLBI_VAE3IS_Xt)
4094  .monSecureWrite().monNonSecureWrite();
4095  InitReg(MISCREG_TLBI_VALE3IS_Xt)
4096  .monSecureWrite().monNonSecureWrite();
4097  InitReg(MISCREG_TLBI_ALLE3)
4098  .monSecureWrite().monNonSecureWrite();
4099  InitReg(MISCREG_TLBI_VAE3_Xt)
4100  .monSecureWrite().monNonSecureWrite();
4101  InitReg(MISCREG_TLBI_VALE3_Xt)
4102  .monSecureWrite().monNonSecureWrite();
4103  InitReg(MISCREG_PMINTENSET_EL1)
4104  .allPrivileges().exceptUserMode()
4105  .mapsTo(MISCREG_PMINTENSET);
4106  InitReg(MISCREG_PMINTENCLR_EL1)
4107  .allPrivileges().exceptUserMode()
4108  .mapsTo(MISCREG_PMINTENCLR);
4109  InitReg(MISCREG_PMCR_EL0)
4110  .allPrivileges()
4111  .mapsTo(MISCREG_PMCR);
4112  InitReg(MISCREG_PMCNTENSET_EL0)
4113  .allPrivileges()
4114  .mapsTo(MISCREG_PMCNTENSET);
4115  InitReg(MISCREG_PMCNTENCLR_EL0)
4116  .allPrivileges()
4117  .mapsTo(MISCREG_PMCNTENCLR);
4118  InitReg(MISCREG_PMOVSCLR_EL0)
4119  .allPrivileges();
4120 // .mapsTo(MISCREG_PMOVSCLR);
4121  InitReg(MISCREG_PMSWINC_EL0)
4122  .writes(1).user()
4123  .mapsTo(MISCREG_PMSWINC);
4124  InitReg(MISCREG_PMSELR_EL0)
4125  .allPrivileges()
4126  .mapsTo(MISCREG_PMSELR);
4127  InitReg(MISCREG_PMCEID0_EL0)
4128  .reads(1).user()
4129  .mapsTo(MISCREG_PMCEID0);
4130  InitReg(MISCREG_PMCEID1_EL0)
4131  .reads(1).user()
4132  .mapsTo(MISCREG_PMCEID1);
4133  InitReg(MISCREG_PMCCNTR_EL0)
4134  .allPrivileges()
4135  .mapsTo(MISCREG_PMCCNTR);
4136  InitReg(MISCREG_PMXEVTYPER_EL0)
4137  .allPrivileges()
4138  .mapsTo(MISCREG_PMXEVTYPER);
4139  InitReg(MISCREG_PMCCFILTR_EL0)
4140  .allPrivileges();
4141  InitReg(MISCREG_PMXEVCNTR_EL0)
4142  .allPrivileges()
4143  .mapsTo(MISCREG_PMXEVCNTR);
4144  InitReg(MISCREG_PMUSERENR_EL0)
4145  .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
4146  .mapsTo(MISCREG_PMUSERENR);
4147  InitReg(MISCREG_PMOVSSET_EL0)
4148  .allPrivileges()
4149  .mapsTo(MISCREG_PMOVSSET);
4150  InitReg(MISCREG_MAIR_EL1)
4151  .allPrivileges().exceptUserMode()
4152  .faultRead(EL1, HCR_TRAP(trvm))
4153  .faultWrite(EL1, HCR_TRAP(tvm))
4154  .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
4155  InitReg(MISCREG_MAIR_EL12)
4156  .fault(EL2, defaultFaultE2H_EL2)
4157  .fault(EL3, defaultFaultE2H_EL3)
4158  .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
4159  InitReg(MISCREG_AMAIR_EL1)
4160  .allPrivileges().exceptUserMode()
4161  .faultRead(EL1, HCR_TRAP(trvm))
4162  .faultWrite(EL1, HCR_TRAP(tvm))
4163  .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
4164  InitReg(MISCREG_AMAIR_EL12)
4165  .fault(EL2, defaultFaultE2H_EL2)
4166  .fault(EL3, defaultFaultE2H_EL3)
4167  .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
4168  InitReg(MISCREG_MAIR_EL2)
4169  .hyp().mon()
4170  .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1);
4171  InitReg(MISCREG_AMAIR_EL2)
4172  .hyp().mon()
4173  .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1);
4174  InitReg(MISCREG_MAIR_EL3)
4175  .mon();
4176  InitReg(MISCREG_AMAIR_EL3)
4177  .mon();
4178  InitReg(MISCREG_L2CTLR_EL1)
4179  .allPrivileges().exceptUserMode();
4180  InitReg(MISCREG_L2ECTLR_EL1)
4181  .allPrivileges().exceptUserMode();
4182  InitReg(MISCREG_VBAR_EL1)
4183  .allPrivileges().exceptUserMode()
4184  .mapsTo(MISCREG_VBAR_NS);
4185  InitReg(MISCREG_VBAR_EL12)
4186  .fault(EL2, defaultFaultE2H_EL2)
4187  .fault(EL3, defaultFaultE2H_EL3)
4188  .mapsTo(MISCREG_VBAR_NS);
4189  InitReg(MISCREG_RVBAR_EL1)
4190  .privRead(FullSystem && system->highestEL() == EL1);
4191  InitReg(MISCREG_ISR_EL1)
4192  .allPrivileges().exceptUserMode().writes(0);
4193  InitReg(MISCREG_VBAR_EL2)
4194  .hyp().mon()
4195  .res0(0x7ff)
4196  .mapsTo(MISCREG_HVBAR);
4197  InitReg(MISCREG_RVBAR_EL2)
4198  .hypRead(FullSystem && system->highestEL() == EL2);
4199  InitReg(MISCREG_VBAR_EL3)
4200  .mon();
4201  InitReg(MISCREG_RVBAR_EL3)
4202  .mon().writes(0);
4203  InitReg(MISCREG_RMR_EL3)
4204  .mon();
4205  InitReg(MISCREG_CONTEXTIDR_EL1)
4206  .allPrivileges().exceptUserMode()
4207  .faultRead(EL1, HCR_TRAP(trvm))
4208  .faultWrite(EL1, HCR_TRAP(tvm))
4209  .mapsTo(MISCREG_CONTEXTIDR_NS);
4210  InitReg(MISCREG_CONTEXTIDR_EL12)
4211  .fault(EL2, defaultFaultE2H_EL2)
4212  .fault(EL3, defaultFaultE2H_EL3)
4213  .mapsTo(MISCREG_CONTEXTIDR_NS);
4214  InitReg(MISCREG_TPIDR_EL1)
4215  .allPrivileges().exceptUserMode()
4216  .mapsTo(MISCREG_TPIDRPRW_NS);
4217  InitReg(MISCREG_TPIDR_EL0)
4218  .allPrivileges()
4219  .mapsTo(MISCREG_TPIDRURW_NS);
4220  InitReg(MISCREG_TPIDRRO_EL0)
4221  .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
4222  .mapsTo(MISCREG_TPIDRURO_NS);
4223  InitReg(MISCREG_TPIDR_EL2)
4224  .hyp().mon()
4225  .mapsTo(MISCREG_HTPIDR);
4226  InitReg(MISCREG_TPIDR_EL3)
4227  .mon();
4228  // BEGIN Generic Timer (AArch64)
4229  InitReg(MISCREG_CNTFRQ_EL0)
4230  .reads(1)
4231  .faultRead(EL0, faultGenericTimerEL0)
4232  .highest(system)
4233  .privSecureWrite(aarch32EL3)
4234  .mapsTo(MISCREG_CNTFRQ);
4235  InitReg(MISCREG_CNTPCT_EL0)
4236  .unverifiable()
4237  .faultRead(EL0, faultCntpctEL0)
4238  .faultRead(EL1, faultCntpctEL1)
4239  .reads(1)
4240  .mapsTo(MISCREG_CNTPCT);
4241  InitReg(MISCREG_CNTVCT_EL0)
4242  .unverifiable()
4243  .faultRead(EL0, faultCntvctEL0)
4244  .faultRead(EL1, faultCntvctEL1)
4245  .reads(1)
4246  .mapsTo(MISCREG_CNTVCT);
4247  InitReg(MISCREG_CNTP_CTL_EL0)
4248  .allPrivileges()
4249  .fault(EL0, faultCntpCtlEL0)
4250  .fault(EL1, faultCntpCtlEL1)
4251  .res0(0xfffffffffffffff8)
4252  .mapsTo(MISCREG_CNTP_CTL_NS);
4253  InitReg(MISCREG_CNTP_CVAL_EL0)
4254  .allPrivileges()
4255  .fault(EL0, faultCntpCtlEL0)
4256  .fault(EL1, faultCntpCtlEL1)
4257  .mapsTo(MISCREG_CNTP_CVAL_NS);
4258  InitReg(MISCREG_CNTP_TVAL_EL0)
4259  .allPrivileges()
4260  .fault(EL0, faultCntpCtlEL0)
4261  .fault(EL1, faultCntpCtlEL1)
4262  .res0(0xffffffff00000000)
4263  .mapsTo(MISCREG_CNTP_TVAL_NS);
4264  InitReg(MISCREG_CNTV_CTL_EL0)
4265  .allPrivileges()
4266  .fault(EL0, faultCntvCtlEL0)
4267  .fault(EL1, faultCntvCtlEL1)
4268  .res0(0xfffffffffffffff8)
4269  .mapsTo(MISCREG_CNTV_CTL);
4270  InitReg(MISCREG_CNTV_CVAL_EL0)
4271  .allPrivileges()
4272  .fault(EL0, faultCntvCtlEL0)
4273  .fault(EL1, faultCntvCtlEL1)
4274  .mapsTo(MISCREG_CNTV_CVAL);
4275  InitReg(MISCREG_CNTV_TVAL_EL0)
4276  .allPrivileges()
4277  .fault(EL0, faultCntvCtlEL0)
4278  .fault(EL1, faultCntvCtlEL1)
4279  .res0(0xffffffff00000000)
4280  .mapsTo(MISCREG_CNTV_TVAL);
4281  InitReg(MISCREG_CNTP_CTL_EL02)
4282  .fault(EL2, defaultFaultE2H_EL2)
4283  .fault(EL3, defaultFaultE2H_EL3)
4284  .res0(0xfffffffffffffff8)
4285  .mapsTo(MISCREG_CNTP_CTL_NS);
4286  InitReg(MISCREG_CNTP_CVAL_EL02)
4287  .fault(EL2, defaultFaultE2H_EL2)
4288  .fault(EL3, defaultFaultE2H_EL3)
4289  .mapsTo(MISCREG_CNTP_CVAL_NS);
4290  InitReg(MISCREG_CNTP_TVAL_EL02)
4291  .fault(EL2, defaultFaultE2H_EL2)
4292  .fault(EL3, defaultFaultE2H_EL3)
4293  .res0(0xffffffff00000000)
4294  .mapsTo(MISCREG_CNTP_TVAL_NS);
4295  InitReg(MISCREG_CNTV_CTL_EL02)
4296  .fault(EL2, defaultFaultE2H_EL2)
4297  .fault(EL3, defaultFaultE2H_EL3)
4298  .res0(0xfffffffffffffff8)
4299  .mapsTo(MISCREG_CNTV_CTL);
4300  InitReg(MISCREG_CNTV_CVAL_EL02)
4301  .fault(EL2, defaultFaultE2H_EL2)
4302  .fault(EL3, defaultFaultE2H_EL3)
4303  .mapsTo(MISCREG_CNTV_CVAL);
4304  InitReg(MISCREG_CNTV_TVAL_EL02)
4305  .fault(EL2, defaultFaultE2H_EL2)
4306  .fault(EL3, defaultFaultE2H_EL3)
4307  .res0(0xffffffff00000000)
4308  .mapsTo(MISCREG_CNTV_TVAL);
4309  InitReg(MISCREG_CNTKCTL_EL1)
4310  .allPrivileges()
4311  .exceptUserMode()
4312  .res0(0xfffffffffffdfc00)
4313  .mapsTo(MISCREG_CNTKCTL);
4314  InitReg(MISCREG_CNTKCTL_EL12)
4315  .fault(EL2, defaultFaultE2H_EL2)
4316  .fault(EL3, defaultFaultE2H_EL3)
4317  .res0(0xfffffffffffdfc00)
4318  .mapsTo(MISCREG_CNTKCTL);
4319  InitReg(MISCREG_CNTPS_CTL_EL1)
4320  .mon()
4321  .privSecure()
4322  .fault(EL1, faultCntpsCtlEL1)
4323  .res0(0xfffffffffffffff8);
4324  InitReg(MISCREG_CNTPS_CVAL_EL1)
4325  .mon()
4326  .privSecure()
4327  .fault(EL1, faultCntpsCtlEL1);
4328  InitReg(MISCREG_CNTPS_TVAL_EL1)
4329  .mon()
4330  .privSecure()
4331  .fault(EL1, faultCntpsCtlEL1)
4332  .res0(0xffffffff00000000);
4333  InitReg(MISCREG_CNTHCTL_EL2)
4334  .mon()
4335  .hyp()
4336  .res0(0xfffffffffffc0000)
4337  .mapsTo(MISCREG_CNTHCTL);
4338  InitReg(MISCREG_CNTHP_CTL_EL2)
4339  .mon()
4340  .hyp()
4341  .res0(0xfffffffffffffff8)
4342  .mapsTo(MISCREG_CNTHP_CTL);
4343  InitReg(MISCREG_CNTHP_CVAL_EL2)
4344  .mon()
4345  .hyp()
4346  .mapsTo(MISCREG_CNTHP_CVAL);
4347  InitReg(MISCREG_CNTHP_TVAL_EL2)
4348  .mon()
4349  .hyp()
4350  .res0(0xffffffff00000000)
4351  .mapsTo(MISCREG_CNTHP_TVAL);
4352  InitReg(MISCREG_CNTHPS_CTL_EL2)
4353  .mon(sel2_implemented)
4354  .hypSecure(sel2_implemented)
4355  .res0(0xfffffffffffffff8);
4356  InitReg(MISCREG_CNTHPS_CVAL_EL2)
4357  .mon(sel2_implemented)
4358  .hypSecure(sel2_implemented);
4359  InitReg(MISCREG_CNTHPS_TVAL_EL2)
4360  .mon(sel2_implemented)
4361  .hypSecure(sel2_implemented)
4362  .res0(0xffffffff00000000);
4363  InitReg(MISCREG_CNTHV_CTL_EL2)
4364  .mon(vhe_implemented)
4365  .hyp()
4366  .res0(0xfffffffffffffff8);
4367  InitReg(MISCREG_CNTHV_CVAL_EL2)
4368  .mon(vhe_implemented)
4369  .hyp(vhe_implemented);
4370  InitReg(MISCREG_CNTHV_TVAL_EL2)
4371  .mon(vhe_implemented)
4372  .hyp(vhe_implemented)
4373  .res0(0xffffffff00000000);
4374  InitReg(MISCREG_CNTHVS_CTL_EL2)
4375  .mon(vhe_implemented && sel2_implemented)
4376  .hypSecure(vhe_implemented && sel2_implemented)
4377  .res0(0xfffffffffffffff8);
4378  InitReg(MISCREG_CNTHVS_CVAL_EL2)
4379  .mon(vhe_implemented && sel2_implemented)
4380  .hypSecure(vhe_implemented && sel2_implemented);
4381  InitReg(MISCREG_CNTHVS_TVAL_EL2)
4382  .mon(vhe_implemented && sel2_implemented)
4383  .hypSecure(vhe_implemented && sel2_implemented)
4384  .res0(0xffffffff00000000);
4385  // ENDIF Armv8.1-VHE
4386  InitReg(MISCREG_CNTVOFF_EL2)
4387  .mon()
4388  .hyp()
4389  .mapsTo(MISCREG_CNTVOFF);
4390  // END Generic Timer (AArch64)
4391  InitReg(MISCREG_PMEVCNTR0_EL0)
4392  .allPrivileges();
4393 // .mapsTo(MISCREG_PMEVCNTR0);
4394  InitReg(MISCREG_PMEVCNTR1_EL0)
4395  .allPrivileges();
4396 // .mapsTo(MISCREG_PMEVCNTR1);
4397  InitReg(MISCREG_PMEVCNTR2_EL0)
4398  .allPrivileges();
4399 // .mapsTo(MISCREG_PMEVCNTR2);
4400  InitReg(MISCREG_PMEVCNTR3_EL0)
4401  .allPrivileges();
4402 // .mapsTo(MISCREG_PMEVCNTR3);
4403  InitReg(MISCREG_PMEVCNTR4_EL0)
4404  .allPrivileges();
4405 // .mapsTo(MISCREG_PMEVCNTR4);
4406  InitReg(MISCREG_PMEVCNTR5_EL0)
4407  .allPrivileges();
4408 // .mapsTo(MISCREG_PMEVCNTR5);
4409  InitReg(MISCREG_PMEVTYPER0_EL0)
4410  .allPrivileges();
4411 // .mapsTo(MISCREG_PMEVTYPER0);
4412  InitReg(MISCREG_PMEVTYPER1_EL0)
4413  .allPrivileges();
4414 // .mapsTo(MISCREG_PMEVTYPER1);
4415  InitReg(MISCREG_PMEVTYPER2_EL0)
4416  .allPrivileges();
4417 // .mapsTo(MISCREG_PMEVTYPER2);
4418  InitReg(MISCREG_PMEVTYPER3_EL0)
4419  .allPrivileges();
4420 // .mapsTo(MISCREG_PMEVTYPER3);
4421  InitReg(MISCREG_PMEVTYPER4_EL0)
4422  .allPrivileges();
4423 // .mapsTo(MISCREG_PMEVTYPER4);
4424  InitReg(MISCREG_PMEVTYPER5_EL0)
4425  .allPrivileges();
4426 // .mapsTo(MISCREG_PMEVTYPER5);
4427  InitReg(MISCREG_IL1DATA0_EL1)
4428  .allPrivileges().exceptUserMode();
4429  InitReg(MISCREG_IL1DATA1_EL1)
4430  .allPrivileges().exceptUserMode();
4431  InitReg(MISCREG_IL1DATA2_EL1)
4432  .allPrivileges().exceptUserMode();
4433  InitReg(MISCREG_IL1DATA3_EL1)
4434  .allPrivileges().exceptUserMode();
4435  InitReg(MISCREG_DL1DATA0_EL1)
4436  .allPrivileges().exceptUserMode();
4437  InitReg(MISCREG_DL1DATA1_EL1)
4438  .allPrivileges().exceptUserMode();
4439  InitReg(MISCREG_DL1DATA2_EL1)
4440  .allPrivileges().exceptUserMode();
4441  InitReg(MISCREG_DL1DATA3_EL1)
4442  .allPrivileges().exceptUserMode();
4443  InitReg(MISCREG_DL1DATA4_EL1)
4444  .allPrivileges().exceptUserMode();
4445  InitReg(MISCREG_L2ACTLR_EL1)
4446  .allPrivileges().exceptUserMode();
4447  InitReg(MISCREG_CPUACTLR_EL1)
4448  .allPrivileges().exceptUserMode();
4449  InitReg(MISCREG_CPUECTLR_EL1)
4450  .allPrivileges().exceptUserMode();
4451  InitReg(MISCREG_CPUMERRSR_EL1)
4452  .allPrivileges().exceptUserMode();
4453  InitReg(MISCREG_L2MERRSR_EL1)
4454  .warnNotFail()
4455  .fault(faultUnimplemented);
4456  InitReg(MISCREG_CBAR_EL1)
4457  .allPrivileges().exceptUserMode().writes(0);
4458  InitReg(MISCREG_CONTEXTIDR_EL2)
4459  .mon().hyp();
4460 
4461  // GICv3 AArch64
4462  InitReg(MISCREG_ICC_PMR_EL1)
4463  .res0(0xffffff00) // [31:8]
4464  .allPrivileges().exceptUserMode()
4465  .mapsTo(MISCREG_ICC_PMR);
4466  InitReg(MISCREG_ICC_IAR0_EL1)
4467  .allPrivileges().exceptUserMode().writes(0)
4468  .mapsTo(MISCREG_ICC_IAR0);
4469  InitReg(MISCREG_ICC_EOIR0_EL1)
4470  .allPrivileges().exceptUserMode().reads(0)
4471  .mapsTo(MISCREG_ICC_EOIR0);
4472  InitReg(MISCREG_ICC_HPPIR0_EL1)
4473  .allPrivileges().exceptUserMode().writes(0)
4474  .mapsTo(MISCREG_ICC_HPPIR0);
4475  InitReg(MISCREG_ICC_BPR0_EL1)
4476  .res0(0xfffffff8) // [31:3]
4477  .allPrivileges().exceptUserMode()
4478  .mapsTo(MISCREG_ICC_BPR0);
4479  InitReg(MISCREG_ICC_AP0R0_EL1)
4480  .allPrivileges().exceptUserMode()
4481  .mapsTo(MISCREG_ICC_AP0R0);
4482  InitReg(MISCREG_ICC_AP0R1_EL1)
4483  .allPrivileges().exceptUserMode()
4484  .mapsTo(MISCREG_ICC_AP0R1);
4485  InitReg(MISCREG_ICC_AP0R2_EL1)
4486  .allPrivileges().exceptUserMode()
4487  .mapsTo(MISCREG_ICC_AP0R2);
4488  InitReg(MISCREG_ICC_AP0R3_EL1)
4489  .allPrivileges().exceptUserMode()
4490  .mapsTo(MISCREG_ICC_AP0R3);
4491  InitReg(MISCREG_ICC_AP1R0_EL1)
4492  .banked64()
4493  .mapsTo(MISCREG_ICC_AP1R0);
4494  InitReg(MISCREG_ICC_AP1R0_EL1_NS)
4495  .bankedChild()
4496  .allPrivileges().exceptUserMode()
4497  .mapsTo(MISCREG_ICC_AP1R0_NS);
4498  InitReg(MISCREG_ICC_AP1R0_EL1_S)
4499  .bankedChild()
4500  .allPrivileges().exceptUserMode()
4501  .mapsTo(MISCREG_ICC_AP1R0_S);
4502  InitReg(MISCREG_ICC_AP1R1_EL1)
4503  .banked64()
4504  .mapsTo(MISCREG_ICC_AP1R1);
4505  InitReg(MISCREG_ICC_AP1R1_EL1_NS)
4506  .bankedChild()
4507  .allPrivileges().exceptUserMode()
4508  .mapsTo(MISCREG_ICC_AP1R1_NS);
4509  InitReg(MISCREG_ICC_AP1R1_EL1_S)
4510  .bankedChild()
4511  .allPrivileges().exceptUserMode()
4512  .mapsTo(MISCREG_ICC_AP1R1_S);
4513  InitReg(MISCREG_ICC_AP1R2_EL1)
4514  .banked64()
4515  .mapsTo(MISCREG_ICC_AP1R2);
4516  InitReg(MISCREG_ICC_AP1R2_EL1_NS)
4517  .bankedChild()
4518  .allPrivileges().exceptUserMode()
4519  .mapsTo(MISCREG_ICC_AP1R2_NS);
4520  InitReg(MISCREG_ICC_AP1R2_EL1_S)
4521  .bankedChild()
4522  .allPrivileges().exceptUserMode()
4523  .mapsTo(MISCREG_ICC_AP1R2_S);
4524  InitReg(MISCREG_ICC_AP1R3_EL1)
4525  .banked64()
4526  .mapsTo(MISCREG_ICC_AP1R3);
4527  InitReg(MISCREG_ICC_AP1R3_EL1_NS)
4528  .bankedChild()
4529  .allPrivileges().exceptUserMode()
4530  .mapsTo(MISCREG_ICC_AP1R3_NS);
4531  InitReg(MISCREG_ICC_AP1R3_EL1_S)
4532  .bankedChild()
4533  .allPrivileges().exceptUserMode()
4534  .mapsTo(MISCREG_ICC_AP1R3_S);
4535  InitReg(MISCREG_ICC_DIR_EL1)
4536  .res0(0xFF000000) // [31:24]
4537  .allPrivileges().exceptUserMode().reads(0)
4538  .mapsTo(MISCREG_ICC_DIR);
4539  InitReg(MISCREG_ICC_RPR_EL1)
4540  .allPrivileges().exceptUserMode().writes(0)
4541  .mapsTo(MISCREG_ICC_RPR);
4542  InitReg(MISCREG_ICC_SGI1R_EL1)
4543  .allPrivileges().exceptUserMode().reads(0)
4544  .faultWrite(EL1, faultIccSgiEL1)
4545  .faultWrite(EL2, faultIccSgiEL2)
4546  .mapsTo(MISCREG_ICC_SGI1R);
4547  InitReg(MISCREG_ICC_ASGI1R_EL1)
4548  .allPrivileges().exceptUserMode().reads(0)
4549  .faultWrite(EL1, faultIccSgiEL1)
4550  .faultWrite(EL2, faultIccSgiEL2)
4551  .mapsTo(MISCREG_ICC_ASGI1R);
4552  InitReg(MISCREG_ICC_SGI0R_EL1)
4553  .allPrivileges().exceptUserMode().reads(0)
4554  .faultWrite(EL1, faultIccSgiEL1)
4555  .faultWrite(EL2, faultIccSgiEL2)
4556  .mapsTo(MISCREG_ICC_SGI0R);
4557  InitReg(MISCREG_ICC_IAR1_EL1)
4558  .allPrivileges().exceptUserMode().writes(0)
4559  .mapsTo(MISCREG_ICC_IAR1);
4560  InitReg(MISCREG_ICC_EOIR1_EL1)
4561  .res0(0xFF000000) // [31:24]
4562  .allPrivileges().exceptUserMode().reads(0)
4563  .mapsTo(MISCREG_ICC_EOIR1);
4564  InitReg(MISCREG_ICC_HPPIR1_EL1)
4565  .allPrivileges().exceptUserMode().writes(0)
4566  .mapsTo(MISCREG_ICC_HPPIR1);
4567  InitReg(MISCREG_ICC_BPR1_EL1)
4568  .banked64()
4569  .mapsTo(MISCREG_ICC_BPR1);
4570  InitReg(MISCREG_ICC_BPR1_EL1_NS)
4571  .bankedChild()
4572  .res0(0xfffffff8) // [31:3]
4573  .allPrivileges().exceptUserMode()
4574  .mapsTo(MISCREG_ICC_BPR1_NS);
4575  InitReg(MISCREG_ICC_BPR1_EL1_S)
4576  .bankedChild()
4577  .res0(0xfffffff8) // [31:3]
4578  .secure().exceptUserMode()
4579  .mapsTo(MISCREG_ICC_BPR1_S);
4580  InitReg(MISCREG_ICC_CTLR_EL1)
4581  .banked64()
4582  .mapsTo(MISCREG_ICC_CTLR);
4583  InitReg(MISCREG_ICC_CTLR_EL1_NS)
4584  .bankedChild()
4585  .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
4586  .allPrivileges().exceptUserMode()
4587  .mapsTo(MISCREG_ICC_CTLR_NS);
4588  InitReg(MISCREG_ICC_CTLR_EL1_S)
4589  .bankedChild()
4590  .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
4591  .secure().exceptUserMode()
4592  .mapsTo(MISCREG_ICC_CTLR_S);
4593  InitReg(MISCREG_ICC_SRE_EL1)
4594  .banked()
4595  .mapsTo(MISCREG_ICC_SRE);
4596  InitReg(MISCREG_ICC_SRE_EL1_NS)
4597  .bankedChild()
4598  .res0(0xFFFFFFF8) // [31:3]
4599  .allPrivileges().exceptUserMode()
4600  .mapsTo(MISCREG_ICC_SRE_NS);
4601  InitReg(MISCREG_ICC_SRE_EL1_S)
4602  .bankedChild()
4603  .res0(0xFFFFFFF8) // [31:3]
4604  .secure().exceptUserMode()
4605  .mapsTo(MISCREG_ICC_SRE_S);
4606  InitReg(MISCREG_ICC_IGRPEN0_EL1)
4607  .res0(0xFFFFFFFE) // [31:1]
4608  .allPrivileges().exceptUserMode()
4609  .mapsTo(MISCREG_ICC_IGRPEN0);
4610  InitReg(MISCREG_ICC_IGRPEN1_EL1)
4611  .banked64()
4612  .mapsTo(MISCREG_ICC_IGRPEN1);
4613  InitReg(MISCREG_ICC_IGRPEN1_EL1_NS)
4614  .bankedChild()
4615  .res0(0xFFFFFFFE) // [31:1]
4616  .allPrivileges().exceptUserMode()
4617  .mapsTo(MISCREG_ICC_IGRPEN1_NS);
4618  InitReg(MISCREG_ICC_IGRPEN1_EL1_S)
4619  .bankedChild()
4620  .res0(0xFFFFFFFE) // [31:1]
4621  .secure().exceptUserMode()
4622  .mapsTo(MISCREG_ICC_IGRPEN1_S);
4623  InitReg(MISCREG_ICC_SRE_EL2)
4624  .hyp().mon()
4625  .mapsTo(MISCREG_ICC_HSRE);
4626  InitReg(MISCREG_ICC_CTLR_EL3)
4627  .mon()
4628  .mapsTo(MISCREG_ICC_MCTLR);
4629  InitReg(MISCREG_ICC_SRE_EL3)
4630  .mon()
4631  .mapsTo(MISCREG_ICC_MSRE);
4632  InitReg(MISCREG_ICC_IGRPEN1_EL3)
4633  .mon()
4634  .mapsTo(MISCREG_ICC_MGRPEN1);
4635 
4636  InitReg(MISCREG_ICH_AP0R0_EL2)
4637  .hyp().mon()
4638  .mapsTo(MISCREG_ICH_AP0R0);
4639  InitReg(MISCREG_ICH_AP0R1_EL2)
4640  .hyp().mon()
4641  .mapsTo(MISCREG_ICH_AP0R1);
4642  InitReg(MISCREG_ICH_AP0R2_EL2)
4643  .hyp().mon()
4644  .mapsTo(MISCREG_ICH_AP0R2);
4645  InitReg(MISCREG_ICH_AP0R3_EL2)
4646  .hyp().mon()
4647  .mapsTo(MISCREG_ICH_AP0R3);
4648  InitReg(MISCREG_ICH_AP1R0_EL2)
4649  .hyp().mon()
4650  .mapsTo(MISCREG_ICH_AP1R0);
4651  InitReg(MISCREG_ICH_AP1R1_EL2)
4652  .hyp().mon()
4653  .mapsTo(MISCREG_ICH_AP1R1);
4654  InitReg(MISCREG_ICH_AP1R2_EL2)
4655  .hyp().mon()
4656  .mapsTo(MISCREG_ICH_AP1R2);
4657  InitReg(MISCREG_ICH_AP1R3_EL2)
4658  .hyp().mon()
4659  .mapsTo(MISCREG_ICH_AP1R3);
4660  InitReg(MISCREG_ICH_HCR_EL2)
4661  .hyp().mon()
4662  .mapsTo(MISCREG_ICH_HCR);
4663  InitReg(MISCREG_ICH_VTR_EL2)
4664  .hyp().mon().writes(0)
4665  .mapsTo(MISCREG_ICH_VTR);
4666  InitReg(MISCREG_ICH_MISR_EL2)
4667  .hyp().mon().writes(0)
4668  .mapsTo(MISCREG_ICH_MISR);
4669  InitReg(MISCREG_ICH_EISR_EL2)
4670  .hyp().mon().writes(0)
4671  .mapsTo(MISCREG_ICH_EISR);
4672  InitReg(MISCREG_ICH_ELRSR_EL2)
4673  .hyp().mon().writes(0)
4674  .mapsTo(MISCREG_ICH_ELRSR);
4675  InitReg(MISCREG_ICH_VMCR_EL2)
4676  .hyp().mon()
4677  .mapsTo(MISCREG_ICH_VMCR);
4678  InitReg(MISCREG_ICH_LR0_EL2)
4679  .hyp().mon()
4680  .mapsTo(MISCREG_ICH_LR0, MISCREG_ICH_LRC0);
4681  InitReg(MISCREG_ICH_LR1_EL2)
4682  .hyp().mon()
4683  .mapsTo(MISCREG_ICH_LR1, MISCREG_ICH_LRC1);
4684  InitReg(MISCREG_ICH_LR2_EL2)
4685  .hyp().mon()
4686  .mapsTo(MISCREG_ICH_LR2, MISCREG_ICH_LRC2);
4687  InitReg(MISCREG_ICH_LR3_EL2)
4688  .hyp().mon()
4689  .mapsTo(MISCREG_ICH_LR3, MISCREG_ICH_LRC3);
4690  InitReg(MISCREG_ICH_LR4_EL2)
4691  .hyp().mon()
4692  .mapsTo(MISCREG_ICH_LR4, MISCREG_ICH_LRC4);
4693  InitReg(MISCREG_ICH_LR5_EL2)
4694  .hyp().mon()
4695  .mapsTo(MISCREG_ICH_LR5, MISCREG_ICH_LRC5);
4696  InitReg(MISCREG_ICH_LR6_EL2)
4697  .hyp().mon()
4698  .mapsTo(MISCREG_ICH_LR6, MISCREG_ICH_LRC6);
4699  InitReg(MISCREG_ICH_LR7_EL2)
4700  .hyp().mon()
4701  .mapsTo(MISCREG_ICH_LR7, MISCREG_ICH_LRC7);
4702  InitReg(MISCREG_ICH_LR8_EL2)
4703  .hyp().mon()
4704  .mapsTo(MISCREG_ICH_LR8, MISCREG_ICH_LRC8);
4705  InitReg(MISCREG_ICH_LR9_EL2)
4706  .hyp().mon()
4707  .mapsTo(MISCREG_ICH_LR9, MISCREG_ICH_LRC9);
4708  InitReg(MISCREG_ICH_LR10_EL2)
4709  .hyp().mon()
4710  .mapsTo(MISCREG_ICH_LR10, MISCREG_ICH_LRC10);
4711  InitReg(MISCREG_ICH_LR11_EL2)
4712  .hyp().mon()
4713  .mapsTo(MISCREG_ICH_LR11, MISCREG_ICH_LRC11);
4714  InitReg(MISCREG_ICH_LR12_EL2)
4715  .hyp().mon()
4716  .mapsTo(MISCREG_ICH_LR12, MISCREG_ICH_LRC12);
4717  InitReg(MISCREG_ICH_LR13_EL2)
4718  .hyp().mon()
4719  .mapsTo(MISCREG_ICH_LR13, MISCREG_ICH_LRC13);
4720  InitReg(MISCREG_ICH_LR14_EL2)
4721  .hyp().mon()
4722  .mapsTo(MISCREG_ICH_LR14, MISCREG_ICH_LRC14);
4723  InitReg(MISCREG_ICH_LR15_EL2)
4724  .hyp().mon()
4725  .mapsTo(MISCREG_ICH_LR15, MISCREG_ICH_LRC15);
4726 
4727  // GICv3 AArch32
4728  InitReg(MISCREG_ICC_AP0R0)
4729  .allPrivileges().exceptUserMode();
4730  InitReg(MISCREG_ICC_AP0R1)
4731  .allPrivileges().exceptUserMode();
4732  InitReg(MISCREG_ICC_AP0R2)
4733  .allPrivileges().exceptUserMode();
4734  InitReg(MISCREG_ICC_AP0R3)
4735  .allPrivileges().exceptUserMode();
4736  InitReg(MISCREG_ICC_AP1R0)
4737  .allPrivileges().exceptUserMode();
4738  InitReg(MISCREG_ICC_AP1R0_NS)
4739  .allPrivileges().exceptUserMode();
4740  InitReg(MISCREG_ICC_AP1R0_S)
4741  .allPrivileges().exceptUserMode();
4742  InitReg(MISCREG_ICC_AP1R1)
4743  .allPrivileges().exceptUserMode();
4744  InitReg(MISCREG_ICC_AP1R1_NS)
4745  .allPrivileges().exceptUserMode();
4746  InitReg(MISCREG_ICC_AP1R1_S)
4747  .allPrivileges().exceptUserMode();
4748  InitReg(MISCREG_ICC_AP1R2)
4749  .allPrivileges().exceptUserMode();
4750  InitReg(MISCREG_ICC_AP1R2_NS)
4751  .allPrivileges().exceptUserMode();
4752  InitReg(MISCREG_ICC_AP1R2_S)
4753  .allPrivileges().exceptUserMode();
4754  InitReg(MISCREG_ICC_AP1R3)
4755  .allPrivileges().exceptUserMode();
4756  InitReg(MISCREG_ICC_AP1R3_NS)
4757  .allPrivileges().exceptUserMode();
4758  InitReg(MISCREG_ICC_AP1R3_S)
4759  .allPrivileges().exceptUserMode();
4760  InitReg(MISCREG_ICC_ASGI1R)
4761  .allPrivileges().exceptUserMode().reads(0);
4762  InitReg(MISCREG_ICC_BPR0)
4763  .allPrivileges().exceptUserMode();
4764  InitReg(MISCREG_ICC_BPR1)
4765  .allPrivileges().exceptUserMode();
4766  InitReg(MISCREG_ICC_BPR1_NS)
4767  .allPrivileges().exceptUserMode();
4768  InitReg(MISCREG_ICC_BPR1_S)
4769  .allPrivileges().exceptUserMode();
4770  InitReg(MISCREG_ICC_CTLR)
4771  .allPrivileges().exceptUserMode();
4772  InitReg(MISCREG_ICC_CTLR_NS)
4773  .allPrivileges().exceptUserMode();
4774  InitReg(MISCREG_ICC_CTLR_S)
4775  .allPrivileges().exceptUserMode();
4776  InitReg(MISCREG_ICC_DIR)
4777  .allPrivileges().exceptUserMode().reads(0);
4778  InitReg(MISCREG_ICC_EOIR0)
4779  .allPrivileges().exceptUserMode().reads(0);
4780  InitReg(MISCREG_ICC_EOIR1)
4781  .allPrivileges().exceptUserMode().reads(0);
4782  InitReg(MISCREG_ICC_HPPIR0)
4783  .allPrivileges().exceptUserMode().writes(0);
4784  InitReg(MISCREG_ICC_HPPIR1)
4785  .allPrivileges().exceptUserMode().writes(0);
4786  InitReg(MISCREG_ICC_HSRE)
4787  .hyp().mon();
4788  InitReg(MISCREG_ICC_IAR0)
4789  .allPrivileges().exceptUserMode().writes(0);
4790  InitReg(MISCREG_ICC_IAR1)
4791  .allPrivileges().exceptUserMode().writes(0);
4792  InitReg(MISCREG_ICC_IGRPEN0)
4793  .allPrivileges().exceptUserMode();
4794  InitReg(MISCREG_ICC_IGRPEN1)
4795  .allPrivileges().exceptUserMode();
4796  InitReg(MISCREG_ICC_IGRPEN1_NS)
4797  .allPrivileges().exceptUserMode();
4798  InitReg(MISCREG_ICC_IGRPEN1_S)
4799  .allPrivileges().exceptUserMode();
4800  InitReg(MISCREG_ICC_MCTLR)
4801  .mon();
4802  InitReg(MISCREG_ICC_MGRPEN1)
4803  .mon();
4804  InitReg(MISCREG_ICC_MSRE)
4805  .mon();
4806  InitReg(MISCREG_ICC_PMR)
4807  .allPrivileges().exceptUserMode();
4808  InitReg(MISCREG_ICC_RPR)
4809  .allPrivileges().exceptUserMode().writes(0);
4810  InitReg(MISCREG_ICC_SGI0R)
4811  .allPrivileges().exceptUserMode().reads(0);
4812  InitReg(MISCREG_ICC_SGI1R)
4813  .allPrivileges().exceptUserMode().reads(0);
4814  InitReg(MISCREG_ICC_SRE)
4815  .allPrivileges().exceptUserMode();
4816  InitReg(MISCREG_ICC_SRE_NS)
4817  .allPrivileges().exceptUserMode();
4818  InitReg(MISCREG_ICC_SRE_S)
4819  .allPrivileges().exceptUserMode();
4820 
4821  InitReg(MISCREG_ICH_AP0R0)
4822  .hyp().mon();
4823  InitReg(MISCREG_ICH_AP0R1)
4824  .hyp().mon();
4825  InitReg(MISCREG_ICH_AP0R2)
4826  .hyp().mon();
4827  InitReg(MISCREG_ICH_AP0R3)
4828  .hyp().mon();
4829  InitReg(MISCREG_ICH_AP1R0)
4830  .hyp().mon();
4831  InitReg(MISCREG_ICH_AP1R1)
4832  .hyp().mon();
4833  InitReg(MISCREG_ICH_AP1R2)
4834  .hyp().mon();
4835  InitReg(MISCREG_ICH_AP1R3)
4836  .hyp().mon();
4837  InitReg(MISCREG_ICH_HCR)
4838  .hyp().mon();
4839  InitReg(MISCREG_ICH_VTR)
4840  .hyp().mon().writes(0);
4841  InitReg(MISCREG_ICH_MISR)
4842  .hyp().mon().writes(0);
4843  InitReg(MISCREG_ICH_EISR)
4844  .hyp().mon().writes(0);
4845  InitReg(MISCREG_ICH_ELRSR)
4846  .hyp().mon().writes(0);
4847  InitReg(MISCREG_ICH_VMCR)
4848  .hyp().mon();
4849  InitReg(MISCREG_ICH_LR0)
4850  .hyp().mon();
4851  InitReg(MISCREG_ICH_LR1)
4852  .hyp().mon();
4853  InitReg(MISCREG_ICH_LR2)
4854  .hyp().mon();
4855  InitReg(MISCREG_ICH_LR3)
4856  .hyp().mon();
4857  InitReg(MISCREG_ICH_LR4)
4858  .hyp().mon();
4859  InitReg(MISCREG_ICH_LR5)
4860  .hyp().mon();
4861  InitReg(MISCREG_ICH_LR6)
4862  .hyp().mon();
4863  InitReg(MISCREG_ICH_LR7)
4864  .hyp().mon();
4865  InitReg(MISCREG_ICH_LR8)
4866  .hyp().mon();
4867  InitReg(MISCREG_ICH_LR9)
4868  .hyp().mon();
4869  InitReg(MISCREG_ICH_LR10)
4870  .hyp().mon();
4871  InitReg(MISCREG_ICH_LR11)
4872  .hyp().mon();
4873  InitReg(MISCREG_ICH_LR12)
4874  .hyp().mon();
4875  InitReg(MISCREG_ICH_LR13)
4876  .hyp().mon();
4877  InitReg(MISCREG_ICH_LR14)
4878  .hyp().mon();
4879  InitReg(MISCREG_ICH_LR15)
4880  .hyp().mon();
4881  InitReg(MISCREG_ICH_LRC0)
4882  .hyp().mon();
4883  InitReg(MISCREG_ICH_LRC1)
4884  .hyp().mon();
4885  InitReg(MISCREG_ICH_LRC2)
4886  .hyp().mon();
4887  InitReg(MISCREG_ICH_LRC3)
4888  .hyp().mon();
4889  InitReg(MISCREG_ICH_LRC4)
4890  .hyp().mon();
4891  InitReg(MISCREG_ICH_LRC5)
4892  .hyp().mon();
4893  InitReg(MISCREG_ICH_LRC6)
4894  .hyp().mon();
4895  InitReg(MISCREG_ICH_LRC7)
4896  .hyp().mon();
4897  InitReg(MISCREG_ICH_LRC8)
4898  .hyp().mon();
4899  InitReg(MISCREG_ICH_LRC9)
4900  .hyp().mon();
4901  InitReg(MISCREG_ICH_LRC10)
4902  .hyp().mon();
4903  InitReg(MISCREG_ICH_LRC11)
4904  .hyp().mon();
4905  InitReg(MISCREG_ICH_LRC12)
4906  .hyp().mon();
4907  InitReg(MISCREG_ICH_LRC13)
4908  .hyp().mon();
4909  InitReg(MISCREG_ICH_LRC14)
4910  .hyp().mon();
4911  InitReg(MISCREG_ICH_LRC15)
4912  .hyp().mon();
4913 
4914  // SVE
4915  InitReg(MISCREG_ID_AA64ZFR0_EL1)
4916  .faultRead(EL1, HCR_TRAP(tid3))
4917  .allPrivileges().exceptUserMode().writes(0);
4918  InitReg(MISCREG_ZCR_EL3)
4919  .fault(EL3, faultZcrEL3)
4920  .mon();
4921  InitReg(MISCREG_ZCR_EL2)
4922  .fault(EL2, faultZcrEL2)
4923  .fault(EL3, faultZcrEL3)
4924  .hyp().mon();
4925  InitReg(MISCREG_ZCR_EL12)
4926  .fault(EL2, defaultFaultE2H_EL2)
4927  .fault(EL3, defaultFaultE2H_EL3)
4928  .mapsTo(MISCREG_ZCR_EL1);
4929  InitReg(MISCREG_ZCR_EL1)
4930  .fault(EL1, faultZcrEL1)
4931  .fault(EL2, faultZcrEL2)
4932  .fault(EL3, faultZcrEL3)
4933  .allPrivileges().exceptUserMode();
4934 
4935  // Dummy registers
4936  InitReg(MISCREG_NOP)
4937  .allPrivileges();
4938  InitReg(MISCREG_RAZ)
4939  .allPrivileges().exceptUserMode().writes(0);
4940  InitReg(MISCREG_UNKNOWN);
4941  InitReg(MISCREG_IMPDEF_UNIMPL)
4942  .fault(EL1, faultImpdefUnimplEL1)
4943  .fault(EL2, faultUnimplemented)
4944  .fault(EL3, faultUnimplemented)
4945  .warnNotFail(impdefAsNop);
4946 
4947  // RAS extension (unimplemented)
4948  InitReg(MISCREG_ERRIDR_EL1)
4949  .warnNotFail()
4950  .fault(faultUnimplemented);
4951  InitReg(MISCREG_ERRSELR_EL1)
4952  .warnNotFail()
4953  .fault(faultUnimplemented);
4954  InitReg(MISCREG_ERXFR_EL1)
4955  .warnNotFail()
4956  .fault(faultUnimplemented);
4957  InitReg(MISCREG_ERXCTLR_EL1)
4958  .warnNotFail()
4959  .fault(faultUnimplemented);
4960  InitReg(MISCREG_ERXSTATUS_EL1)
4961  .warnNotFail()
4962  .fault(faultUnimplemented);
4963  InitReg(MISCREG_ERXADDR_EL1)
4964  .warnNotFail()
4965  .fault(faultUnimplemented);
4966  InitReg(MISCREG_ERXMISC0_EL1)
4967  .warnNotFail()
4968  .fault(faultUnimplemented);
4969  InitReg(MISCREG_ERXMISC1_EL1)
4970  .warnNotFail()
4971  .fault(faultUnimplemented);
4972  InitReg(MISCREG_DISR_EL1)
4973  .warnNotFail()
4974  .fault(faultUnimplemented);
4975  InitReg(MISCREG_VSESR_EL2)
4976  .warnNotFail()
4977  .fault(faultUnimplemented);
4978  InitReg(MISCREG_VDISR_EL2)
4979  .warnNotFail()
4980  .fault(faultUnimplemented);
4981 
4982  // Register mappings for some unimplemented registers:
4983  // ESR_EL1 -> DFSR
4984  // RMR_EL1 -> RMR
4985  // RMR_EL2 -> HRMR
4986  // DBGDTR_EL0 -> DBGDTR{R or T}Xint
4987  // DBGDTRRX_EL0 -> DBGDTRRXint
4988  // DBGDTRTX_EL0 -> DBGDTRRXint
4989  // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
4990 
4991  // Populate the idxToMiscRegNum map
4992  assert(idxToMiscRegNum.empty());
4993  for (const auto& [key, val] : miscRegNumToIdx) {
4994  idxToMiscRegNum.insert({val, key});
4995  }
4996 
4997  completed = true;
4998 }
4999 
5000 } // namespace ArmISA
5001 } // namespace gem5
HCR_TRAP
#define HCR_TRAP(bitfield)
Definition: misc.cc:1709
gem5::ArmISA::ArmStaticInst::undefined
Fault undefined(bool disabled=false) const
Definition: static_inst.hh:587
gem5::ArmISA::ISA::system
ArmSystem * system
Definition: isa.hh:73
gem5::ArmISA::ISA::impdefAsNop
bool impdefAsNop
If true, accesses to IMPLEMENTATION DEFINED registers are treated as NOP hence not causing UNDEFINED ...
Definition: isa.hh:105
gem5::ArmISA::ISA::InitReg
const MiscRegLUTEntryInitializer InitReg(uint32_t reg)
Definition: isa.hh:110
gem5::ArmISA::ISA::initializeMiscRegMetadata
void initializeMiscRegMetadata()
Definition: misc.cc:2070
gem5::ArmISA::ISA::release
const ArmRelease * release
This could be either a FS or a SE release.
Definition: isa.hh:99
gem5::ArmISA::ISA::highestELIs64
bool highestELIs64
Definition: isa.hh:91
gem5::ArmISA::MiscRegLUTEntryInitializer
Metadata table accessible via the value of the register.
Definition: misc.hh:1201
gem5::ArmISA::MiscRegLUTEntryInitializer::userNonSecureWrite
chain userNonSecureWrite(bool v=true) const
Definition: misc.hh:1290
gem5::ArmISA::MiscRegLUTEntryInitializer::userSecureWrite
chain userSecureWrite(bool v=true) const
Definition: misc.hh:1302
gem5::ArmISA::MiscRegLUTEntryInitializer::warnNotFail
chain warnNotFail(bool v=true) const
Definition: misc.hh:1254
gem5::ArmISA::MiscRegLUTEntryInitializer::mapsTo
chain mapsTo(uint32_t l, uint32_t u=0) const
Definition: misc.hh:1206
gem5::ArmISA::MiscRegLUTEntryInitializer::fault
chain fault(ExceptionLevel el, MiscRegLUTEntry::FaultCB cb) const
Definition: misc.hh:1557
gem5::ArmISA::MiscRegLUTEntryInitializer::userSecureRead
chain userSecureRead(bool v=true) const
Definition: misc.hh:1296
gem5::ArmISA::MiscRegLUTEntryInitializer::highest
chain highest(ArmSystem *const sys) const
Definition: misc.cc:2057
gem5::ArmISA::MiscRegLUTEntryInitializer::secure
chain secure(bool v=true) const
Definition: misc.hh:1500
gem5::ArmISA::MiscRegLUTEntryInitializer::mutex
chain mutex(bool v=true) const
Definition: misc.hh:1260
gem5::ArmISA::MiscRegLUTEntryInitializer::priv
chain priv(bool v=true) const
Definition: misc.hh:1355
gem5::ArmISA::MiscRegLUTEntryInitializer::monSecure
chain monSecure(bool v=true) const
Definition: misc.hh:1454
gem5::ArmISA::MiscRegLUTEntryInitializer::privSecure
chain privSecure(bool v=true) const
Definition: misc.hh:1348
gem5::ArmISA::MiscRegLUTEntryInitializer::nonSecure
chain nonSecure(bool v=true) const
Definition: misc.hh:1487
gem5::ArmISA::MiscRegLUTEntryInitializer::monNonSecureWrite
chain monNonSecureWrite(bool v=true) const
Definition: misc.hh:1439
gem5::ArmISA::MiscRegLUTEntryInitializer::monNonSecureRead
chain monNonSecureRead(bool v=true) const
Definition: misc.hh:1433
gem5::ArmISA::MiscRegLUTEntryInitializer::user
chain user(bool v=true) const
Definition: misc.hh:1308
gem5::ArmISA::MiscRegLUTEntryInitializer::unverifiable
chain unverifiable(bool v=true) const
Definition: misc.hh:1248
gem5::ArmISA::MiscRegLUTEntryInitializer::hypSecure
chain hypSecure(bool v=true) const
Definition: misc.hh:1407
gem5::ArmISA::MiscRegLUTEntryInitializer::banked
chain banked(bool v=true) const
Definition: misc.hh:1266
gem5::ArmISA::MiscRegLUTEntryInitializer::privRead
chain privRead(bool v=true) const
Definition: misc.hh:1362
gem5::ArmISA::MiscRegLUTEntryInitializer::hypRead
chain hypRead(bool v=true) const
Definition: misc.hh:1381
gem5::ArmISA::MiscRegLUTEntryInitializer::banked64
chain banked64(bool v=true) const
Definition: misc.hh:1272
gem5::ArmISA::MiscRegLUTEntryInitializer::res0
chain res0(uint64_t mask) const
Definition: misc.hh:1213
gem5::ArmISA::MiscRegLUTEntryInitializer::bankedChild
chain bankedChild(bool v=true) const
Definition: misc.hh:1278
gem5::ArmISA::MiscRegLUTEntryInitializer::hypWrite
chain hypWrite(bool v=true) const
Definition: misc.hh:1400
gem5::ArmISA::MiscRegLUTEntryInitializer::allPrivileges
chain allPrivileges(bool v=true) const
Definition: misc.hh:1468
gem5::ArmISA::MiscRegLUTEntryInitializer::monSecureRead
chain monSecureRead(bool v=true) const
Definition: misc.hh:1421
gem5::ArmISA::MiscRegLUTEntryInitializer::privSecureWrite
chain privSecureWrite(bool v=true) const
Definition: misc.hh:1342
gem5::ArmISA::MiscRegLUTEntryInitializer::res1
chain res1(uint64_t mask) const
Definition: misc.hh:1219
gem5::ArmISA::MiscRegLUTEntryInitializer::faultRead
chain faultRead(ExceptionLevel el, MiscRegLUTEntry::FaultCB cb) const
Definition: misc.hh:1543
gem5::ArmISA::MiscRegLUTEntryInitializer::monNonSecure
chain monNonSecure(bool v=true) const
Definition: misc.hh:1461
gem5::ArmISA::MiscRegLUTEntryInitializer::monSecureWrite
chain monSecureWrite(bool v=true) const
Definition: misc.hh:1427
gem5::ArmISA::MiscRegLUTEntryInitializer::mon
chain mon(bool v=true) const
Definition: misc.hh:1445
gem5::ArmISA::MiscRegLUTEntryInitializer::privNonSecureWrite
chain privNonSecureWrite(bool v=true) const
Definition: misc.hh:1323
gem5::ArmISA::MiscRegLUTEntryInitializer::faultWrite
chain faultWrite(ExceptionLevel el, MiscRegLUTEntry::FaultCB cb) const
Definition: misc.hh:1550
gem5::ArmISA::MiscRegLUTEntryInitializer::hyp
chain hyp(bool v=true) const
Definition: misc.hh:1414
gem5::ArmRelease::has
bool has(ArmExtension ext) const
Definition: system.hh:76
gem5::ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:184
gem5::ArmSystem::highestEL
ArmISA::ExceptionLevel highestEL() const
Returns the highest implemented exception level.
Definition: system.hh:188
gem5::ArmSystem::haveEL
static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el)
Return true if the system implements a specific exception level.
Definition: system.cc:131
gem5::MiscRegOp64
This class is implementing the Base class for a generic AArch64 instruction which is making use of sy...
Definition: misc64.hh:125
gem5::MiscRegOp64::miscRead
bool miscRead() const
Definition: misc64.hh:141
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:89
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr() const =0
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
std::vector
STL vector class.
Definition: stl.hh:37
thread_context.hh
full_system.hh
gic_v3_cpu_interface.hh
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
warn
#define warn(...)
Definition: logging.hh:246
gem5::ArmISA::ELIs32
bool ELIs32(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:275
gem5::ArmISA::MODE_SYSTEM
@ MODE_SYSTEM
Definition: types.hh:296
gem5::ArmISA::MODE_ABORT
@ MODE_ABORT
Definition: types.hh:293
gem5::ArmISA::MODE_UNDEFINED
@ MODE_UNDEFINED
Definition: types.hh:295
gem5::ArmISA::encodeAArch64SysReg
MiscRegNum64 encodeAArch64SysReg(MiscRegIndex misc_reg)
Definition: misc.cc:2001
gem5::ArmISA::unflattenResultMiscReg
int unflattenResultMiscReg[NUM_MISCREGS]
If the reg is a child reg of a banked set, then the parent is the last banked one in the list.
Definition: misc.cc:703
gem5::ArmISA::AArch32isUndefinedGenericTimer
bool AArch32isUndefinedGenericTimer(MiscRegIndex reg, ThreadContext *tc)
Definition: misc.cc:658
gem5::ArmISA::ttlb
Bitfield< 25 > ttlb
Definition: misc_types.hh:265
gem5::ArmISA::currEL
ExceptionLevel currEL(const ThreadContext *tc)
Returns the current Exception Level (EL) of the provided ThreadContext.
Definition: utility.cc:124
gem5::ArmISA::decodeAArch64SysReg
MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2)
Definition: misc.cc:1975
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::ArmISA::gic
Bitfield< 27, 24 > gic
Definition: misc_types.hh:175
gem5::ArmISA::decodeCP15Reg
MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
Definition: misc.cc:533
gem5::ArmISA::tid1
Bitfield< 16 > tid1
Definition: misc_types.hh:275
gem5::ArmISA::tid3
Bitfield< 18 > tid3
Definition: misc_types.hh:273
gem5::ArmISA::tacr
Bitfield< 21 > tacr
Definition: misc_types.hh:270
gem5::ArmISA::checkFaultAccessAArch64SysReg
Fault checkFaultAccessAArch64SysReg(MiscRegIndex reg, CPSR cpsr, ThreadContext *tc, const MiscRegOp64 &inst)
Definition: misc.cc:728
gem5::ArmISA::tdz
Bitfield< 28 > tdz
Definition: misc_types.hh:262
gem5::ArmISA::opc2
Bitfield< 7, 5 > opc2
Definition: types.hh:106
gem5::ArmISA::tsw
Bitfield< 22 > tsw
Definition: misc_types.hh:268
gem5::ArmISA::tid2
Bitfield< 17 > tid2
Definition: misc_types.hh:274
gem5::ArmISA::at
Bitfield< 35, 32 > at
Definition: misc_types.hh:155
gem5::ArmISA::isSecureBelowEL3
bool isSecureBelowEL3(ThreadContext *tc)
Definition: utility.cc:86
gem5::ArmISA::tpc
Bitfield< 23 > tpc
Definition: misc_types.hh:267
gem5::ArmISA::ns
Bitfield< 0 > ns
Definition: misc_types.hh:338
gem5::ArmISA::EL2Enabled
bool EL2Enabled(ThreadContext *tc)
Definition: utility.cc:260
gem5::ArmISA::preUnflattenMiscReg
void preUnflattenMiscReg()
Definition: misc.cc:706
gem5::ArmISA::trvm
Bitfield< 30 > trvm
Definition: misc_types.hh:260
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:64
gem5::ArmISA::MISCREG_PMXEVTYPER_EL0
@ MISCREG_PMXEVTYPER_EL0
Definition: misc.hh:726
gem5::ArmISA::MISCREG_ERXSTATUS_EL1
@ MISCREG_ERXSTATUS_EL1
Definition: misc.hh:1087
gem5::ArmISA::MISCREG_AMAIR_EL3
@ MISCREG_AMAIR_EL3
Definition: misc.hh:738
gem5::ArmISA::MISCREG_DBGWVR1_EL1
@ MISCREG_DBGWVR1_EL1
Definition: misc.hh:496
gem5::ArmISA::MISCREG_DBGDRAR
@ MISCREG_DBGDRAR
Definition: misc.hh:175
gem5::ArmISA::MISCREG_NSACR
@ MISCREG_NSACR
Definition: misc.hh:250
gem5::ArmISA::MISCREG_DL1DATA1
@ MISCREG_DL1DATA1
Definition: misc.hh:445
gem5::ArmISA::MISCREG_ID_AA64PFR0_EL1
@ MISCREG_ID_AA64PFR0_EL1
Definition: misc.hh:566
gem5::ArmISA::MISCREG_DBGWCR5
@ MISCREG_DBGWCR5
Definition: misc.hh:164
gem5::ArmISA::MISCREG_ICH_VMCR
@ MISCREG_ICH_VMCR
Definition: misc.hh:1024
gem5::ArmISA::MISCREG_CSSELR_NS
@ MISCREG_CSSELR_NS
Definition: misc.hh:236
gem5::ArmISA::MISCREG_HSTR_EL2
@ MISCREG_HSTR_EL2
Definition: misc.hh:594
gem5::ArmISA::MISCREG_DBGWVR13_EL1
@ MISCREG_DBGWVR13_EL1
Definition: misc.hh:508
gem5::ArmISA::MISCREG_PMUSERENR
@ MISCREG_PMUSERENR
Definition: misc.hh:368
gem5::ArmISA::MISCREG_DBGBCR15
@ MISCREG_DBGBCR15
Definition: misc.hh:142
gem5::ArmISA::MISCREG_DBGOSLSR
@ MISCREG_DBGOSLSR
Definition: misc.hh:193
gem5::ArmISA::MISCREG_DBGDTRRXext
@ MISCREG_DBGDTRRXext
Definition: misc.hh:107
gem5::ArmISA::MISCREG_ID_MMFR2_EL1
@ MISCREG_ID_MMFR2_EL1
Definition: misc.hh:553
gem5::ArmISA::MISCREG_TTBR1_EL12
@ MISCREG_TTBR1_EL12
Definition: misc.hh:605
gem5::ArmISA::MISCREG_DCCISW
@ MISCREG_DCCISW
Definition: misc.hh:323
gem5::ArmISA::MISCREG_ERRIDR_EL1
@ MISCREG_ERRIDR_EL1
Definition: misc.hh:1083
gem5::ArmISA::MISCREG_DACR_S
@ MISCREG_DACR_S
Definition: misc.hh:272
gem5::ArmISA::MISCREG_CNTV_CTL_EL0
@ MISCREG_CNTV_CTL_EL0
Definition: misc.hh:764
gem5::ArmISA::MISCREG_ICH_LR7
@ MISCREG_ICH_LR7
Definition: misc.hh:1032
gem5::ArmISA::MISCREG_DBGWCR8
@ MISCREG_DBGWCR8
Definition: misc.hh:167
gem5::ArmISA::MISCREG_HCR
@ MISCREG_HCR
Definition: misc.hh:253
gem5::ArmISA::MISCREG_ICC_BPR1_EL1_NS
@ MISCREG_ICC_BPR1_EL1_NS
Definition: misc.hh:872
gem5::ArmISA::MISCREG_NMRR_NS
@ MISCREG_NMRR_NS
Definition: misc.hh:381
gem5::ArmISA::MISCREG_CPSR_MODE
@ MISCREG_CPSR_MODE
Definition: misc.hh:82
gem5::ArmISA::MISCREG_PRRR_MAIR0
@ MISCREG_PRRR_MAIR0
Definition: misc.hh:88
gem5::ArmISA::MISCREG_TLBI_ALLE3
@ MISCREG_TLBI_ALLE3
Definition: misc.hh:712
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_NS
@ MISCREG_ICC_IGRPEN1_EL1_NS
Definition: misc.hh:882
gem5::ArmISA::MISCREG_TLBI_ALLE1IS
@ MISCREG_TLBI_ALLE1IS
Definition: misc.hh:699
gem5::ArmISA::MISCREG_ICH_AP0R2_EL2
@ MISCREG_ICH_AP0R2_EL2
Definition: misc.hh:892
gem5::ArmISA::MISCREG_VSTCR_EL2
@ MISCREG_VSTCR_EL2
Definition: misc.hh:613
gem5::ArmISA::MISCREG_DBGWVR14
@ MISCREG_DBGWVR14
Definition: misc.hh:157
gem5::ArmISA::MISCREG_HDFAR
@ MISCREG_HDFAR
Definition: misc.hh:294
gem5::ArmISA::MISCREG_MPIDR_EL1
@ MISCREG_MPIDR_EL1
Definition: misc.hh:545
gem5::ArmISA::MISCREG_ICC_IGRPEN1
@ MISCREG_ICC_IGRPEN1
Definition: misc.hh:997
gem5::ArmISA::MISCREG_DFSR_S
@ MISCREG_DFSR_S
Definition: misc.hh:275
gem5::ArmISA::MISCREG_IL1DATA1
@ MISCREG_IL1DATA1
Definition: misc.hh:441
gem5::ArmISA::MISCREG_DBGWVR10_EL1
@ MISCREG_DBGWVR10_EL1
Definition: misc.hh:505
gem5::ArmISA::MISCREG_DL1DATA0
@ MISCREG_DL1DATA0
Definition: misc.hh:444
gem5::ArmISA::MISCREG_CPUECTLR_EL1
@ MISCREG_CPUECTLR_EL1
Definition: misc.hh:818
gem5::ArmISA::MISCREG_ATS1HR
@ MISCREG_ATS1HR
Definition: misc.hh:324
gem5::ArmISA::MISCREG_ERXCTLR_EL1
@ MISCREG_ERXCTLR_EL1
Definition: misc.hh:1086
gem5::ArmISA::MISCREG_SCTLR_EL2
@ MISCREG_SCTLR_EL2
Definition: misc.hh:589
gem5::ArmISA::MISCREG_PMSELR_EL0
@ MISCREG_PMSELR_EL0
Definition: misc.hh:722
gem5::ArmISA::MISCREG_ID_DFR0_EL1
@ MISCREG_ID_DFR0_EL1
Definition: misc.hh:549
gem5::ArmISA::MISCREG_CNTV_CVAL_EL02
@ MISCREG_CNTV_CVAL_EL02
Definition: misc.hh:771
gem5::ArmISA::MISCREG_TLBI_IPAS2E1IS_Xt
@ MISCREG_TLBI_IPAS2E1IS_Xt
Definition: misc.hh:695
gem5::ArmISA::MISCREG_CP15ISB
@ MISCREG_CP15ISB
Definition: misc.hh:304
gem5::ArmISA::MISCREG_CNTP_CTL_EL0
@ MISCREG_CNTP_CTL_EL0
Definition: misc.hh:761
gem5::ArmISA::MISCREG_DFAR_NS
@ MISCREG_DFAR_NS
Definition: misc.hh:289
gem5::ArmISA::MISCREG_DBGBXVR8
@ MISCREG_DBGBXVR8
Definition: misc.hh:184
gem5::ArmISA::MISCREG_TLBIMVALIS
@ MISCREG_TLBIMVALIS
Definition: misc.hh:330
gem5::ArmISA::MISCREG_PMOVSSET
@ MISCREG_PMOVSSET
Definition: misc.hh:371
gem5::ArmISA::MISCREG_FPEXC
@ MISCREG_FPEXC
Definition: misc.hh:79
gem5::ArmISA::MISCREG_DBGWCR1
@ MISCREG_DBGWCR1
Definition: misc.hh:160
gem5::ArmISA::MISCREG_NMRR_MAIR1_S
@ MISCREG_NMRR_MAIR1_S
Definition: misc.hh:93
gem5::ArmISA::MISCREG_ICH_LR7_EL2
@ MISCREG_ICH_LR7_EL2
Definition: misc.hh:911
gem5::ArmISA::MISCREG_CNTP_CTL_EL02
@ MISCREG_CNTP_CTL_EL02
Definition: misc.hh:767
gem5::ArmISA::MISCREG_ICC_IAR1_EL1
@ MISCREG_ICC_IAR1_EL1
Definition: misc.hh:868
gem5::ArmISA::MISCREG_SPSEL
@ MISCREG_SPSEL
Definition: misc.hh:622
gem5::ArmISA::MISCREG_TCR_EL2
@ MISCREG_TCR_EL2
Definition: misc.hh:609
gem5::ArmISA::MISCREG_AT_S1E1W_Xt
@ MISCREG_AT_S1E1W_Xt
Definition: misc.hh:665
gem5::ArmISA::MISCREG_ID_ISAR0_EL1
@ MISCREG_ID_ISAR0_EL1
Definition: misc.hh:556
gem5::ArmISA::MISCREG_DBGWCR5_EL1
@ MISCREG_DBGWCR5_EL1
Definition: misc.hh:516
gem5::ArmISA::MISCREG_DBGWVR2
@ MISCREG_DBGWVR2
Definition: misc.hh:145
gem5::ArmISA::MISCREG_ICH_LR6_EL2
@ MISCREG_ICH_LR6_EL2
Definition: misc.hh:910
gem5::ArmISA::MISCREG_ICH_AP1R1
@ MISCREG_ICH_AP1R1
Definition: misc.hh:1016
gem5::ArmISA::MISCREG_DBGDSCRint
@ MISCREG_DBGDSCRint
Definition: misc.hh:101
gem5::ArmISA::MISCREG_MVFR1
@ MISCREG_MVFR1
Definition: misc.hh:77
gem5::ArmISA::MISCREG_IL1DATA0_EL1
@ MISCREG_IL1DATA0_EL1
Definition: misc.hh:807
gem5::ArmISA::MISCREG_MIDR_EL1
@ MISCREG_MIDR_EL1
Definition: misc.hh:544
gem5::ArmISA::MISCREG_SDER
@ MISCREG_SDER
Definition: misc.hh:249
gem5::ArmISA::MISCREG_DBGWCR12_EL1
@ MISCREG_DBGWCR12_EL1
Definition: misc.hh:523
gem5::ArmISA::MISCREG_OSDLR_EL1
@ MISCREG_OSDLR_EL1
Definition: misc.hh:535
gem5::ArmISA::MISCREG_DL1DATA3
@ MISCREG_DL1DATA3
Definition: misc.hh:447
gem5::ArmISA::MISCREG_HTPIDR
@ MISCREG_HTPIDR
Definition: misc.hh:416
gem5::ArmISA::MISCREG_DBGBXVR15
@ MISCREG_DBGBXVR15
Definition: misc.hh:191
gem5::ArmISA::MISCREG_TLBIMVAALIS
@ MISCREG_TLBIMVAALIS
Definition: misc.hh:331
gem5::ArmISA::MISCREG_ICC_MGRPEN1
@ MISCREG_ICC_MGRPEN1
Definition: misc.hh:1001
gem5::ArmISA::MISCREG_ZCR_EL2
@ MISCREG_ZCR_EL2
Definition: misc.hh:1061
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL3
@ MISCREG_ICC_IGRPEN1_EL3
Definition: misc.hh:887
gem5::ArmISA::MISCREG_SPSR_HYP
@ MISCREG_SPSR_HYP
Definition: misc.hh:72
gem5::ArmISA::MISCREG_ID_AA64ZFR0_EL1
@ MISCREG_ID_AA64ZFR0_EL1
Definition: misc.hh:1059
gem5::ArmISA::MISCREG_DBGDEVID0
@ MISCREG_DBGDEVID0
Definition: misc.hh:202
gem5::ArmISA::MISCREG_CNTFRQ
@ MISCREG_CNTFRQ
Definition: misc.hh:418
gem5::ArmISA::MISCREG_DBGDSAR
@ MISCREG_DBGDSAR
Definition: misc.hh:196
gem5::ArmISA::MISCREG_AFSR1_EL12
@ MISCREG_AFSR1_EL12
Definition: misc.hh:643
gem5::ArmISA::MISCREG_CPUMERRSR
@ MISCREG_CPUMERRSR
Definition: misc.hh:454
gem5::ArmISA::MISCREG_CPSR_Q
@ MISCREG_CPSR_Q
Definition: misc.hh:83
gem5::ArmISA::MISCREG_DBGBVR5_EL1
@ MISCREG_DBGBVR5_EL1
Definition: misc.hh:468
gem5::ArmISA::MISCREG_MAIR_EL1
@ MISCREG_MAIR_EL1
Definition: misc.hh:731
gem5::ArmISA::MISCREG_TLBI_IPAS2E1_Xt
@ MISCREG_TLBI_IPAS2E1_Xt
Definition: misc.hh:702
gem5::ArmISA::MISCREG_DBGBCR2_EL1
@ MISCREG_DBGBCR2_EL1
Definition: misc.hh:481
gem5::ArmISA::MISCREG_ID_ISAR2_EL1
@ MISCREG_ID_ISAR2_EL1
Definition: misc.hh:558
gem5::ArmISA::MISCREG_TLBIMVAAL
@ MISCREG_TLBIMVAAL
Definition: misc.hh:343
gem5::ArmISA::MISCREG_DBGBVR1_EL1
@ MISCREG_DBGBVR1_EL1
Definition: misc.hh:464
gem5::ArmISA::MISCREG_PAR_NS
@ MISCREG_PAR_NS
Definition: misc.hh:300
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_S
@ MISCREG_ICC_IGRPEN1_EL1_S
Definition: misc.hh:883
gem5::ArmISA::MISCREG_HAMAIR1
@ MISCREG_HAMAIR1
Definition: misc.hh:395
gem5::ArmISA::MISCREG_PMXEVCNTR_EL0
@ MISCREG_PMXEVCNTR_EL0
Definition: misc.hh:728
gem5::ArmISA::MISCREG_ICC_IGRPEN1_NS
@ MISCREG_ICC_IGRPEN1_NS
Definition: misc.hh:998
gem5::ArmISA::MISCREG_ICC_PMR_EL1
@ MISCREG_ICC_PMR_EL1
Definition: misc.hh:842
gem5::ArmISA::MISCREG_CONTEXTIDR_EL1
@ MISCREG_CONTEXTIDR_EL1
Definition: misc.hh:750
gem5::ArmISA::MISCREG_CNTV_TVAL
@ MISCREG_CNTV_TVAL
Definition: misc.hh:432
gem5::ArmISA::MISCREG_VBAR_EL3
@ MISCREG_VBAR_EL3
Definition: misc.hh:747
gem5::ArmISA::MISCREG_AIFSR_NS
@ MISCREG_AIFSR_NS
Definition: misc.hh:283
gem5::ArmISA::MISCREG_DBGWCR10
@ MISCREG_DBGWCR10
Definition: misc.hh:169
gem5::ArmISA::MISCREG_DBGBXVR9
@ MISCREG_DBGBXVR9
Definition: misc.hh:185
gem5::ArmISA::MISCREG_ICC_CTLR_NS
@ MISCREG_ICC_CTLR_NS
Definition: misc.hh:986
gem5::ArmISA::MISCREG_CNTPS_TVAL_EL1
@ MISCREG_CNTPS_TVAL_EL1
Definition: misc.hh:777
gem5::ArmISA::MISCREG_ICC_AP1R3
@ MISCREG_ICC_AP1R3
Definition: misc.hh:977
gem5::ArmISA::MISCREG_ICC_MCTLR
@ MISCREG_ICC_MCTLR
Definition: misc.hh:1000
gem5::ArmISA::MISCREG_HCPTR
@ MISCREG_HCPTR
Definition: misc.hh:256
gem5::ArmISA::MISCREG_SPSR_EL2
@ MISCREG_SPSR_EL2
Definition: misc.hh:630
gem5::ArmISA::MISCREG_ICH_LR8
@ MISCREG_ICH_LR8
Definition: misc.hh:1033
gem5::ArmISA::MISCREG_ICC_AP1R0_EL1
@ MISCREG_ICC_AP1R0_EL1
Definition: misc.hh:851
gem5::ArmISA::MISCREG_ICC_BPR0_EL1
@ MISCREG_ICC_BPR0_EL1
Definition: misc.hh:846
gem5::ArmISA::MISCREG_DBGWFAR
@ MISCREG_DBGWFAR
Definition: misc.hh:105
gem5::ArmISA::MISCREG_IFAR
@ MISCREG_IFAR
Definition: misc.hh:291
gem5::ArmISA::MISCREG_TLBI_ALLE1
@ MISCREG_TLBI_ALLE1
Definition: misc.hh:706
gem5::ArmISA::MISCREG_FCSEIDR
@ MISCREG_FCSEIDR
Definition: misc.hh:403
gem5::ArmISA::MISCREG_DBGWVR7
@ MISCREG_DBGWVR7
Definition: misc.hh:150
gem5::ArmISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: misc.hh:1100
gem5::ArmISA::MISCREG_ID_MMFR1
@ MISCREG_ID_MMFR1
Definition: misc.hh:221
gem5::ArmISA::MISCREG_AT_S1E2W_Xt
@ MISCREG_AT_S1E2W_Xt
Definition: misc.hh:676
gem5::ArmISA::MISCREG_PMEVTYPER1_EL0
@ MISCREG_PMEVTYPER1_EL0
Definition: misc.hh:802
gem5::ArmISA::MISCREG_LOCKFLAG
@ MISCREG_LOCKFLAG
Definition: misc.hh:87
gem5::ArmISA::MISCREG_ICH_LR15_EL2
@ MISCREG_ICH_LR15_EL2
Definition: misc.hh:919
gem5::ArmISA::MISCREG_FPSID
@ MISCREG_FPSID
Definition: misc.hh:75
gem5::ArmISA::MISCREG_DBGBXVR12
@ MISCREG_DBGBXVR12
Definition: misc.hh:188
gem5::ArmISA::MISCREG_ICH_MISR
@ MISCREG_ICH_MISR
Definition: misc.hh:1021
gem5::ArmISA::MISCREG_DBGWCR6_EL1
@ MISCREG_DBGWCR6_EL1
Definition: misc.hh:517
gem5::ArmISA::MISCREG_ID_AFR0_EL1
@ MISCREG_ID_AFR0_EL1
Definition: misc.hh:550
gem5::ArmISA::MISCREG_DBGBVR2
@ MISCREG_DBGBVR2
Definition: misc.hh:113
gem5::ArmISA::MISCREG_MAIR_EL12
@ MISCREG_MAIR_EL12
Definition: misc.hh:732
gem5::ArmISA::MISCREG_DBGBVR7_EL1
@ MISCREG_DBGBVR7_EL1
Definition: misc.hh:470
gem5::ArmISA::MISCREG_ICH_LRC0
@ MISCREG_ICH_LRC0
Definition: misc.hh:1041
gem5::ArmISA::MISCREG_SCTLR
@ MISCREG_SCTLR
Definition: misc.hh:240
gem5::ArmISA::MISCREG_PAR_EL1
@ MISCREG_PAR_EL1
Definition: misc.hh:660
gem5::ArmISA::MISCREG_TTBCR
@ MISCREG_TTBCR
Definition: misc.hh:265
gem5::ArmISA::MISCREG_DBGWVR3_EL1
@ MISCREG_DBGWVR3_EL1
Definition: misc.hh:498
gem5::ArmISA::MISCREG_ICH_LR5
@ MISCREG_ICH_LR5
Definition: misc.hh:1030
gem5::ArmISA::MISCREG_AT_S12E1W_Xt
@ MISCREG_AT_S12E1W_Xt
Definition: misc.hh:678
gem5::ArmISA::MISCREG_SCTLR_RST
@ MISCREG_SCTLR_RST
Definition: misc.hh:95
gem5::ArmISA::MISCREG_TLBIIPAS2
@ MISCREG_TLBIIPAS2
Definition: misc.hh:350
gem5::ArmISA::MISCREG_ATS12NSOUW
@ MISCREG_ATS12NSOUW
Definition: misc.hh:316
gem5::ArmISA::MISCREG_MAIR_EL2
@ MISCREG_MAIR_EL2
Definition: misc.hh:735
gem5::ArmISA::MISCREG_CNTV_CVAL
@ MISCREG_CNTV_CVAL
Definition: misc.hh:431
gem5::ArmISA::MISCREG_APDBKeyLo_EL1
@ MISCREG_APDBKeyLo_EL1
Definition: misc.hh:833
gem5::ArmISA::MISCREG_MDRAR_EL1
@ MISCREG_MDRAR_EL1
Definition: misc.hh:532
gem5::ArmISA::MISCREG_CSSELR
@ MISCREG_CSSELR
Definition: misc.hh:235
gem5::ArmISA::MISCREG_CPACR
@ MISCREG_CPACR
Definition: misc.hh:246
gem5::ArmISA::MISCREG_TLBI_VAE2_Xt
@ MISCREG_TLBI_VAE2_Xt
Definition: misc.hh:705
gem5::ArmISA::MISCREG_HAMAIR0
@ MISCREG_HAMAIR0
Definition: misc.hh:394
gem5::ArmISA::MISCREG_TLBIIPAS2L
@ MISCREG_TLBIIPAS2L
Definition: misc.hh:351
gem5::ArmISA::MISCREG_ICC_BPR1_S
@ MISCREG_ICC_BPR1_S
Definition: misc.hh:984
gem5::ArmISA::MISCREG_DBGBVR8
@ MISCREG_DBGBVR8
Definition: misc.hh:119
gem5::ArmISA::MISCREG_ADFSR_S
@ MISCREG_ADFSR_S
Definition: misc.hh:281
gem5::ArmISA::MISCREG_ICH_LRC11
@ MISCREG_ICH_LRC11
Definition: misc.hh:1052
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: misc.hh:598
gem5::ArmISA::MISCREG_TTBR0_S
@ MISCREG_TTBR0_S
Definition: misc.hh:261
gem5::ArmISA::MISCREG_TLBIALLHIS
@ MISCREG_TLBIALLHIS
Definition: misc.hh:346
gem5::ArmISA::MISCREG_TLBI_ASIDE1IS_Xt
@ MISCREG_TLBI_ASIDE1IS_Xt
Definition: misc.hh:685
gem5::ArmISA::MISCREG_IL1DATA1_EL1
@ MISCREG_IL1DATA1_EL1
Definition: misc.hh:808
gem5::ArmISA::MISCREG_CNTKCTL_EL12
@ MISCREG_CNTKCTL_EL12
Definition: misc.hh:774
gem5::ArmISA::MISCREG_APDAKeyHi_EL1
@ MISCREG_APDAKeyHi_EL1
Definition: misc.hh:830
gem5::ArmISA::MISCREG_TLBIIPAS2LIS
@ MISCREG_TLBIIPAS2LIS
Definition: misc.hh:345
gem5::ArmISA::MISCREG_TLBIASIDIS
@ MISCREG_TLBIASIDIS
Definition: misc.hh:328
gem5::ArmISA::MISCREG_ID_AA64DFR0_EL1
@ MISCREG_ID_AA64DFR0_EL1
Definition: misc.hh:568
gem5::ArmISA::MISCREG_ID_ISAR6
@ MISCREG_ID_ISAR6
Definition: misc.hh:231
gem5::ArmISA::MISCREG_DBGCLAIMCLR
@ MISCREG_DBGCLAIMCLR
Definition: misc.hh:198
gem5::ArmISA::MISCREG_TPIDRRO_EL0
@ MISCREG_TPIDRRO_EL0
Definition: misc.hh:754
gem5::ArmISA::MISCREG_DBGBVR3
@ MISCREG_DBGBVR3
Definition: misc.hh:114
gem5::ArmISA::MISCREG_DBGWVR5_EL1
@ MISCREG_DBGWVR5_EL1
Definition: misc.hh:500
gem5::ArmISA::MISCREG_DBGOSLAR
@ MISCREG_DBGOSLAR
Definition: misc.hh:192
gem5::ArmISA::MISCREG_PMEVTYPER3_EL0
@ MISCREG_PMEVTYPER3_EL0
Definition: misc.hh:804
gem5::ArmISA::MISCREG_ICC_SRE_EL1_NS
@ MISCREG_ICC_SRE_EL1_NS
Definition: misc.hh:878
gem5::ArmISA::MISCREG_DBGBCR10
@ MISCREG_DBGBCR10
Definition: misc.hh:137
gem5::ArmISA::MISCREG_SPSR_SVC
@ MISCREG_SPSR_SVC
Definition: misc.hh:69
gem5::ArmISA::MISCREG_REVIDR_EL1
@ MISCREG_REVIDR_EL1
Definition: misc.hh:546
gem5::ArmISA::MISCREG_DBGDSCRext
@ MISCREG_DBGDSCRext
Definition: misc.hh:108
gem5::ArmISA::MISCREG_TLBI_VAE2IS_Xt
@ MISCREG_TLBI_VAE2IS_Xt
Definition: misc.hh:698
gem5::ArmISA::MISCREG_TCR_EL3
@ MISCREG_TCR_EL3
Definition: misc.hh:615
gem5::ArmISA::MISCREG_FPSR
@ MISCREG_FPSR
Definition: misc.hh:627
gem5::ArmISA::MISCREG_UAO
@ MISCREG_UAO
Definition: misc.hh:1097
gem5::ArmISA::MISCREG_DBGDIDR
@ MISCREG_DBGDIDR
Definition: misc.hh:100
gem5::ArmISA::MISCREG_DBGBVR9_EL1
@ MISCREG_DBGBVR9_EL1
Definition: misc.hh:472
gem5::ArmISA::MISCREG_ICH_HCR_EL2
@ MISCREG_ICH_HCR_EL2
Definition: misc.hh:898
gem5::ArmISA::MISCREG_CPACR_EL12
@ MISCREG_CPACR_EL12
Definition: misc.hh:588
gem5::ArmISA::MISCREG_HDCR
@ MISCREG_HDCR
Definition: misc.hh:255
gem5::ArmISA::MISCREG_AIFSR_S
@ MISCREG_AIFSR_S
Definition: misc.hh:284
gem5::ArmISA::MISCREG_ESR_EL1
@ MISCREG_ESR_EL1
Definition: misc.hh:644
gem5::ArmISA::MISCREG_DISR_EL1
@ MISCREG_DISR_EL1
Definition: misc.hh:1091
gem5::ArmISA::MISCREG_ADFSR
@ MISCREG_ADFSR
Definition: misc.hh:279
gem5::ArmISA::MISCREG_ICC_AP1R3_EL1_NS
@ MISCREG_ICC_AP1R3_EL1_NS
Definition: misc.hh:861
gem5::ArmISA::MISCREG_PMCCNTR_EL0
@ MISCREG_PMCCNTR_EL0
Definition: misc.hh:725
gem5::ArmISA::MISCREG_CNTP_TVAL
@ MISCREG_CNTP_TVAL
Definition: misc.hh:427
gem5::ArmISA::MISCREG_MDCCSR_EL0
@ MISCREG_MDCCSR_EL0
Definition: misc.hh:527
gem5::ArmISA::MISCREG_DTLBIMVA
@ MISCREG_DTLBIMVA
Definition: misc.hh:336
gem5::ArmISA::MISCREG_SPSR_UND_AA64
@ MISCREG_SPSR_UND_AA64
Definition: misc.hh:635
gem5::ArmISA::MISCREG_DBGWVR13
@ MISCREG_DBGWVR13
Definition: misc.hh:156
gem5::ArmISA::MISCREG_AT_S12E0W_Xt
@ MISCREG_AT_S12E0W_Xt
Definition: misc.hh:680
gem5::ArmISA::MISCREG_DBGBXVR4
@ MISCREG_DBGBXVR4
Definition: misc.hh:180
gem5::ArmISA::MISCREG_TCR_EL1
@ MISCREG_TCR_EL1
Definition: misc.hh:606
gem5::ArmISA::MISCREG_NOP
@ MISCREG_NOP
Definition: misc.hh:1073
gem5::ArmISA::MISCREG_PMINTENSET
@ MISCREG_PMINTENSET
Definition: misc.hh:369
gem5::ArmISA::MISCREG_TTBCR_NS
@ MISCREG_TTBCR_NS
Definition: misc.hh:266
gem5::ArmISA::MISCREG_PMXEVTYPER
@ MISCREG_PMXEVTYPER
Definition: misc.hh:365
gem5::ArmISA::MISCREG_DBGBCR13_EL1
@ MISCREG_DBGBCR13_EL1
Definition: misc.hh:492
gem5::ArmISA::MISCREG_TPIDR_EL3
@ MISCREG_TPIDR_EL3
Definition: misc.hh:756
gem5::ArmISA::MISCREG_DBGBVR11
@ MISCREG_DBGBVR11
Definition: misc.hh:122
gem5::ArmISA::MISCREG_ICC_AP0R3
@ MISCREG_ICC_AP0R3
Definition: misc.hh:967
gem5::ArmISA::MISCREG_VMPIDR
@ MISCREG_VMPIDR
Definition: misc.hh:239
gem5::ArmISA::MISCREG_TLBI_VAAE1_Xt
@ MISCREG_TLBI_VAAE1_Xt
Definition: misc.hh:692
gem5::ArmISA::MISCREG_TPIDRURW_S
@ MISCREG_TPIDRURW_S
Definition: misc.hh:409
gem5::ArmISA::MISCREG_CCSIDR_EL1
@ MISCREG_CCSIDR_EL1
Definition: misc.hh:576
gem5::ArmISA::MISCREG_DBGBXVR5
@ MISCREG_DBGBXVR5
Definition: misc.hh:181
gem5::ArmISA::MISCREG_CNTVCT
@ MISCREG_CNTVCT
Definition: misc.hh:420
gem5::ArmISA::MISCREG_ESR_EL12
@ MISCREG_ESR_EL12
Definition: misc.hh:645
gem5::ArmISA::MISCREG_TLBIMVALH
@ MISCREG_TLBIMVALH
Definition: misc.hh:355
gem5::ArmISA::MISCREG_DL1DATA1_EL1
@ MISCREG_DL1DATA1_EL1
Definition: misc.hh:812
gem5::ArmISA::MISCREG_ICC_AP1R0_EL1_S
@ MISCREG_ICC_AP1R0_EL1_S
Definition: misc.hh:853
gem5::ArmISA::MISCREG_DBGWCR8_EL1
@ MISCREG_DBGWCR8_EL1
Definition: misc.hh:519
gem5::ArmISA::MISCREG_ICC_IGRPEN1_S
@ MISCREG_ICC_IGRPEN1_S
Definition: misc.hh:999
gem5::ArmISA::MISCREG_AFSR0_EL1
@ MISCREG_AFSR0_EL1
Definition: misc.hh:640
gem5::ArmISA::MISCREG_ICC_AP1R0_S
@ MISCREG_ICC_AP1R0_S
Definition: misc.hh:970
gem5::ArmISA::MISCREG_SPSR_UND
@ MISCREG_SPSR_UND
Definition: misc.hh:73
gem5::ArmISA::MISCREG_TCMTR
@ MISCREG_TCMTR
Definition: misc.hh:212
gem5::ArmISA::MISCREG_DBGWCR13_EL1
@ MISCREG_DBGWCR13_EL1
Definition: misc.hh:524
gem5::ArmISA::MISCREG_DBGOSDLR
@ MISCREG_DBGOSDLR
Definition: misc.hh:194
gem5::ArmISA::MISCREG_DBGBXVR3
@ MISCREG_DBGBXVR3
Definition: misc.hh:179
gem5::ArmISA::MISCREG_DBGWCR11_EL1
@ MISCREG_DBGWCR11_EL1
Definition: misc.hh:522
gem5::ArmISA::MISCREG_DBGWVR11_EL1
@ MISCREG_DBGWVR11_EL1
Definition: misc.hh:506
gem5::ArmISA::MISCREG_TLBI_ALLE2IS
@ MISCREG_TLBI_ALLE2IS
Definition: misc.hh:697
gem5::ArmISA::MISCREG_SPSR_IRQ
@ MISCREG_SPSR_IRQ
Definition: misc.hh:68
gem5::ArmISA::MISCREG_ID_ISAR5
@ MISCREG_ID_ISAR5
Definition: misc.hh:230
gem5::ArmISA::MISCREG_BPIALL
@ MISCREG_BPIALL
Definition: misc.hh:305
gem5::ArmISA::MISCREG_DBGBVR10_EL1
@ MISCREG_DBGBVR10_EL1
Definition: misc.hh:473
gem5::ArmISA::MISCREG_ID_ISAR3_EL1
@ MISCREG_ID_ISAR3_EL1
Definition: misc.hh:559
gem5::ArmISA::MISCREG_PMEVTYPER4_EL0
@ MISCREG_PMEVTYPER4_EL0
Definition: misc.hh:805
gem5::ArmISA::MISCREG_ATS1CUR
@ MISCREG_ATS1CUR
Definition: misc.hh:311
gem5::ArmISA::MISCREG_ICH_ELRSR_EL2
@ MISCREG_ICH_ELRSR_EL2
Definition: misc.hh:902
gem5::ArmISA::MISCREG_DC_CVAC_Xt
@ MISCREG_DC_CVAC_Xt
Definition: misc.hh:672
gem5::ArmISA::MISCREG_VPIDR_EL2
@ MISCREG_VPIDR_EL2
Definition: misc.hh:582
gem5::ArmISA::MISCREG_DBGWCR2
@ MISCREG_DBGWCR2
Definition: misc.hh:161
gem5::ArmISA::MISCREG_OSLAR_EL1
@ MISCREG_OSLAR_EL1
Definition: misc.hh:533
gem5::ArmISA::MISCREG_CNTPCT_EL0
@ MISCREG_CNTPCT_EL0
Definition: misc.hh:759
gem5::ArmISA::MISCREG_DBGWCR4_EL1
@ MISCREG_DBGWCR4_EL1
Definition: misc.hh:515
gem5::ArmISA::MISCREG_ERXADDR_EL1
@ MISCREG_ERXADDR_EL1
Definition: misc.hh:1088
gem5::ArmISA::MISCREG_AMAIR0_NS
@ MISCREG_AMAIR0_NS
Definition: misc.hh:387
gem5::ArmISA::MISCREG_DBGBCR14_EL1
@ MISCREG_DBGBCR14_EL1
Definition: misc.hh:493
gem5::ArmISA::MISCREG_ICH_AP1R3
@ MISCREG_ICH_AP1R3
Definition: misc.hh:1018
gem5::ArmISA::MISCREG_SPSR_ABT
@ MISCREG_SPSR_ABT
Definition: misc.hh:71
gem5::ArmISA::MISCREG_DBGWVR0_EL1
@ MISCREG_DBGWVR0_EL1
Definition: misc.hh:495
gem5::ArmISA::MISCREG_AFSR1_EL2
@ MISCREG_AFSR1_EL2
Definition: misc.hh:648
gem5::ArmISA::MISCREG_CNTV_CTL_EL02
@ MISCREG_CNTV_CTL_EL02
Definition: misc.hh:770
gem5::ArmISA::MISCREG_CP15DMB
@ MISCREG_CP15DMB
Definition: misc.hh:320
gem5::ArmISA::MISCREG_DBGBCR0_EL1
@ MISCREG_DBGBCR0_EL1
Definition: misc.hh:479
gem5::ArmISA::MISCREG_DBGWVR15
@ MISCREG_DBGWVR15
Definition: misc.hh:158
gem5::ArmISA::MISCREG_TLBIMVA
@ MISCREG_TLBIMVA
Definition: misc.hh:339
gem5::ArmISA::MISCREG_PMEVCNTR4_EL0
@ MISCREG_PMEVCNTR4_EL0
Definition: misc.hh:799
gem5::ArmISA::MISCREG_CONTEXTIDR_NS
@ MISCREG_CONTEXTIDR_NS
Definition: misc.hh:405
gem5::ArmISA::MISCREG_ICH_AP1R3_EL2
@ MISCREG_ICH_AP1R3_EL2
Definition: misc.hh:897
gem5::ArmISA::MISCREG_DBGBCR6_EL1
@ MISCREG_DBGBCR6_EL1
Definition: misc.hh:485
gem5::ArmISA::MISCREG_ID_ISAR4
@ MISCREG_ID_ISAR4
Definition: misc.hh:229
gem5::ArmISA::MISCREG_DBGBCR3_EL1
@ MISCREG_DBGBCR3_EL1
Definition: misc.hh:482
gem5::ArmISA::MISCREG_ICC_AP1R1_EL1_S
@ MISCREG_ICC_AP1R1_EL1_S
Definition: misc.hh:856
gem5::ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition: misc.hh:584
gem5::ArmISA::MISCREG_CNTP_TVAL_EL02
@ MISCREG_CNTP_TVAL_EL02
Definition: misc.hh:769
gem5::ArmISA::MISCREG_ICH_AP0R3
@ MISCREG_ICH_AP0R3
Definition: misc.hh:1014
gem5::ArmISA::MISCREG_DBGWVR4_EL1
@ MISCREG_DBGWVR4_EL1
Definition: misc.hh:499
gem5::ArmISA::MISCREG_TPIDRPRW_NS
@ MISCREG_TPIDRPRW_NS
Definition: misc.hh:414
gem5::ArmISA::MISCREG_AIDR_EL1
@ MISCREG_AIDR_EL1
Definition: misc.hh:578
gem5::ArmISA::MISCREG_DC_CIVAC_Xt
@ MISCREG_DC_CIVAC_Xt
Definition: misc.hh:674
gem5::ArmISA::MISCREG_DBGDEVID1
@ MISCREG_DBGDEVID1
Definition: misc.hh:201
gem5::ArmISA::MISCREG_PRRR
@ MISCREG_PRRR
Definition: misc.hh:374
gem5::ArmISA::MISCREG_ICC_IGRPEN0
@ MISCREG_ICC_IGRPEN0
Definition: misc.hh:996
gem5::ArmISA::MISCREG_ICH_LRC7
@ MISCREG_ICH_LRC7
Definition: misc.hh:1048
gem5::ArmISA::MISCREG_TEECR
@ MISCREG_TEECR
Definition: misc.hh:203
gem5::ArmISA::MISCREG_DC_CVAU_Xt
@ MISCREG_DC_CVAU_Xt
Definition: misc.hh:673
gem5::ArmISA::MISCREG_DBGBXVR7
@ MISCREG_DBGBXVR7
Definition: misc.hh:183
gem5::ArmISA::MISCREG_AMAIR1_S
@ MISCREG_AMAIR1_S
Definition: misc.hh:391
gem5::ArmISA::MISCREG_DBGWVR7_EL1
@ MISCREG_DBGWVR7_EL1
Definition: misc.hh:502
gem5::ArmISA::MISCREG_DBGBVR9
@ MISCREG_DBGBVR9
Definition: misc.hh:120
gem5::ArmISA::MISCREG_PMEVTYPER0_EL0
@ MISCREG_PMEVTYPER0_EL0
Definition: misc.hh:801
gem5::ArmISA::MISCREG_ICH_LRC8
@ MISCREG_ICH_LRC8
Definition: misc.hh:1049
gem5::ArmISA::MISCREG_CPTR_EL2
@ MISCREG_CPTR_EL2
Definition: misc.hh:593
gem5::ArmISA::MISCREG_ICH_LR9_EL2
@ MISCREG_ICH_LR9_EL2
Definition: misc.hh:913
gem5::ArmISA::MISCREG_DBGBCR8_EL1
@ MISCREG_DBGBCR8_EL1
Definition: misc.hh:487
gem5::ArmISA::MISCREG_CCSIDR
@ MISCREG_CCSIDR
Definition: misc.hh:232
gem5::ArmISA::MISCREG_FAR_EL1
@ MISCREG_FAR_EL1
Definition: misc.hh:654
gem5::ArmISA::MISCREG_ERXMISC0_EL1
@ MISCREG_ERXMISC0_EL1
Definition: misc.hh:1089
gem5::ArmISA::MISCREG_TPIDR_EL1
@ MISCREG_TPIDR_EL1
Definition: misc.hh:752
gem5::ArmISA::MISCREG_PMUSERENR_EL0
@ MISCREG_PMUSERENR_EL0
Definition: misc.hh:729
gem5::ArmISA::MISCREG_TLBI_VAAE1IS_Xt
@ MISCREG_TLBI_VAAE1IS_Xt
Definition: misc.hh:686
gem5::ArmISA::MISCREG_APIAKeyLo_EL1
@ MISCREG_APIAKeyLo_EL1
Definition: misc.hh:837
gem5::ArmISA::MISCREG_DBGWCR0
@ MISCREG_DBGWCR0
Definition: misc.hh:159
gem5::ArmISA::MISCREG_AT_S1E2R_Xt
@ MISCREG_AT_S1E2R_Xt
Definition: misc.hh:675
gem5::ArmISA::MISCREG_PMCR
@ MISCREG_PMCR
Definition: misc.hh:356
gem5::ArmISA::MISCREG_CNTHV_CTL_EL2
@ MISCREG_CNTHV_CTL_EL2
Definition: misc.hh:786
gem5::ArmISA::MISCREG_ICC_DIR
@ MISCREG_ICC_DIR
Definition: misc.hh:988
gem5::ArmISA::MISCREG_CNTP_TVAL_NS
@ MISCREG_CNTP_TVAL_NS
Definition: misc.hh:428
gem5::ArmISA::MISCREG_CNTV_CTL
@ MISCREG_CNTV_CTL
Definition: misc.hh:430
gem5::ArmISA::MISCREG_AFSR1_EL3
@ MISCREG_AFSR1_EL3
Definition: misc.hh:652
gem5::ArmISA::MISCREG_ADFSR_NS
@ MISCREG_ADFSR_NS
Definition: misc.hh:280
gem5::ArmISA::MISCREG_APIBKeyLo_EL1
@ MISCREG_APIBKeyLo_EL1
Definition: misc.hh:839
gem5::ArmISA::MISCREG_DFAR
@ MISCREG_DFAR
Definition: misc.hh:288
gem5::ArmISA::MISCREG_ID_AA64DFR1_EL1
@ MISCREG_ID_AA64DFR1_EL1
Definition: misc.hh:569
gem5::ArmISA::MISCREG_DC_CSW_Xt
@ MISCREG_DC_CSW_Xt
Definition: misc.hh:668
gem5::ArmISA::MISCREG_JMCR
@ MISCREG_JMCR
Definition: misc.hh:207
gem5::ArmISA::MISCREG_RMR_EL3
@ MISCREG_RMR_EL3
Definition: misc.hh:749
gem5::ArmISA::MISCREG_ID_AA64ISAR1_EL1
@ MISCREG_ID_AA64ISAR1_EL1
Definition: misc.hh:573
gem5::ArmISA::MISCREG_TLBIMVAL
@ MISCREG_TLBIMVAL
Definition: misc.hh:342
gem5::ArmISA::MISCREG_ELR_EL12
@ MISCREG_ELR_EL12
Definition: misc.hh:620
gem5::ArmISA::MISCREG_DL1DATA2_EL1
@ MISCREG_DL1DATA2_EL1
Definition: misc.hh:813
gem5::ArmISA::MISCREG_DBGBVR0
@ MISCREG_DBGBVR0
Definition: misc.hh:111
gem5::ArmISA::MISCREG_ICC_HSRE
@ MISCREG_ICC_HSRE
Definition: misc.hh:993
gem5::ArmISA::MISCREG_ICH_LR1
@ MISCREG_ICH_LR1
Definition: misc.hh:1026
gem5::ArmISA::MISCREG_PMEVCNTR0_EL0
@ MISCREG_PMEVCNTR0_EL0
Definition: misc.hh:795
gem5::ArmISA::MISCREG_TEECR32_EL1
@ MISCREG_TEECR32_EL1
Definition: misc.hh:540
gem5::ArmISA::MISCREG_AFSR0_EL3
@ MISCREG_AFSR0_EL3
Definition: misc.hh:651
gem5::ArmISA::MISCREG_CSSELR_EL1
@ MISCREG_CSSELR_EL1
Definition: misc.hh:579
gem5::ArmISA::MISCREG_VBAR_EL12
@ MISCREG_VBAR_EL12
Definition: misc.hh:742
gem5::ArmISA::MISCREG_MAIR_EL3
@ MISCREG_MAIR_EL3
Definition: misc.hh:737
gem5::ArmISA::MISCREG_ITLBIALL
@ MISCREG_ITLBIALL
Definition: misc.hh:332
gem5::ArmISA::MISCREG_L2MERRSR
@ MISCREG_L2MERRSR
Definition: misc.hh:455
gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
Definition: misc.hh:575
gem5::ArmISA::MISCREG_DBGPRCR_EL1
@ MISCREG_DBGPRCR_EL1
Definition: misc.hh:536
gem5::ArmISA::MISCREG_NMRR_MAIR1
@ MISCREG_NMRR_MAIR1
Definition: misc.hh:91
gem5::ArmISA::MISCREG_ICH_LR4_EL2
@ MISCREG_ICH_LR4_EL2
Definition: misc.hh:908
gem5::ArmISA::MISCREG_UNKNOWN
@ MISCREG_UNKNOWN
Definition: misc.hh:1075
gem5::ArmISA::MISCREG_PMOVSR
@ MISCREG_PMOVSR
Definition: misc.hh:359
gem5::ArmISA::MISCREG_ICH_ELRSR
@ MISCREG_ICH_ELRSR
Definition: misc.hh:1023
gem5::ArmISA::MISCREG_TLBIALLNSNH
@ MISCREG_TLBIALLNSNH
Definition: misc.hh:354
gem5::ArmISA::MISCREG_TTBR0_EL12
@ MISCREG_TTBR0_EL12
Definition: misc.hh:603
gem5::ArmISA::MISCREG_CNTHP_TVAL
@ MISCREG_CNTHP_TVAL
Definition: misc.hh:437
gem5::ArmISA::MISCREG_ATS12NSOUR
@ MISCREG_ATS12NSOUR
Definition: misc.hh:315
gem5::ArmISA::MISCREG_ELR_HYP
@ MISCREG_ELR_HYP
Definition: misc.hh:74
gem5::ArmISA::MISCREG_DBGWCR10_EL1
@ MISCREG_DBGWCR10_EL1
Definition: misc.hh:521
gem5::ArmISA::MISCREG_CNTVCT_EL0
@ MISCREG_CNTVCT_EL0
Definition: misc.hh:760
gem5::ArmISA::MISCREG_DBGBVR14
@ MISCREG_DBGBVR14
Definition: misc.hh:125
gem5::ArmISA::MISCREG_TLBI_VMALLE1
@ MISCREG_TLBI_VMALLE1
Definition: misc.hh:689
gem5::ArmISA::MISCREG_DBGBVR8_EL1
@ MISCREG_DBGBVR8_EL1
Definition: misc.hh:471
gem5::ArmISA::MISCREG_ICH_LR11_EL2
@ MISCREG_ICH_LR11_EL2
Definition: misc.hh:915
gem5::ArmISA::MISCREG_CBAR_EL1
@ MISCREG_CBAR_EL1
Definition: misc.hh:821
gem5::ArmISA::MISCREG_ICC_AP1R1_EL1
@ MISCREG_ICC_AP1R1_EL1
Definition: misc.hh:854
gem5::ArmISA::MISCREG_DL1DATA3_EL1
@ MISCREG_DL1DATA3_EL1
Definition: misc.hh:814
gem5::ArmISA::MISCREG_RVBAR_EL2
@ MISCREG_RVBAR_EL2
Definition: misc.hh:746
gem5::ArmISA::MISCREG_DBGDEVID2
@ MISCREG_DBGDEVID2
Definition: misc.hh:200
gem5::ArmISA::MISCREG_SP_EL0
@ MISCREG_SP_EL0
Definition: misc.hh:621
gem5::ArmISA::MISCREG_PMCNTENCLR
@ MISCREG_PMCNTENCLR
Definition: misc.hh:358
gem5::ArmISA::MISCREG_ERRSELR_EL1
@ MISCREG_ERRSELR_EL1
Definition: misc.hh:1084
gem5::ArmISA::MISCREG_TLBI_VMALLS12E1
@ MISCREG_TLBI_VMALLS12E1
Definition: misc.hh:708
gem5::ArmISA::MISCREG_DFAR_S
@ MISCREG_DFAR_S
Definition: misc.hh:290
gem5::ArmISA::MISCREG_DBGBVR0_EL1
@ MISCREG_DBGBVR0_EL1
Definition: misc.hh:463
gem5::ArmISA::MISCREG_ICC_AP1R2_NS
@ MISCREG_ICC_AP1R2_NS
Definition: misc.hh:975
gem5::ArmISA::MISCREG_DBGBCR4_EL1
@ MISCREG_DBGBCR4_EL1
Definition: misc.hh:483
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:65
gem5::ArmISA::MISCREG_FPCR
@ MISCREG_FPCR
Definition: misc.hh:626
gem5::ArmISA::MISCREG_SDCR
@ MISCREG_SDCR
Definition: misc.hh:247
gem5::ArmISA::MISCREG_DBGWCR4
@ MISCREG_DBGWCR4
Definition: misc.hh:163
gem5::ArmISA::MISCREG_ICH_LR14_EL2
@ MISCREG_ICH_LR14_EL2
Definition: misc.hh:918
gem5::ArmISA::MISCREG_RMR
@ MISCREG_RMR
Definition: misc.hh:400
gem5::ArmISA::MISCREG_CPACR_EL1
@ MISCREG_CPACR_EL1
Definition: misc.hh:587
gem5::ArmISA::MISCREG_HACR
@ MISCREG_HACR
Definition: misc.hh:258
gem5::ArmISA::MISCREG_ICC_RPR_EL1
@ MISCREG_ICC_RPR_EL1
Definition: misc.hh:864
gem5::ArmISA::MISCREG_DBGBXVR13
@ MISCREG_DBGBXVR13
Definition: misc.hh:189
gem5::ArmISA::MISCREG_IFSR_NS
@ MISCREG_IFSR_NS
Definition: misc.hh:277
gem5::ArmISA::MISCREG_ID_MMFR0
@ MISCREG_ID_MMFR0
Definition: misc.hh:220
gem5::ArmISA::MISCREG_PMEVTYPER5_EL0
@ MISCREG_PMEVTYPER5_EL0
Definition: misc.hh:806
gem5::ArmISA::MISCREG_CNTP_CVAL
@ MISCREG_CNTP_CVAL
Definition: misc.hh:424
gem5::ArmISA::MISCREG_ID_ISAR0
@ MISCREG_ID_ISAR0
Definition: misc.hh:225
gem5::ArmISA::MISCREG_DBGBVR2_EL1
@ MISCREG_DBGBVR2_EL1
Definition: misc.hh:465
gem5::ArmISA::MISCREG_ICC_AP1R3_EL1_S
@ MISCREG_ICC_AP1R3_EL1_S
Definition: misc.hh:862
gem5::ArmISA::MISCREG_DL1DATA4
@ MISCREG_DL1DATA4
Definition: misc.hh:448
gem5::ArmISA::MISCREG_CNTKCTL_EL1
@ MISCREG_CNTKCTL_EL1
Definition: misc.hh:773
gem5::ArmISA::MISCREG_HMAIR0
@ MISCREG_HMAIR0
Definition: misc.hh:392
gem5::ArmISA::MISCREG_DBGWVR11
@ MISCREG_DBGWVR11
Definition: misc.hh:154
gem5::ArmISA::MISCREG_ICC_AP0R3_EL1
@ MISCREG_ICC_AP0R3_EL1
Definition: misc.hh:850
gem5::ArmISA::MISCREG_ICC_BPR1_NS
@ MISCREG_ICC_BPR1_NS
Definition: misc.hh:983
gem5::ArmISA::MISCREG_CNTPCT
@ MISCREG_CNTPCT
Definition: misc.hh:419
gem5::ArmISA::MISCREG_ICH_LR10_EL2
@ MISCREG_ICH_LR10_EL2
Definition: misc.hh:914
gem5::ArmISA::MISCREG_SP_EL2
@ MISCREG_SP_EL2
Definition: misc.hh:639
gem5::ArmISA::MISCREG_ICC_AP0R1
@ MISCREG_ICC_AP0R1
Definition: misc.hh:965
gem5::ArmISA::MISCREG_PMCCFILTR_EL0
@ MISCREG_PMCCFILTR_EL0
Definition: misc.hh:727
gem5::ArmISA::MISCREG_ICH_LR10
@ MISCREG_ICH_LR10
Definition: misc.hh:1035
gem5::ArmISA::MISCREG_CNTPS_CTL_EL1
@ MISCREG_CNTPS_CTL_EL1
Definition: misc.hh:775
gem5::ArmISA::MISCREG_TLBI_VALE2_Xt
@ MISCREG_TLBI_VALE2_Xt
Definition: misc.hh:707
gem5::ArmISA::MISCREG_TLBI_VMALLS12E1IS
@ MISCREG_TLBI_VMALLS12E1IS
Definition: misc.hh:701
gem5::ArmISA::MISCREG_NMRR
@ MISCREG_NMRR
Definition: misc.hh:380
gem5::ArmISA::MISCREG_ICC_SRE_EL1
@ MISCREG_ICC_SRE_EL1
Definition: misc.hh:877
gem5::ArmISA::MISCREG_DBGBVR12_EL1
@ MISCREG_DBGBVR12_EL1
Definition: misc.hh:475
gem5::ArmISA::MISCREG_PMSWINC_EL0
@ MISCREG_PMSWINC_EL0
Definition: misc.hh:721
gem5::ArmISA::MISCREG_SCTLR_EL12
@ MISCREG_SCTLR_EL12
Definition: misc.hh:585
gem5::ArmISA::MISCREG_DBGBVR10
@ MISCREG_DBGBVR10
Definition: misc.hh:121
gem5::ArmISA::MISCREG_TTBR1_EL1
@ MISCREG_TTBR1_EL1
Definition: misc.hh:604
gem5::ArmISA::MISCREG_PMEVTYPER2_EL0
@ MISCREG_PMEVTYPER2_EL0
Definition: misc.hh:803
gem5::ArmISA::MISCREG_MAIR1
@ MISCREG_MAIR1
Definition: misc.hh:383
gem5::ArmISA::MISCREG_TLBI_VAE3IS_Xt
@ MISCREG_TLBI_VAE3IS_Xt
Definition: misc.hh:710
gem5::ArmISA::MISCREG_DAIF
@ MISCREG_DAIF
Definition: misc.hh:625
gem5::ArmISA::MISCREG_SPSR_ABT_AA64
@ MISCREG_SPSR_ABT_AA64
Definition: misc.hh:634
gem5::ArmISA::MISCREG_SEV_MAILBOX
@ MISCREG_SEV_MAILBOX
Definition: misc.hh:96
gem5::ArmISA::MISCREG_SPSR_EL12
@ MISCREG_SPSR_EL12
Definition: misc.hh:618
gem5::ArmISA::MISCREG_CNTP_CVAL_EL02
@ MISCREG_CNTP_CVAL_EL02
Definition: misc.hh:768
gem5::ArmISA::MISCREG_ACTLR_NS
@ MISCREG_ACTLR_NS
Definition: misc.hh:244
gem5::ArmISA::MISCREG_PMINTENSET_EL1
@ MISCREG_PMINTENSET_EL1
Definition: misc.hh:715
gem5::ArmISA::MISCREG_ICC_AP1R1_S
@ MISCREG_ICC_AP1R1_S
Definition: misc.hh:973
gem5::ArmISA::MISCREG_PMINTENCLR_EL1
@ MISCREG_PMINTENCLR_EL1
Definition: misc.hh:716
gem5::ArmISA::MISCREG_CNTHPS_CVAL_EL2
@ MISCREG_CNTHPS_CVAL_EL2
Definition: misc.hh:783
gem5::ArmISA::MISCREG_REVIDR
@ MISCREG_REVIDR
Definition: misc.hh:215
gem5::ArmISA::MISCREG_DBGBCR9
@ MISCREG_DBGBCR9
Definition: misc.hh:136
gem5::ArmISA::MISCREG_DL1DATA0_EL1
@ MISCREG_DL1DATA0_EL1
Definition: misc.hh:811
gem5::ArmISA::MISCREG_TLBI_VAE1IS_Xt
@ MISCREG_TLBI_VAE1IS_Xt
Definition: misc.hh:684
gem5::ArmISA::MISCREG_PMCCFILTR
@ MISCREG_PMCCFILTR
Definition: misc.hh:366
gem5::ArmISA::MISCREG_ACTLR_EL3
@ MISCREG_ACTLR_EL3
Definition: misc.hh:597
gem5::ArmISA::MISCREG_ID_PFR1_EL1
@ MISCREG_ID_PFR1_EL1
Definition: misc.hh:548
gem5::ArmISA::MISCREG_DBGBCR11_EL1
@ MISCREG_DBGBCR11_EL1
Definition: misc.hh:490
gem5::ArmISA::MISCREG_DBGBCR1_EL1
@ MISCREG_DBGBCR1_EL1
Definition: misc.hh:480
gem5::ArmISA::MISCREG_TLBIIPAS2IS
@ MISCREG_TLBIIPAS2IS
Definition: misc.hh:344
gem5::ArmISA::MISCREG_DBGBVR11_EL1
@ MISCREG_DBGBVR11_EL1
Definition: misc.hh:474
gem5::ArmISA::MISCREG_DBGBCR14
@ MISCREG_DBGBCR14
Definition: misc.hh:141
gem5::ArmISA::MISCREG_DBGBCR11
@ MISCREG_DBGBCR11
Definition: misc.hh:138
gem5::ArmISA::MISCREG_APDBKeyHi_EL1
@ MISCREG_APDBKeyHi_EL1
Definition: misc.hh:832
gem5::ArmISA::MISCREG_TEEHBR32_EL1
@ MISCREG_TEEHBR32_EL1
Definition: misc.hh:541
gem5::ArmISA::MISCREG_DBGBVR13
@ MISCREG_DBGBVR13
Definition: misc.hh:124
gem5::ArmISA::MISCREG_ID_MMFR3
@ MISCREG_ID_MMFR3
Definition: misc.hh:223
gem5::ArmISA::MISCREG_CSSELR_S
@ MISCREG_CSSELR_S
Definition: misc.hh:237
gem5::ArmISA::MISCREG_DBGBCR12
@ MISCREG_DBGBCR12
Definition: misc.hh:139
gem5::ArmISA::MISCREG_ICH_LRC15
@ MISCREG_ICH_LRC15
Definition: misc.hh:1056
gem5::ArmISA::MISCREG_ICC_SRE_EL2
@ MISCREG_ICC_SRE_EL2
Definition: misc.hh:884
gem5::ArmISA::MISCREG_ICH_HCR
@ MISCREG_ICH_HCR
Definition: misc.hh:1019
gem5::ArmISA::MISCREG_ICC_IAR0
@ MISCREG_ICC_IAR0
Definition: misc.hh:994
gem5::ArmISA::MISCREG_ICC_ASGI1R_EL1
@ MISCREG_ICC_ASGI1R_EL1
Definition: misc.hh:866
gem5::ArmISA::MISCREG_DBGVCR32_EL2
@ MISCREG_DBGVCR32_EL2
Definition: misc.hh:531
gem5::ArmISA::MISCREG_DBGWVR9_EL1
@ MISCREG_DBGWVR9_EL1
Definition: misc.hh:504
gem5::ArmISA::MISCREG_L2ECTLR
@ MISCREG_L2ECTLR
Definition: misc.hh:373
gem5::ArmISA::MISCREG_ID_PFR0_EL1
@ MISCREG_ID_PFR0_EL1
Definition: misc.hh:547
gem5::ArmISA::MISCREG_ICC_CTLR
@ MISCREG_ICC_CTLR
Definition: misc.hh:985
gem5::ArmISA::MISCREG_ICH_LR2_EL2
@ MISCREG_ICH_LR2_EL2
Definition: misc.hh:906
gem5::ArmISA::MISCREG_DL1DATA4_EL1
@ MISCREG_DL1DATA4_EL1
Definition: misc.hh:815
gem5::ArmISA::MISCREG_TLBIMVAAIS
@ MISCREG_TLBIMVAAIS
Definition: misc.hh:329
gem5::ArmISA::MISCREG_ICC_EOIR0
@ MISCREG_ICC_EOIR0
Definition: misc.hh:989
gem5::ArmISA::MISCREG_CNTP_CVAL_NS
@ MISCREG_CNTP_CVAL_NS
Definition: misc.hh:425
gem5::ArmISA::MISCREG_OSECCR_EL1
@ MISCREG_OSECCR_EL1
Definition: misc.hh:462
gem5::ArmISA::MISCREG_RVBAR_EL1
@ MISCREG_RVBAR_EL1
Definition: misc.hh:743
gem5::ArmISA::MISCREG_ISR
@ MISCREG_ISR
Definition: misc.hh:401
gem5::ArmISA::MISCREG_DBGWCR7_EL1
@ MISCREG_DBGWCR7_EL1
Definition: misc.hh:518
gem5::ArmISA::MISCREG_HAIFSR
@ MISCREG_HAIFSR
Definition: misc.hh:286
gem5::ArmISA::MISCREG_ID_ISAR5_EL1
@ MISCREG_ID_ISAR5_EL1
Definition: misc.hh:561
gem5::ArmISA::MISCREG_CONTEXTIDR
@ MISCREG_CONTEXTIDR
Definition: misc.hh:404
gem5::ArmISA::MISCREG_PMCEID1
@ MISCREG_PMCEID1
Definition: misc.hh:363
gem5::ArmISA::MISCREG_TLBI_ALLE3IS
@ MISCREG_TLBI_ALLE3IS
Definition: misc.hh:709
gem5::ArmISA::MISCREG_DBGBVR15_EL1
@ MISCREG_DBGBVR15_EL1
Definition: misc.hh:478
gem5::ArmISA::MISCREG_ID_ISAR4_EL1
@ MISCREG_ID_ISAR4_EL1
Definition: misc.hh:560
gem5::ArmISA::MISCREG_CNTHPS_TVAL_EL2
@ MISCREG_CNTHPS_TVAL_EL2
Definition: misc.hh:784
gem5::ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition: misc.hh:248
gem5::ArmISA::MISCREG_DC_IVAC_Xt
@ MISCREG_DC_IVAC_Xt
Definition: misc.hh:662
gem5::ArmISA::MISCREG_ICC_AP1R0
@ MISCREG_ICC_AP1R0
Definition: misc.hh:968
gem5::ArmISA::MISCREG_ICC_HPPIR0_EL1
@ MISCREG_ICC_HPPIR0_EL1
Definition: misc.hh:845
gem5::ArmISA::MISCREG_TLBI_IPAS2LE1IS_Xt
@ MISCREG_TLBI_IPAS2LE1IS_Xt
Definition: misc.hh:696
gem5::ArmISA::MISCREG_PMCNTENSET
@ MISCREG_PMCNTENSET
Definition: misc.hh:357
gem5::ArmISA::MISCREG_DBGBVR7
@ MISCREG_DBGBVR7
Definition: misc.hh:118
gem5::ArmISA::MISCREG_ICC_SGI1R_EL1
@ MISCREG_ICC_SGI1R_EL1
Definition: misc.hh:865
gem5::ArmISA::MISCREG_DBGWVR9
@ MISCREG_DBGWVR9
Definition: misc.hh:152
gem5::ArmISA::MISCREG_ELR_EL2
@ MISCREG_ELR_EL2
Definition: misc.hh:631
gem5::ArmISA::MISCREG_MAIR0_S
@ MISCREG_MAIR0_S
Definition: misc.hh:379
gem5::ArmISA::MISCREG_ICH_LR5_EL2
@ MISCREG_ICH_LR5_EL2
Definition: misc.hh:909
gem5::ArmISA::MISCREG_CONTEXTIDR_EL2
@ MISCREG_CONTEXTIDR_EL2
Definition: misc.hh:822
gem5::ArmISA::MISCREG_CNTP_TVAL_S
@ MISCREG_CNTP_TVAL_S
Definition: misc.hh:429
gem5::ArmISA::MISCREG_TCR_EL12
@ MISCREG_TCR_EL12
Definition: misc.hh:607
gem5::ArmISA::MISCREG_CNTHCTL_EL2
@ MISCREG_CNTHCTL_EL2
Definition: misc.hh:778
gem5::ArmISA::MISCREG_DBGBXVR6
@ MISCREG_DBGBXVR6
Definition: misc.hh:182
gem5::ArmISA::MISCREG_DBGBXVR0
@ MISCREG_DBGBXVR0
Definition: misc.hh:176
gem5::ArmISA::MISCREG_TEEHBR
@ MISCREG_TEEHBR
Definition: misc.hh:205
gem5::ArmISA::MISCREG_ERXMISC1_EL1
@ MISCREG_ERXMISC1_EL1
Definition: misc.hh:1090
gem5::ArmISA::MISCREG_MDSCR_EL1
@ MISCREG_MDSCR_EL1
Definition: misc.hh:460
gem5::ArmISA::MISCREG_AMAIR1_NS
@ MISCREG_AMAIR1_NS
Definition: misc.hh:390
gem5::ArmISA::MISCREG_DL1DATA2
@ MISCREG_DL1DATA2
Definition: misc.hh:446
gem5::ArmISA::MISCREG_DBGWCR2_EL1
@ MISCREG_DBGWCR2_EL1
Definition: misc.hh:513
gem5::ArmISA::MISCREG_ID_MMFR4_EL1
@ MISCREG_ID_MMFR4_EL1
Definition: misc.hh:555
gem5::ArmISA::MISCREG_PAR_S
@ MISCREG_PAR_S
Definition: misc.hh:301
gem5::ArmISA::MISCREG_DBGBCR12_EL1
@ MISCREG_DBGBCR12_EL1
Definition: misc.hh:491
gem5::ArmISA::MISCREG_ID_DFR0
@ MISCREG_ID_DFR0
Definition: misc.hh:218
gem5::ArmISA::MISCREG_CNTP_CTL_S
@ MISCREG_CNTP_CTL_S
Definition: misc.hh:423
gem5::ArmISA::MISCREG_ICC_AP1R1_EL1_NS
@ MISCREG_ICC_AP1R1_EL1_NS
Definition: misc.hh:855
gem5::ArmISA::MISCREG_TTBR1_EL2
@ MISCREG_TTBR1_EL2
Definition: misc.hh:825
gem5::ArmISA::MISCREG_ICC_SGI1R
@ MISCREG_ICC_SGI1R
Definition: misc.hh:1006
gem5::ArmISA::MISCREG_DBGDTRTXint
@ MISCREG_DBGDTRTXint
Definition: misc.hh:103
gem5::ArmISA::MISCREG_ID_AA64MMFR0_EL1
@ MISCREG_ID_AA64MMFR0_EL1
Definition: misc.hh:574
gem5::ArmISA::MISCREG_HPFAR
@ MISCREG_HPFAR
Definition: misc.hh:296
gem5::ArmISA::MISCREG_ICC_PMR
@ MISCREG_ICC_PMR
Definition: misc.hh:1003
gem5::ArmISA::MISCREG_PAN
@ MISCREG_PAN
Definition: misc.hh:1096
gem5::ArmISA::MISCREG_ICH_LRC5
@ MISCREG_ICH_LRC5
Definition: misc.hh:1046
gem5::ArmISA::MISCREG_TPIDRPRW_S
@ MISCREG_TPIDRPRW_S
Definition: misc.hh:415
gem5::ArmISA::MISCREG_ICH_LR6
@ MISCREG_ICH_LR6
Definition: misc.hh:1031
gem5::ArmISA::MISCREG_TLBIMVAHIS
@ MISCREG_TLBIMVAHIS
Definition: misc.hh:347
gem5::ArmISA::MISCREG_IC_IALLU
@ MISCREG_IC_IALLU
Definition: misc.hh:661
gem5::ArmISA::MISCREG_ICC_AP1R2
@ MISCREG_ICC_AP1R2
Definition: misc.hh:974
gem5::ArmISA::MISCREG_DBGWCR9
@ MISCREG_DBGWCR9
Definition: misc.hh:168
gem5::ArmISA::MISCREG_APIAKeyHi_EL1
@ MISCREG_APIAKeyHi_EL1
Definition: misc.hh:836
gem5::ArmISA::MISCREG_SPSR_EL3
@ MISCREG_SPSR_EL3
Definition: misc.hh:637
gem5::ArmISA::MISCREG_APDAKeyLo_EL1
@ MISCREG_APDAKeyLo_EL1
Definition: misc.hh:831
gem5::ArmISA::MISCREG_AT_S1E1R_Xt
@ MISCREG_AT_S1E1R_Xt
Definition: misc.hh:664
gem5::ArmISA::MISCREG_ICH_AP1R2_EL2
@ MISCREG_ICH_AP1R2_EL2
Definition: misc.hh:896
gem5::ArmISA::MISCREG_DTLBIALL
@ MISCREG_DTLBIALL
Definition: misc.hh:335
gem5::ArmISA::MISCREG_TLBIALLIS
@ MISCREG_TLBIALLIS
Definition: misc.hh:326
gem5::ArmISA::MISCREG_AMAIR_EL1
@ MISCREG_AMAIR_EL1
Definition: misc.hh:733
gem5::ArmISA::MISCREG_ICC_CTLR_EL1_NS
@ MISCREG_ICC_CTLR_EL1_NS
Definition: misc.hh:875
gem5::ArmISA::MISCREG_ICC_CTLR_S
@ MISCREG_ICC_CTLR_S
Definition: misc.hh:987
gem5::ArmISA::MISCREG_ESR_EL3
@ MISCREG_ESR_EL3
Definition: misc.hh:653
gem5::ArmISA::MISCREG_IL1DATA0
@ MISCREG_IL1DATA0
Definition: misc.hh:440
gem5::ArmISA::MISCREG_ATS1HW
@ MISCREG_ATS1HW
Definition: misc.hh:325
gem5::ArmISA::MISCREG_ICH_VTR
@ MISCREG_ICH_VTR
Definition: misc.hh:1020
gem5::ArmISA::MISCREG_VBAR_S
@ MISCREG_VBAR_S
Definition: misc.hh:398
gem5::ArmISA::MISCREG_ICH_AP0R1_EL2
@ MISCREG_ICH_AP0R1_EL2
Definition: misc.hh:891
gem5::ArmISA::MISCREG_AT_S1E3R_Xt
@ MISCREG_AT_S1E3R_Xt
Definition: misc.hh:681
gem5::ArmISA::MISCREG_ICC_SRE
@ MISCREG_ICC_SRE
Definition: misc.hh:1007
gem5::ArmISA::MISCREG_DC_ZVA_Xt
@ MISCREG_DC_ZVA_Xt
Definition: misc.hh:670
gem5::ArmISA::MISCREG_CNTHVS_TVAL_EL2
@ MISCREG_CNTHVS_TVAL_EL2
Definition: misc.hh:791
gem5::ArmISA::MISCREG_ATS1CPR
@ MISCREG_ATS1CPR
Definition: misc.hh:309
gem5::ArmISA::MISCREG_TLBIASID
@ MISCREG_TLBIASID
Definition: misc.hh:340
gem5::ArmISA::MISCREG_ICH_LRC12
@ MISCREG_ICH_LRC12
Definition: misc.hh:1053
gem5::ArmISA::MISCREG_DBGBXVR10
@ MISCREG_DBGBXVR10
Definition: misc.hh:186
gem5::ArmISA::MISCREG_APGAKeyLo_EL1
@ MISCREG_APGAKeyLo_EL1
Definition: misc.hh:835
gem5::ArmISA::MISCREG_ITLBIMVA
@ MISCREG_ITLBIMVA
Definition: misc.hh:333
gem5::ArmISA::MISCREG_NZCV
@ MISCREG_NZCV
Definition: misc.hh:624
gem5::ArmISA::MISCREG_HTTBR
@ MISCREG_HTTBR
Definition: misc.hh:452
gem5::ArmISA::MISCREG_IFSR32_EL2
@ MISCREG_IFSR32_EL2
Definition: misc.hh:646
gem5::ArmISA::MISCREG_ICH_LRC9
@ MISCREG_ICH_LRC9
Definition: misc.hh:1050
gem5::ArmISA::MISCREG_SPSR_EL1
@ MISCREG_SPSR_EL1
Definition: misc.hh:617
gem5::ArmISA::MISCREG_APIBKeyHi_EL1
@ MISCREG_APIBKeyHi_EL1
Definition: misc.hh:838
gem5::ArmISA::MISCREG_FAR_EL12
@ MISCREG_FAR_EL12
Definition: misc.hh:655
gem5::ArmISA::MISCREG_MAIR0_NS
@ MISCREG_MAIR0_NS
Definition: misc.hh:378
gem5::ArmISA::MISCREG_CP15DSB
@ MISCREG_CP15DSB
Definition: misc.hh:319
gem5::ArmISA::MISCREG_ICH_LR13_EL2
@ MISCREG_ICH_LR13_EL2
Definition: misc.hh:917
gem5::ArmISA::MISCREG_ICC_CTLR_EL3
@ MISCREG_ICC_CTLR_EL3
Definition: misc.hh:885
gem5::ArmISA::MISCREG_DBGDCCINT
@ MISCREG_DBGDCCINT
Definition: misc.hh:102
gem5::ArmISA::MISCREG_ICC_CTLR_EL1
@ MISCREG_ICC_CTLR_EL1
Definition: misc.hh:874
gem5::ArmISA::MISCREG_TLBIALLNSNHIS
@ MISCREG_TLBIALLNSNHIS
Definition: misc.hh:348
gem5::ArmISA::MISCREG_CNTP_CVAL_EL0
@ MISCREG_CNTP_CVAL_EL0
Definition: misc.hh:762
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: misc.hh:591
gem5::ArmISA::MISCREG_CNTHVS_CVAL_EL2
@ MISCREG_CNTHVS_CVAL_EL2
Definition: misc.hh:790
gem5::ArmISA::MISCREG_L2ACTLR_EL1
@ MISCREG_L2ACTLR_EL1
Definition: misc.hh:816
gem5::ArmISA::MISCREG_DCIMVAC
@ MISCREG_DCIMVAC
Definition: misc.hh:307
gem5::ArmISA::MISCREG_ATS1CPW
@ MISCREG_ATS1CPW
Definition: misc.hh:310
gem5::ArmISA::MISCREG_TTBR1
@ MISCREG_TTBR1
Definition: misc.hh:262
gem5::ArmISA::MISCREG_AT_S12E0R_Xt
@ MISCREG_AT_S12E0R_Xt
Definition: misc.hh:679
gem5::ArmISA::MISCREG_ICH_AP1R0
@ MISCREG_ICH_AP1R0
Definition: misc.hh:1015
gem5::ArmISA::MISCREG_MPIDR
@ MISCREG_MPIDR
Definition: misc.hh:214
gem5::ArmISA::MISCREG_ICC_AP0R2
@ MISCREG_ICC_AP0R2
Definition: misc.hh:966
gem5::ArmISA::MISCREG_DBGCLAIMSET
@ MISCREG_DBGCLAIMSET
Definition: misc.hh:197
gem5::ArmISA::MISCREG_TLBIMVALHIS
@ MISCREG_TLBIMVALHIS
Definition: misc.hh:349
gem5::ArmISA::MISCREG_PRRR_NS
@ MISCREG_PRRR_NS
Definition: misc.hh:375
gem5::ArmISA::MISCREG_ZCR_EL1
@ MISCREG_ZCR_EL1
Definition: misc.hh:1063
gem5::ArmISA::MISCREG_PMCEID0_EL0
@ MISCREG_PMCEID0_EL0
Definition: misc.hh:723
gem5::ArmISA::MISCREG_ID_AA64MMFR2_EL1
@ MISCREG_ID_AA64MMFR2_EL1
Definition: misc.hh:827
gem5::ArmISA::MISCREG_ICC_DIR_EL1
@ MISCREG_ICC_DIR_EL1
Definition: misc.hh:863
gem5::ArmISA::MISCREG_SDER32_EL3
@ MISCREG_SDER32_EL3
Definition: misc.hh:599
gem5::ArmISA::MISCREG_TPIDR_EL0
@ MISCREG_TPIDR_EL0
Definition: misc.hh:753
gem5::ArmISA::MISCREG_DBGDTRTXext
@ MISCREG_DBGDTRTXext
Definition: misc.hh:109
gem5::ArmISA::MISCREG_DBGOSECCR
@ MISCREG_DBGOSECCR
Definition: misc.hh:110
gem5::ArmISA::MISCREG_ICC_SRE_EL3
@ MISCREG_ICC_SRE_EL3
Definition: misc.hh:886
gem5::ArmISA::MISCREG_VTCR_EL2
@ MISCREG_VTCR_EL2
Definition: misc.hh:611
gem5::ArmISA::MISCREG_DBGWCR3
@ MISCREG_DBGWCR3
Definition: misc.hh:162
gem5::ArmISA::MISCREG_ELR_EL3
@ MISCREG_ELR_EL3
Definition: misc.hh:638
gem5::ArmISA::MISCREG_ITLBIASID
@ MISCREG_ITLBIASID
Definition: misc.hh:334
gem5::ArmISA::MISCREG_ICH_LR12
@ MISCREG_ICH_LR12
Definition: misc.hh:1037
gem5::ArmISA::MISCREG_DBGWCR11
@ MISCREG_DBGWCR11
Definition: misc.hh:170
gem5::ArmISA::MISCREG_DBGCLAIMSET_EL1
@ MISCREG_DBGCLAIMSET_EL1
Definition: misc.hh:537
gem5::ArmISA::MISCREG_ICH_LR3_EL2
@ MISCREG_ICH_LR3_EL2
Definition: misc.hh:907
gem5::ArmISA::MISCREG_VTTBR
@ MISCREG_VTTBR
Definition: misc.hh:453
gem5::ArmISA::MISCREG_MDDTRRX_EL0
@ MISCREG_MDDTRRX_EL0
Definition: misc.hh:530
gem5::ArmISA::MISCREG_CNTVOFF_EL2
@ MISCREG_CNTVOFF_EL2
Definition: misc.hh:793
gem5::ArmISA::MISCREG_AIFSR
@ MISCREG_AIFSR
Definition: misc.hh:282
gem5::ArmISA::MISCREG_DBGWCR6
@ MISCREG_DBGWCR6
Definition: misc.hh:165
gem5::ArmISA::MISCREG_ICH_AP1R1_EL2
@ MISCREG_ICH_AP1R1_EL2
Definition: misc.hh:895
gem5::ArmISA::MISCREG_TLBI_VAALE1_Xt
@ MISCREG_TLBI_VAALE1_Xt
Definition: misc.hh:694
gem5::ArmISA::MISCREG_VPIDR
@ MISCREG_VPIDR
Definition: misc.hh:238
gem5::ArmISA::MISCREG_ICH_AP1R2
@ MISCREG_ICH_AP1R2
Definition: misc.hh:1017
gem5::ArmISA::MISCREG_BPIALLIS
@ MISCREG_BPIALLIS
Definition: misc.hh:298
gem5::ArmISA::MISCREG_ICC_AP1R0_EL1_NS
@ MISCREG_ICC_AP1R0_EL1_NS
Definition: misc.hh:852
gem5::ArmISA::MISCREG_DBGWCR15
@ MISCREG_DBGWCR15
Definition: misc.hh:174
gem5::ArmISA::MISCREG_CNTHCTL
@ MISCREG_CNTHCTL
Definition: misc.hh:434
gem5::ArmISA::MISCREG_ICC_EOIR0_EL1
@ MISCREG_ICC_EOIR0_EL1
Definition: misc.hh:844
gem5::ArmISA::MISCREG_TTBR1_NS
@ MISCREG_TTBR1_NS
Definition: misc.hh:263
gem5::ArmISA::MISCREG_FAR_EL3
@ MISCREG_FAR_EL3
Definition: misc.hh:658
gem5::ArmISA::MISCREG_ACTLR_EL1
@ MISCREG_ACTLR_EL1
Definition: misc.hh:586
gem5::ArmISA::MISCREG_ICH_LR8_EL2
@ MISCREG_ICH_LR8_EL2
Definition: misc.hh:912
gem5::ArmISA::MISCREG_CNTHPS_CTL_EL2
@ MISCREG_CNTHPS_CTL_EL2
Definition: misc.hh:782
gem5::ArmISA::MISCREG_DBGBVR3_EL1
@ MISCREG_DBGBVR3_EL1
Definition: misc.hh:466
gem5::ArmISA::MISCREG_DBGVCR
@ MISCREG_DBGVCR
Definition: misc.hh:106
gem5::ArmISA::MISCREG_MDCCINT_EL1
@ MISCREG_MDCCINT_EL1
Definition: misc.hh:458
gem5::ArmISA::MISCREG_DBGBVR6_EL1
@ MISCREG_DBGBVR6_EL1
Definition: misc.hh:469
gem5::ArmISA::MISCREG_DBGWCR9_EL1
@ MISCREG_DBGWCR9_EL1
Definition: misc.hh:520
gem5::ArmISA::MISCREG_ICC_IAR1
@ MISCREG_ICC_IAR1
Definition: misc.hh:995
gem5::ArmISA::MISCREG_IL1DATA3_EL1
@ MISCREG_IL1DATA3_EL1
Definition: misc.hh:810
gem5::ArmISA::MISCREG_ICH_LR15
@ MISCREG_ICH_LR15
Definition: misc.hh:1040
gem5::ArmISA::MISCREG_DC_CISW_Xt
@ MISCREG_DC_CISW_Xt
Definition: misc.hh:669
gem5::ArmISA::MISCREG_ICH_AP0R0
@ MISCREG_ICH_AP0R0
Definition: misc.hh:1011
gem5::ArmISA::MISCREG_VBAR_EL2
@ MISCREG_VBAR_EL2
Definition: misc.hh:745
gem5::ArmISA::MISCREG_ICC_AP1R2_EL1_S
@ MISCREG_ICC_AP1R2_EL1_S
Definition: misc.hh:859
gem5::ArmISA::MISCREG_DBGBCR7_EL1
@ MISCREG_DBGBCR7_EL1
Definition: misc.hh:486
gem5::ArmISA::MISCREG_ICC_EOIR1_EL1
@ MISCREG_ICC_EOIR1_EL1
Definition: misc.hh:869
gem5::ArmISA::MISCREG_ICIMVAU
@ MISCREG_ICIMVAU
Definition: misc.hh:303
gem5::ArmISA::MISCREG_ICH_AP0R3_EL2
@ MISCREG_ICH_AP0R3_EL2
Definition: misc.hh:893
gem5::ArmISA::MISCREG_DBGWCR14
@ MISCREG_DBGWCR14
Definition: misc.hh:173
gem5::ArmISA::MISCREG_DBGBCR5_EL1
@ MISCREG_DBGBCR5_EL1
Definition: misc.hh:484
gem5::ArmISA::MISCREG_L2ACTLR
@ MISCREG_L2ACTLR
Definition: misc.hh:450
gem5::ArmISA::MISCREG_ACTLR_EL2
@ MISCREG_ACTLR_EL2
Definition: misc.hh:590
gem5::ArmISA::MISCREG_CPUMERRSR_EL1
@ MISCREG_CPUMERRSR_EL1
Definition: misc.hh:819
gem5::ArmISA::MISCREG_IFAR_NS
@ MISCREG_IFAR_NS
Definition: misc.hh:292
gem5::ArmISA::MISCREG_DBGWVR15_EL1
@ MISCREG_DBGWVR15_EL1
Definition: misc.hh:510
gem5::ArmISA::MISCREG_CTR
@ MISCREG_CTR
Definition: misc.hh:211
gem5::ArmISA::MISCREG_HPFAR_EL2
@ MISCREG_HPFAR_EL2
Definition: misc.hh:657
gem5::ArmISA::MISCREG_TPIDRURW
@ MISCREG_TPIDRURW
Definition: misc.hh:407
gem5::ArmISA::MISCREG_DBGBXVR11
@ MISCREG_DBGBXVR11
Definition: misc.hh:187
gem5::ArmISA::MISCREG_ICH_LRC6
@ MISCREG_ICH_LRC6
Definition: misc.hh:1047
gem5::ArmISA::MISCREG_ICH_LR1_EL2
@ MISCREG_ICH_LR1_EL2
Definition: misc.hh:905
gem5::ArmISA::MISCREG_CLIDR
@ MISCREG_CLIDR
Definition: misc.hh:233
gem5::ArmISA::MISCREG_SCTLR_S
@ MISCREG_SCTLR_S
Definition: misc.hh:242
gem5::ArmISA::MISCREG_DBGDTRRXint
@ MISCREG_DBGDTRRXint
Definition: misc.hh:104
gem5::ArmISA::MISCREG_ICH_AP0R1
@ MISCREG_ICH_AP0R1
Definition: misc.hh:1012
gem5::ArmISA::MISCREG_MDCR_EL2
@ MISCREG_MDCR_EL2
Definition: misc.hh:592
gem5::ArmISA::MISCREG_VBAR
@ MISCREG_VBAR
Definition: misc.hh:396
gem5::ArmISA::MISCREG_IFSR
@ MISCREG_IFSR
Definition: misc.hh:276
gem5::ArmISA::MISCREG_PMSELR
@ MISCREG_PMSELR
Definition: misc.hh:361
gem5::ArmISA::MISCREG_ICIALLUIS
@ MISCREG_ICIALLUIS
Definition: misc.hh:297
gem5::ArmISA::MISCREG_HACTLR
@ MISCREG_HACTLR
Definition: misc.hh:252
gem5::ArmISA::MISCREG_ID_MMFR0_EL1
@ MISCREG_ID_MMFR0_EL1
Definition: misc.hh:551
gem5::ArmISA::MISCREG_AMAIR1
@ MISCREG_AMAIR1
Definition: misc.hh:389
gem5::ArmISA::MISCREG_CNTHV_TVAL_EL2
@ MISCREG_CNTHV_TVAL_EL2
Definition: misc.hh:788
gem5::ArmISA::MISCREG_VBAR_EL1
@ MISCREG_VBAR_EL1
Definition: misc.hh:741
gem5::ArmISA::MISCREG_MIDR
@ MISCREG_MIDR
Definition: misc.hh:210
gem5::ArmISA::MISCREG_ICH_EISR
@ MISCREG_ICH_EISR
Definition: misc.hh:1022
gem5::ArmISA::MISCREG_PMEVCNTR2_EL0
@ MISCREG_PMEVCNTR2_EL0
Definition: misc.hh:797
gem5::ArmISA::MISCREG_CNTPS_CVAL_EL1
@ MISCREG_CNTPS_CVAL_EL1
Definition: misc.hh:776
gem5::ArmISA::MISCREG_HTCR
@ MISCREG_HTCR
Definition: misc.hh:268
gem5::ArmISA::MISCREG_AMAIR_EL2
@ MISCREG_AMAIR_EL2
Definition: misc.hh:736
gem5::ArmISA::MISCREG_ICC_BPR0
@ MISCREG_ICC_BPR0
Definition: misc.hh:981
gem5::ArmISA::MISCREG_TLBIMVAIS
@ MISCREG_TLBIMVAIS
Definition: misc.hh:327
gem5::ArmISA::MISCREG_TTBR1_S
@ MISCREG_TTBR1_S
Definition: misc.hh:264
gem5::ArmISA::MISCREG_ICH_LR2
@ MISCREG_ICH_LR2
Definition: misc.hh:1027
gem5::ArmISA::MISCREG_HVBAR
@ MISCREG_HVBAR
Definition: misc.hh:402
gem5::ArmISA::MISCREG_JIDR
@ MISCREG_JIDR
Definition: misc.hh:204
gem5::ArmISA::MISCREG_DC_ISW_Xt
@ MISCREG_DC_ISW_Xt
Definition: misc.hh:663
gem5::ArmISA::MISCREG_RAZ
@ MISCREG_RAZ
Definition: misc.hh:1074
gem5::ArmISA::MISCREG_L2CTLR
@ MISCREG_L2CTLR
Definition: misc.hh:372
gem5::ArmISA::MISCREG_DBGPRCR
@ MISCREG_DBGPRCR
Definition: misc.hh:195
gem5::ArmISA::MISCREG_DBGWVR10
@ MISCREG_DBGWVR10
Definition: misc.hh:153
gem5::ArmISA::MISCREG_CNTP_CTL
@ MISCREG_CNTP_CTL
Definition: misc.hh:421
gem5::ArmISA::MISCREG_TTBR0_EL3
@ MISCREG_TTBR0_EL3
Definition: misc.hh:614
gem5::ArmISA::MISCREG_ICC_AP0R0_EL1
@ MISCREG_ICC_AP0R0_EL1
Definition: misc.hh:847
gem5::ArmISA::MISCREG_ICC_IGRPEN0_EL1
@ MISCREG_ICC_IGRPEN0_EL1
Definition: misc.hh:880
gem5::ArmISA::MISCREG_DBGWCR0_EL1
@ MISCREG_DBGWCR0_EL1
Definition: misc.hh:511
gem5::ArmISA::MISCREG_ICC_AP1R2_S
@ MISCREG_ICC_AP1R2_S
Definition: misc.hh:976
gem5::ArmISA::MISCREG_DCZID_EL0
@ MISCREG_DCZID_EL0
Definition: misc.hh:581
gem5::ArmISA::MISCREG_ICH_LRC13
@ MISCREG_ICH_LRC13
Definition: misc.hh:1054
gem5::ArmISA::MISCREG_TLBIALLH
@ MISCREG_TLBIALLH
Definition: misc.hh:352
gem5::ArmISA::MISCREG_ICC_AP1R2_EL1_NS
@ MISCREG_ICC_AP1R2_EL1_NS
Definition: misc.hh:858
gem5::ArmISA::MISCREG_ICH_VMCR_EL2
@ MISCREG_ICH_VMCR_EL2
Definition: misc.hh:903
gem5::ArmISA::MISCREG_ATS12NSOPW
@ MISCREG_ATS12NSOPW
Definition: misc.hh:314
gem5::ArmISA::MISCREG_TLBI_VAE3_Xt
@ MISCREG_TLBI_VAE3_Xt
Definition: misc.hh:713
gem5::ArmISA::MISCREG_ICH_LRC14
@ MISCREG_ICH_LRC14
Definition: misc.hh:1055
gem5::ArmISA::MISCREG_DACR_NS
@ MISCREG_DACR_NS
Definition: misc.hh:271
gem5::ArmISA::MISCREG_TLBIMVAH
@ MISCREG_TLBIMVAH
Definition: misc.hh:353
gem5::ArmISA::MISCREG_ICC_EOIR1
@ MISCREG_ICC_EOIR1
Definition: misc.hh:990
gem5::ArmISA::MISCREG_DBGWVR12
@ MISCREG_DBGWVR12
Definition: misc.hh:155
gem5::ArmISA::MISCREG_TLBI_VALE3IS_Xt
@ MISCREG_TLBI_VALE3IS_Xt
Definition: misc.hh:711
gem5::ArmISA::MISCREG_ISR_EL1
@ MISCREG_ISR_EL1
Definition: misc.hh:744
gem5::ArmISA::MISCREG_ICC_SGI0R_EL1
@ MISCREG_ICC_SGI0R_EL1
Definition: misc.hh:867
gem5::ArmISA::MISCREG_HACR_EL2
@ MISCREG_HACR_EL2
Definition: misc.hh:595
gem5::ArmISA::MISCREG_DBGBCR4
@ MISCREG_DBGBCR4
Definition: misc.hh:131
gem5::ArmISA::MISCREG_OSDTRTX_EL1
@ MISCREG_OSDTRTX_EL1
Definition: misc.hh:461
gem5::ArmISA::MISCREG_CNTVOFF
@ MISCREG_CNTVOFF
Definition: misc.hh:438
gem5::ArmISA::MISCREG_ICH_LR12_EL2
@ MISCREG_ICH_LR12_EL2
Definition: misc.hh:916
gem5::ArmISA::MISCREG_DBGCLAIMCLR_EL1
@ MISCREG_DBGCLAIMCLR_EL1
Definition: misc.hh:538
gem5::ArmISA::MISCREG_ICH_LRC3
@ MISCREG_ICH_LRC3
Definition: misc.hh:1044
gem5::ArmISA::MISCREG_AT_S1E0W_Xt
@ MISCREG_AT_S1E0W_Xt
Definition: misc.hh:667
gem5::ArmISA::MISCREG_AMAIR0_S
@ MISCREG_AMAIR0_S
Definition: misc.hh:388
gem5::ArmISA::MISCREG_DCCSW
@ MISCREG_DCCSW
Definition: misc.hh:318
gem5::ArmISA::MISCREG_AT_S12E1R_Xt
@ MISCREG_AT_S12E1R_Xt
Definition: misc.hh:677
gem5::ArmISA::MISCREG_DBGBXVR2
@ MISCREG_DBGBXVR2
Definition: misc.hh:178
gem5::ArmISA::MISCREG_TLBTR
@ MISCREG_TLBTR
Definition: misc.hh:213
gem5::ArmISA::MISCREG_DBGWVR0
@ MISCREG_DBGWVR0
Definition: misc.hh:143
gem5::ArmISA::MISCREG_ID_AA64AFR1_EL1
@ MISCREG_ID_AA64AFR1_EL1
Definition: misc.hh:571
gem5::ArmISA::MISCREG_DBGWCR12
@ MISCREG_DBGWCR12
Definition: misc.hh:171
gem5::ArmISA::MISCREG_AFSR0_EL12
@ MISCREG_AFSR0_EL12
Definition: misc.hh:641
gem5::ArmISA::MISCREG_DCCMVAU
@ MISCREG_DCCMVAU
Definition: misc.hh:321
gem5::ArmISA::MISCREG_IL1DATA2_EL1
@ MISCREG_IL1DATA2_EL1
Definition: misc.hh:809
gem5::ArmISA::MISCREG_ICH_LR3
@ MISCREG_ICH_LR3
Definition: misc.hh:1028
gem5::ArmISA::MISCREG_DBGBVR14_EL1
@ MISCREG_DBGBVR14_EL1
Definition: misc.hh:477
gem5::ArmISA::MISCREG_DTLBIASID
@ MISCREG_DTLBIASID
Definition: misc.hh:337
gem5::ArmISA::MISCREG_TLBINEEDSYNC
@ MISCREG_TLBINEEDSYNC
Definition: misc.hh:97
gem5::ArmISA::MISCREG_ID_ISAR6_EL1
@ MISCREG_ID_ISAR6_EL1
Definition: misc.hh:562
gem5::ArmISA::MISCREG_ELR_EL1
@ MISCREG_ELR_EL1
Definition: misc.hh:619
gem5::ArmISA::MISCREG_AMAIR_EL12
@ MISCREG_AMAIR_EL12
Definition: misc.hh:734
gem5::ArmISA::MISCREG_PMXEVCNTR
@ MISCREG_PMXEVCNTR
Definition: misc.hh:367
gem5::ArmISA::MISCREG_DBGBVR1
@ MISCREG_DBGBVR1
Definition: misc.hh:112
gem5::ArmISA::MISCREG_CNTHP_CTL
@ MISCREG_CNTHP_CTL
Definition: misc.hh:435
gem5::ArmISA::MISCREG_DBGWCR15_EL1
@ MISCREG_DBGWCR15_EL1
Definition: misc.hh:526
gem5::ArmISA::MISCREG_PMCEID0
@ MISCREG_PMCEID0
Definition: misc.hh:362
gem5::ArmISA::MISCREG_ICH_LR9
@ MISCREG_ICH_LR9
Definition: misc.hh:1034
gem5::ArmISA::MISCREG_TPIDR_EL2
@ MISCREG_TPIDR_EL2
Definition: misc.hh:755
gem5::ArmISA::MISCREG_DBGBXVR14
@ MISCREG_DBGBXVR14
Definition: misc.hh:190
gem5::ArmISA::MISCREG_ICC_SRE_NS
@ MISCREG_ICC_SRE_NS
Definition: misc.hh:1008
gem5::ArmISA::MISCREG_DFSR_NS
@ MISCREG_DFSR_NS
Definition: misc.hh:274
gem5::ArmISA::MISCREG_ID_PFR1
@ MISCREG_ID_PFR1
Definition: misc.hh:217
gem5::ArmISA::MISCREG_CNTHP_CVAL_EL2
@ MISCREG_CNTHP_CVAL_EL2
Definition: misc.hh:780
gem5::ArmISA::MISCREG_CNTV_TVAL_EL0
@ MISCREG_CNTV_TVAL_EL0
Definition: misc.hh:766
gem5::ArmISA::MISCREG_ZCR_EL3
@ MISCREG_ZCR_EL3
Definition: misc.hh:1060
gem5::ArmISA::MISCREG_DBGBCR2
@ MISCREG_DBGBCR2
Definition: misc.hh:129
gem5::ArmISA::MISCREG_DBGWCR14_EL1
@ MISCREG_DBGWCR14_EL1
Definition: misc.hh:525
gem5::ArmISA::MISCREG_SPSR_MON
@ MISCREG_SPSR_MON
Definition: misc.hh:70
gem5::ArmISA::MISCREG_DCCIMVAC
@ MISCREG_DCCIMVAC
Definition: misc.hh:322
gem5::ArmISA::MISCREG_L2CTLR_EL1
@ MISCREG_L2CTLR_EL1
Definition: misc.hh:739
gem5::ArmISA::MISCREG_VTCR
@ MISCREG_VTCR
Definition: misc.hh:269
gem5::ArmISA::MISCREG_FPSCR
@ MISCREG_FPSCR
Definition: misc.hh:76
gem5::ArmISA::MISCREG_TTBR0
@ MISCREG_TTBR0
Definition: misc.hh:259
gem5::ArmISA::MISCREG_DBGWVR14_EL1
@ MISCREG_DBGWVR14_EL1
Definition: misc.hh:509
gem5::ArmISA::MISCREG_DBGWVR1
@ MISCREG_DBGWVR1
Definition: misc.hh:144
gem5::ArmISA::MISCREG_DACR
@ MISCREG_DACR
Definition: misc.hh:270
gem5::ArmISA::MISCREG_TTBR0_EL2
@ MISCREG_TTBR0_EL2
Definition: misc.hh:608
gem5::ArmISA::MISCREG_HSCTLR
@ MISCREG_HSCTLR
Definition: misc.hh:251
gem5::ArmISA::MISCREG_SCTLR_NS
@ MISCREG_SCTLR_NS
Definition: misc.hh:241
gem5::ArmISA::MISCREG_DBGWVR2_EL1
@ MISCREG_DBGWVR2_EL1
Definition: misc.hh:497
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1
@ MISCREG_ICC_IGRPEN1_EL1
Definition: misc.hh:881
gem5::ArmISA::MISCREG_ICC_AP0R0
@ MISCREG_ICC_AP0R0
Definition: misc.hh:964
gem5::ArmISA::MISCREG_ACTLR_S
@ MISCREG_ACTLR_S
Definition: misc.hh:245
gem5::ArmISA::MISCREG_BPIMVA
@ MISCREG_BPIMVA
Definition: misc.hh:306
gem5::ArmISA::MISCREG_PMINTENCLR
@ MISCREG_PMINTENCLR
Definition: misc.hh:370
gem5::ArmISA::MISCREG_PMCNTENCLR_EL0
@ MISCREG_PMCNTENCLR_EL0
Definition: misc.hh:719
gem5::ArmISA::MISCREG_IL1DATA2
@ MISCREG_IL1DATA2
Definition: misc.hh:442
gem5::ArmISA::MISCREG_TTBR0_EL1
@ MISCREG_TTBR0_EL1
Definition: misc.hh:602
gem5::ArmISA::MISCREG_ICC_HPPIR0
@ MISCREG_ICC_HPPIR0
Definition: misc.hh:991
gem5::ArmISA::MISCREG_JOSCR
@ MISCREG_JOSCR
Definition: misc.hh:206
gem5::ArmISA::MISCREG_ICIALLU
@ MISCREG_ICIALLU
Definition: misc.hh:302
gem5::ArmISA::MISCREG_IL1DATA3
@ MISCREG_IL1DATA3
Definition: misc.hh:443
gem5::ArmISA::MISCREG_CNTP_CTL_NS
@ MISCREG_CNTP_CTL_NS
Definition: misc.hh:422
gem5::ArmISA::MISCREG_PMEVCNTR5_EL0
@ MISCREG_PMEVCNTR5_EL0
Definition: misc.hh:800
gem5::ArmISA::MISCREG_TLBIALL
@ MISCREG_TLBIALL
Definition: misc.hh:338
gem5::ArmISA::MISCREG_ICC_AP0R2_EL1
@ MISCREG_ICC_AP0R2_EL1
Definition: misc.hh:849
gem5::ArmISA::MISCREG_SCTLR_EL3
@ MISCREG_SCTLR_EL3
Definition: misc.hh:596
gem5::ArmISA::MISCREG_CNTP_TVAL_EL0
@ MISCREG_CNTP_TVAL_EL0
Definition: misc.hh:763
gem5::ArmISA::MISCREG_FPSCR_QC
@ MISCREG_FPSCR_QC
Definition: misc.hh:85
gem5::ArmISA::MISCREG_CURRENTEL
@ MISCREG_CURRENTEL
Definition: misc.hh:623
gem5::ArmISA::MISCREG_DBGBVR13_EL1
@ MISCREG_DBGBVR13_EL1
Definition: misc.hh:476
gem5::ArmISA::MISCREG_DBGWVR6
@ MISCREG_DBGWVR6
Definition: misc.hh:149
gem5::ArmISA::MISCREG_VSESR_EL2
@ MISCREG_VSESR_EL2
Definition: misc.hh:1092
gem5::ArmISA::MISCREG_DBGAUTHSTATUS
@ MISCREG_DBGAUTHSTATUS
Definition: misc.hh:199
gem5::ArmISA::MISCREG_ICC_SGI0R
@ MISCREG_ICC_SGI0R
Definition: misc.hh:1005
gem5::ArmISA::MISCREG_MVFR0_EL1
@ MISCREG_MVFR0_EL1
Definition: misc.hh:563
gem5::ArmISA::MISCREG_ICH_AP0R0_EL2
@ MISCREG_ICH_AP0R0_EL2
Definition: misc.hh:890
gem5::ArmISA::MISCREG_TLBI_VAALE1IS_Xt
@ MISCREG_TLBI_VAALE1IS_Xt
Definition: misc.hh:688
gem5::ArmISA::MISCREG_ID_ISAR1
@ MISCREG_ID_ISAR1
Definition: misc.hh:226
gem5::ArmISA::MISCREG_DBGBCR0
@ MISCREG_DBGBCR0
Definition: misc.hh:127
gem5::ArmISA::MISCREG_ICH_MISR_EL2
@ MISCREG_ICH_MISR_EL2
Definition: misc.hh:900
gem5::ArmISA::MISCREG_TTBCR_S
@ MISCREG_TTBCR_S
Definition: misc.hh:267
gem5::ArmISA::MISCREG_IFSR_S
@ MISCREG_IFSR_S
Definition: misc.hh:278
gem5::ArmISA::MISCREG_PMSWINC
@ MISCREG_PMSWINC
Definition: misc.hh:360
gem5::ArmISA::MISCREG_MVFR1_EL1
@ MISCREG_MVFR1_EL1
Definition: misc.hh:564
gem5::ArmISA::MISCREG_ID_AA64AFR0_EL1
@ MISCREG_ID_AA64AFR0_EL1
Definition: misc.hh:570
gem5::ArmISA::MISCREG_ATS12NSOPR
@ MISCREG_ATS12NSOPR
Definition: misc.hh:313
gem5::ArmISA::MISCREG_MVFR2_EL1
@ MISCREG_MVFR2_EL1
Definition: misc.hh:565
gem5::ArmISA::MISCREG_DBGBCR3
@ MISCREG_DBGBCR3
Definition: misc.hh:130
gem5::ArmISA::MISCREG_OSLSR_EL1
@ MISCREG_OSLSR_EL1
Definition: misc.hh:534
gem5::ArmISA::MISCREG_DBGBCR9_EL1
@ MISCREG_DBGBCR9_EL1
Definition: misc.hh:488
gem5::ArmISA::MISCREG_PMCNTENSET_EL0
@ MISCREG_PMCNTENSET_EL0
Definition: misc.hh:718
gem5::ArmISA::MISCREG_ID_ISAR1_EL1
@ MISCREG_ID_ISAR1_EL1
Definition: misc.hh:557
gem5::ArmISA::MISCREG_AIDR
@ MISCREG_AIDR
Definition: misc.hh:234
gem5::ArmISA::MISCREG_DFSR
@ MISCREG_DFSR
Definition: misc.hh:273
gem5::ArmISA::MISCREG_DBGWVR12_EL1
@ MISCREG_DBGWVR12_EL1
Definition: misc.hh:507
gem5::ArmISA::MISCREG_ICC_AP1R1
@ MISCREG_ICC_AP1R1
Definition: misc.hh:971
gem5::ArmISA::MISCREG_CPUACTLR_EL1
@ MISCREG_CPUACTLR_EL1
Definition: misc.hh:817
gem5::ArmISA::MISCREG_DBGBCR15_EL1
@ MISCREG_DBGBCR15_EL1
Definition: misc.hh:494
gem5::ArmISA::MISCREG_DLR_EL0
@ MISCREG_DLR_EL0
Definition: misc.hh:629
gem5::ArmISA::MISCREG_TLBI_VALE2IS_Xt
@ MISCREG_TLBI_VALE2IS_Xt
Definition: misc.hh:700
gem5::ArmISA::MISCREG_DBGBVR5
@ MISCREG_DBGBVR5
Definition: misc.hh:116
gem5::ArmISA::MISCREG_MVFR0
@ MISCREG_MVFR0
Definition: misc.hh:78
gem5::ArmISA::MISCREG_ICH_LR0
@ MISCREG_ICH_LR0
Definition: misc.hh:1025
gem5::ArmISA::MISCREG_ICH_LRC2
@ MISCREG_ICH_LRC2
Definition: misc.hh:1043
gem5::ArmISA::MISCREG_DBGWVR5
@ MISCREG_DBGWVR5
Definition: misc.hh:148
gem5::ArmISA::MISCREG_ID_MMFR1_EL1
@ MISCREG_ID_MMFR1_EL1
Definition: misc.hh:552
gem5::ArmISA::MISCREG_PRRR_MAIR0_S
@ MISCREG_PRRR_MAIR0_S
Definition: misc.hh:90
gem5::ArmISA::MISCREG_ICC_AP1R3_S
@ MISCREG_ICC_AP1R3_S
Definition: misc.hh:979
gem5::ArmISA::MISCREG_MAIR1_S
@ MISCREG_MAIR1_S
Definition: misc.hh:385
gem5::ArmISA::MISCREG_TLBI_VMALLE1IS
@ MISCREG_TLBI_VMALLE1IS
Definition: misc.hh:683
gem5::ArmISA::MISCREG_DACR32_EL2
@ MISCREG_DACR32_EL2
Definition: misc.hh:616
gem5::ArmISA::MISCREG_ID_AA64ISAR0_EL1
@ MISCREG_ID_AA64ISAR0_EL1
Definition: misc.hh:572
gem5::ArmISA::MISCREG_HIFAR
@ MISCREG_HIFAR
Definition: misc.hh:295
gem5::ArmISA::MISCREG_DBGWVR8
@ MISCREG_DBGWVR8
Definition: misc.hh:151
gem5::ArmISA::MISCREG_ICC_SRE_EL1_S
@ MISCREG_ICC_SRE_EL1_S
Definition: misc.hh:879
gem5::ArmISA::MISCREG_ICH_EISR_EL2
@ MISCREG_ICH_EISR_EL2
Definition: misc.hh:901
gem5::ArmISA::MISCREG_CNTHP_TVAL_EL2
@ MISCREG_CNTHP_TVAL_EL2
Definition: misc.hh:781
gem5::ArmISA::MISCREG_AT_S1E3W_Xt
@ MISCREG_AT_S1E3W_Xt
Definition: misc.hh:682
gem5::ArmISA::MISCREG_ICC_BPR1_EL1
@ MISCREG_ICC_BPR1_EL1
Definition: misc.hh:871
gem5::ArmISA::MISCREG_ICC_AP0R1_EL1
@ MISCREG_ICC_AP0R1_EL1
Definition: misc.hh:848
gem5::ArmISA::MISCREG_TLBI_ALLE2
@ MISCREG_TLBI_ALLE2
Definition: misc.hh:704
gem5::ArmISA::MISCREG_DBGWCR1_EL1
@ MISCREG_DBGWCR1_EL1
Definition: misc.hh:512
gem5::ArmISA::MISCREG_DCISW
@ MISCREG_DCISW
Definition: misc.hh:308
gem5::ArmISA::MISCREG_ID_MMFR2
@ MISCREG_ID_MMFR2
Definition: misc.hh:222
gem5::ArmISA::MISCREG_HMAIR1
@ MISCREG_HMAIR1
Definition: misc.hh:393
gem5::ArmISA::MISCREG_ICH_LR0_EL2
@ MISCREG_ICH_LR0_EL2
Definition: misc.hh:904
gem5::ArmISA::MISCREG_APGAKeyHi_EL1
@ MISCREG_APGAKeyHi_EL1
Definition: misc.hh:834
gem5::ArmISA::MISCREG_VMPIDR_EL2
@ MISCREG_VMPIDR_EL2
Definition: misc.hh:583
gem5::ArmISA::MISCREG_IC_IVAU_Xt
@ MISCREG_IC_IVAU_Xt
Definition: misc.hh:671
gem5::ArmISA::MISCREG_ICC_IAR0_EL1
@ MISCREG_ICC_IAR0_EL1
Definition: misc.hh:843
gem5::ArmISA::MISCREG_ICC_BPR1_EL1_S
@ MISCREG_ICC_BPR1_EL1_S
Definition: misc.hh:873
gem5::ArmISA::MISCREG_DBGBCR8
@ MISCREG_DBGBCR8
Definition: misc.hh:135
gem5::ArmISA::MISCREG_AMAIR0
@ MISCREG_AMAIR0
Definition: misc.hh:386
gem5::ArmISA::MISCREG_VBAR_NS
@ MISCREG_VBAR_NS
Definition: misc.hh:397
gem5::ArmISA::MISCREG_DBGWCR3_EL1
@ MISCREG_DBGWCR3_EL1
Definition: misc.hh:514
gem5::ArmISA::MISCREG_PMOVSCLR_EL0
@ MISCREG_PMOVSCLR_EL0
Definition: misc.hh:720
gem5::ArmISA::MISCREG_ICC_MSRE
@ MISCREG_ICC_MSRE
Definition: misc.hh:1002
gem5::ArmISA::MISCREG_DBGBCR5
@ MISCREG_DBGBCR5
Definition: misc.hh:132
gem5::ArmISA::MISCREG_PMCCNTR
@ MISCREG_PMCCNTR
Definition: misc.hh:364
gem5::ArmISA::MISCREG_ICC_AP1R0_NS
@ MISCREG_ICC_AP1R0_NS
Definition: misc.hh:969
gem5::ArmISA::MISCREG_HSR
@ MISCREG_HSR
Definition: misc.hh:287
gem5::ArmISA::MISCREG_ICC_AP1R2_EL1
@ MISCREG_ICC_AP1R2_EL1
Definition: misc.hh:857
gem5::ArmISA::MISCREG_TPIDRURO
@ MISCREG_TPIDRURO
Definition: misc.hh:410
gem5::ArmISA::MISCREG_ICH_LRC1
@ MISCREG_ICH_LRC1
Definition: misc.hh:1042
gem5::ArmISA::MISCREG_HCR2
@ MISCREG_HCR2
Definition: misc.hh:254
gem5::ArmISA::MISCREG_TLBI_VALE1IS_Xt
@ MISCREG_TLBI_VALE1IS_Xt
Definition: misc.hh:687
gem5::ArmISA::MISCREG_DSPSR_EL0
@ MISCREG_DSPSR_EL0
Definition: misc.hh:628
gem5::ArmISA::MISCREG_ICC_HPPIR1_EL1
@ MISCREG_ICC_HPPIR1_EL1
Definition: misc.hh:870
gem5::ArmISA::MISCREG_L2MERRSR_EL1
@ MISCREG_L2MERRSR_EL1
Definition: misc.hh:820
gem5::ArmISA::MISCREG_ICC_AP1R3_EL1
@ MISCREG_ICC_AP1R3_EL1
Definition: misc.hh:860
gem5::ArmISA::MISCREG_CNTHP_CVAL
@ MISCREG_CNTHP_CVAL
Definition: misc.hh:436
gem5::ArmISA::MISCREG_TTBR0_NS
@ MISCREG_TTBR0_NS
Definition: misc.hh:260
gem5::ArmISA::MISCREG_ICC_RPR
@ MISCREG_ICC_RPR
Definition: misc.hh:1004
gem5::ArmISA::MISCREG_FAR_EL2
@ MISCREG_FAR_EL2
Definition: misc.hh:656
gem5::ArmISA::MISCREG_CNTHVS_CTL_EL2
@ MISCREG_CNTHVS_CTL_EL2
Definition: misc.hh:789
gem5::ArmISA::MISCREG_DBGBCR7
@ MISCREG_DBGBCR7
Definition: misc.hh:134
gem5::ArmISA::MISCREG_DBGWVR3
@ MISCREG_DBGWVR3
Definition: misc.hh:146
gem5::ArmISA::MISCREG_ICC_ASGI1R
@ MISCREG_ICC_ASGI1R
Definition: misc.hh:980
gem5::ArmISA::MISCREG_ICH_AP1R0_EL2
@ MISCREG_ICH_AP1R0_EL2
Definition: misc.hh:894
gem5::ArmISA::MISCREG_PMEVCNTR3_EL0
@ MISCREG_PMEVCNTR3_EL0
Definition: misc.hh:798
gem5::ArmISA::MISCREG_FPSCR_EXC
@ MISCREG_FPSCR_EXC
Definition: misc.hh:84
gem5::ArmISA::MISCREG_CNTV_TVAL_EL02
@ MISCREG_CNTV_TVAL_EL02
Definition: misc.hh:772
gem5::ArmISA::MISCREG_RVBAR_EL3
@ MISCREG_RVBAR_EL3
Definition: misc.hh:748
gem5::ArmISA::MISCREG_ICH_VTR_EL2
@ MISCREG_ICH_VTR_EL2
Definition: misc.hh:899
gem5::ArmISA::MISCREG_TLBI_VALE3_Xt
@ MISCREG_TLBI_VALE3_Xt
Definition: misc.hh:714
gem5::ArmISA::MISCREG_TLBI_ASIDE1_Xt
@ MISCREG_TLBI_ASIDE1_Xt
Definition: misc.hh:691
gem5::ArmISA::MISCREG_DBGBCR10_EL1
@ MISCREG_DBGBCR10_EL1
Definition: misc.hh:489
gem5::ArmISA::MISCREG_OSDTRRX_EL1
@ MISCREG_OSDTRRX_EL1
Definition: misc.hh:459
gem5::ArmISA::MISCREG_AT_S1E0R_Xt
@ MISCREG_AT_S1E0R_Xt
Definition: misc.hh:666
gem5::ArmISA::MISCREG_MDDTRTX_EL0
@ MISCREG_MDDTRTX_EL0
Definition: misc.hh:529
gem5::ArmISA::MISCREG_ICC_SRE_S
@ MISCREG_ICC_SRE_S
Definition: misc.hh:1009
gem5::ArmISA::MISCREG_DBGWVR6_EL1
@ MISCREG_DBGWVR6_EL1
Definition: misc.hh:501
gem5::ArmISA::MISCREG_TLBI_IPAS2LE1_Xt
@ MISCREG_TLBI_IPAS2LE1_Xt
Definition: misc.hh:703
gem5::ArmISA::MISCREG_ID_ISAR3
@ MISCREG_ID_ISAR3
Definition: misc.hh:228
gem5::ArmISA::MISCREG_CNTHP_CTL_EL2
@ MISCREG_CNTHP_CTL_EL2
Definition: misc.hh:779
gem5::ArmISA::MISCREG_ICH_LR14
@ MISCREG_ICH_LR14
Definition: misc.hh:1039
gem5::ArmISA::MISCREG_IMPDEF_UNIMPL
@ MISCREG_IMPDEF_UNIMPL
Definition: misc.hh:1080
gem5::ArmISA::MISCREG_ICH_LRC10
@ MISCREG_ICH_LRC10
Definition: misc.hh:1051
gem5::ArmISA::MISCREG_MVBAR
@ MISCREG_MVBAR
Definition: misc.hh:399
gem5::ArmISA::MISCREG_DBGBCR6
@ MISCREG_DBGBCR6
Definition: misc.hh:133
gem5::ArmISA::MISCREG_DBGWVR8_EL1
@ MISCREG_DBGWVR8_EL1
Definition: misc.hh:503
gem5::ArmISA::MISCREG_ERXFR_EL1
@ MISCREG_ERXFR_EL1
Definition: misc.hh:1085
gem5::ArmISA::MISCREG_PMCR_EL0
@ MISCREG_PMCR_EL0
Definition: misc.hh:717
gem5::ArmISA::MISCREG_PAR
@ MISCREG_PAR
Definition: misc.hh:299
gem5::ArmISA::MISCREG_CBAR
@ MISCREG_CBAR
Definition: misc.hh:451
gem5::ArmISA::MISCREG_CONTEXTIDR_EL12
@ MISCREG_CONTEXTIDR_EL12
Definition: misc.hh:751
gem5::ArmISA::MISCREG_CPTR_EL3
@ MISCREG_CPTR_EL3
Definition: misc.hh:600
gem5::ArmISA::MISCREG_ESR_EL2
@ MISCREG_ESR_EL2
Definition: misc.hh:649
gem5::ArmISA::MISCREG_HADFSR
@ MISCREG_HADFSR
Definition: misc.hh:285
gem5::ArmISA::MISCREG_SPSR_FIQ_AA64
@ MISCREG_SPSR_FIQ_AA64
Definition: misc.hh:636
gem5::ArmISA::MISCREG_IC_IALLUIS
@ MISCREG_IC_IALLUIS
Definition: misc.hh:659
gem5::ArmISA::MISCREG_NMRR_MAIR1_NS
@ MISCREG_NMRR_MAIR1_NS
Definition: misc.hh:92
gem5::ArmISA::MISCREG_ICH_LR4
@ MISCREG_ICH_LR4
Definition: misc.hh:1029
gem5::ArmISA::MISCREG_ID_PFR0
@ MISCREG_ID_PFR0
Definition: misc.hh:216
gem5::ArmISA::MISCREG_CLIDR_EL1
@ MISCREG_CLIDR_EL1
Definition: misc.hh:577
gem5::ArmISA::MISCREG_ICH_LRC4
@ MISCREG_ICH_LRC4
Definition: misc.hh:1045
gem5::ArmISA::MISCREG_DBGBVR6
@ MISCREG_DBGBVR6
Definition: misc.hh:117
gem5::ArmISA::MISCREG_NMRR_S
@ MISCREG_NMRR_S
Definition: misc.hh:382
gem5::ArmISA::MISCREG_DCCMVAC
@ MISCREG_DCCMVAC
Definition: misc.hh:317
gem5::ArmISA::MISCREG_L2ECTLR_EL1
@ MISCREG_L2ECTLR_EL1
Definition: misc.hh:740
gem5::ArmISA::MISCREG_ICC_BPR1
@ MISCREG_ICC_BPR1
Definition: misc.hh:982
gem5::ArmISA::MISCREG_ICH_LR11
@ MISCREG_ICH_LR11
Definition: misc.hh:1036
gem5::ArmISA::MISCREG_IFAR_S
@ MISCREG_IFAR_S
Definition: misc.hh:293
gem5::ArmISA::MISCREG_ICH_AP0R2
@ MISCREG_ICH_AP0R2
Definition: misc.hh:1013
gem5::ArmISA::MISCREG_ID_MMFR3_EL1
@ MISCREG_ID_MMFR3_EL1
Definition: misc.hh:554
gem5::ArmISA::MISCREG_SPSR_IRQ_AA64
@ MISCREG_SPSR_IRQ_AA64
Definition: misc.hh:633
gem5::ArmISA::MISCREG_TLBI_VALE1_Xt
@ MISCREG_TLBI_VALE1_Xt
Definition: misc.hh:693
gem5::ArmISA::MISCREG_ID_MMFR4
@ MISCREG_ID_MMFR4
Definition: misc.hh:224
gem5::ArmISA::MISCREG_DBGBXVR1
@ MISCREG_DBGBXVR1
Definition: misc.hh:177
gem5::ArmISA::MISCREG_AFSR1_EL1
@ MISCREG_AFSR1_EL1
Definition: misc.hh:642
gem5::ArmISA::MISCREG_CNTP_CVAL_S
@ MISCREG_CNTP_CVAL_S
Definition: misc.hh:426
gem5::ArmISA::MISCREG_ICH_LR13
@ MISCREG_ICH_LR13
Definition: misc.hh:1038
gem5::ArmISA::MISCREG_TPIDRURO_S
@ MISCREG_TPIDRURO_S
Definition: misc.hh:412
gem5::ArmISA::MISCREG_DBGBVR4_EL1
@ MISCREG_DBGBVR4_EL1
Definition: misc.hh:467
gem5::ArmISA::MISCREG_VSTTBR_EL2
@ MISCREG_VSTTBR_EL2
Definition: misc.hh:612
gem5::ArmISA::MISCREG_CNTKCTL
@ MISCREG_CNTKCTL
Definition: misc.hh:433
gem5::ArmISA::MISCREG_PRRR_MAIR0_NS
@ MISCREG_PRRR_MAIR0_NS
Definition: misc.hh:89
gem5::ArmISA::MISCREG_DBGWVR4
@ MISCREG_DBGWVR4
Definition: misc.hh:147
gem5::ArmISA::MISCREG_CONTEXTIDR_S
@ MISCREG_CONTEXTIDR_S
Definition: misc.hh:406
gem5::ArmISA::MISCREG_CNTHV_CVAL_EL2
@ MISCREG_CNTHV_CVAL_EL2
Definition: misc.hh:787
gem5::ArmISA::MISCREG_LOCKADDR
@ MISCREG_LOCKADDR
Definition: misc.hh:86
gem5::ArmISA::MISCREG_PMCEID1_EL0
@ MISCREG_PMCEID1_EL0
Definition: misc.hh:724
gem5::ArmISA::MISCREG_TPIDRURW_NS
@ MISCREG_TPIDRURW_NS
Definition: misc.hh:408
gem5::ArmISA::MISCREG_CTR_EL0
@ MISCREG_CTR_EL0
Definition: misc.hh:580
gem5::ArmISA::MISCREG_CNTFRQ_EL0
@ MISCREG_CNTFRQ_EL0
Definition: misc.hh:758
gem5::ArmISA::MISCREG_ID_AFR0
@ MISCREG_ID_AFR0
Definition: misc.hh:219
gem5::ArmISA::MISCREG_ICC_CTLR_EL1_S
@ MISCREG_ICC_CTLR_EL1_S
Definition: misc.hh:876
gem5::ArmISA::MISCREG_DBGAUTHSTATUS_EL1
@ MISCREG_DBGAUTHSTATUS_EL1
Definition: misc.hh:539
gem5::ArmISA::MISCREG_DBGBCR1
@ MISCREG_DBGBCR1
Definition: misc.hh:128
gem5::ArmISA::MISCREG_FPEXC32_EL2
@ MISCREG_FPEXC32_EL2
Definition: misc.hh:650
gem5::ArmISA::MISCREG_TPIDRURO_NS
@ MISCREG_TPIDRURO_NS
Definition: misc.hh:411
gem5::ArmISA::MISCREG_DBGBCR13
@ MISCREG_DBGBCR13
Definition: misc.hh:140
gem5::ArmISA::MISCREG_MDDTR_EL0
@ MISCREG_MDDTR_EL0
Definition: misc.hh:528
gem5::ArmISA::MISCREG_TLBIMVAA
@ MISCREG_TLBIMVAA
Definition: misc.hh:341
gem5::ArmISA::MISCREG_TLBI_VAE1_Xt
@ MISCREG_TLBI_VAE1_Xt
Definition: misc.hh:690
gem5::ArmISA::MISCREG_ICC_AP1R1_NS
@ MISCREG_ICC_AP1R1_NS
Definition: misc.hh:972
gem5::ArmISA::MISCREG_PMEVCNTR1_EL0
@ MISCREG_PMEVCNTR1_EL0
Definition: misc.hh:796
gem5::ArmISA::MISCREG_SPSR
@ MISCREG_SPSR
Definition: misc.hh:66
gem5::ArmISA::MISCREG_TPIDRPRW
@ MISCREG_TPIDRPRW
Definition: misc.hh:413
gem5::ArmISA::MISCREG_ACTLR
@ MISCREG_ACTLR
Definition: misc.hh:243
gem5::ArmISA::MISCREG_DBGBVR12
@ MISCREG_DBGBVR12
Definition: misc.hh:123
gem5::ArmISA::MISCREG_VTTBR_EL2
@ MISCREG_VTTBR_EL2
Definition: misc.hh:610
gem5::ArmISA::MISCREG_DBGWCR7
@ MISCREG_DBGWCR7
Definition: misc.hh:166
gem5::ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR
@ MISCREG_PMXEVTYPER_PMCCFILTR
Definition: misc.hh:94
gem5::ArmISA::MISCREG_MAIR1_NS
@ MISCREG_MAIR1_NS
Definition: misc.hh:384
gem5::ArmISA::MISCREG_ICC_HPPIR1
@ MISCREG_ICC_HPPIR1
Definition: misc.hh:992
gem5::ArmISA::MISCREG_VDISR_EL2
@ MISCREG_VDISR_EL2
Definition: misc.hh:1093
gem5::ArmISA::MISCREG_DBGBVR15
@ MISCREG_DBGBVR15
Definition: misc.hh:126
gem5::ArmISA::MISCREG_DBGBVR4
@ MISCREG_DBGBVR4
Definition: misc.hh:115
gem5::ArmISA::MISCREG_ID_AA64PFR1_EL1
@ MISCREG_ID_AA64PFR1_EL1
Definition: misc.hh:567
gem5::ArmISA::MISCREG_RAMINDEX
@ MISCREG_RAMINDEX
Definition: misc.hh:449
gem5::ArmISA::MISCREG_HSTR
@ MISCREG_HSTR
Definition: misc.hh:257
gem5::ArmISA::MISCREG_MDCR_EL3
@ MISCREG_MDCR_EL3
Definition: misc.hh:601
gem5::ArmISA::MISCREG_AFSR0_EL2
@ MISCREG_AFSR0_EL2
Definition: misc.hh:647
gem5::ArmISA::MISCREG_ID_ISAR2
@ MISCREG_ID_ISAR2
Definition: misc.hh:227
gem5::ArmISA::MISCREG_SPSR_FIQ
@ MISCREG_SPSR_FIQ
Definition: misc.hh:67
gem5::ArmISA::MISCREG_PRRR_S
@ MISCREG_PRRR_S
Definition: misc.hh:376
gem5::ArmISA::MISCREG_ICC_AP1R3_NS
@ MISCREG_ICC_AP1R3_NS
Definition: misc.hh:978
gem5::ArmISA::MISCREG_CNTV_CVAL_EL0
@ MISCREG_CNTV_CVAL_EL0
Definition: misc.hh:765
gem5::ArmISA::MISCREG_ZCR_EL12
@ MISCREG_ZCR_EL12
Definition: misc.hh:1062
gem5::ArmISA::MISCREG_DBGWCR13
@ MISCREG_DBGWCR13
Definition: misc.hh:172
gem5::ArmISA::MISCREG_SP_EL1
@ MISCREG_SP_EL1
Definition: misc.hh:632
gem5::ArmISA::MISCREG_ATS1CUW
@ MISCREG_ATS1CUW
Definition: misc.hh:312
gem5::ArmISA::MISCREG_MAIR0
@ MISCREG_MAIR0
Definition: misc.hh:377
gem5::ArmISA::MISCREG_PMOVSSET_EL0
@ MISCREG_PMOVSSET_EL0
Definition: misc.hh:730
gem5::ArmISA::tvm
Bitfield< 26 > tvm
Definition: misc_types.hh:264
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:73
gem5::ArmISA::MISCREG_USR_S_RD
@ MISCREG_USR_S_RD
Definition: misc.hh:1127
gem5::ArmISA::MISCREG_BANKED_CHILD
@ MISCREG_BANKED_CHILD
Definition: misc.hh:1119
gem5::ArmISA::MISCREG_MON_NS1_RD
@ MISCREG_MON_NS1_RD
Definition: misc.hh:1143
gem5::ArmISA::MISCREG_PRI_NS_WR
@ MISCREG_PRI_NS_WR
Definition: misc.hh:1131
gem5::ArmISA::MISCREG_PRI_S_WR
@ MISCREG_PRI_S_WR
Definition: misc.hh:1133
gem5::ArmISA::MISCREG_MON_NS0_RD
@ MISCREG_MON_NS0_RD
Definition: misc.hh:1140
gem5::ArmISA::MISCREG_BANKED
@ MISCREG_BANKED
Definition: misc.hh:1113
gem5::ArmISA::MISCREG_WARN_NOT_FAIL
@ MISCREG_WARN_NOT_FAIL
Definition: misc.hh:1108
gem5::ArmISA::MISCREG_MON_NS1_WR
@ MISCREG_MON_NS1_WR
Definition: misc.hh:1144
gem5::ArmISA::MISCREG_HYP_NS_WR
@ MISCREG_HYP_NS_WR
Definition: misc.hh:1136
gem5::ArmISA::MISCREG_PRI_S_RD
@ MISCREG_PRI_S_RD
Definition: misc.hh:1132
gem5::ArmISA::MISCREG_PRI_NS_RD
@ MISCREG_PRI_NS_RD
Definition: misc.hh:1130
gem5::ArmISA::MISCREG_USR_NS_WR
@ MISCREG_USR_NS_WR
Definition: misc.hh:1126
gem5::ArmISA::MISCREG_USR_S_WR
@ MISCREG_USR_S_WR
Definition: misc.hh:1128
gem5::ArmISA::MISCREG_USR_NS_RD
@ MISCREG_USR_NS_RD
Definition: misc.hh:1125
gem5::ArmISA::MISCREG_MON_NS0_WR
@ MISCREG_MON_NS0_WR
Definition: misc.hh:1141
gem5::ArmISA::MISCREG_HYP_NS_RD
@ MISCREG_HYP_NS_RD
Definition: misc.hh:1135
gem5::ArmISA::decodeCP14Reg
MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
Definition: misc.cc:519
gem5::ArmISA::condGenericTimerSystemAccessTrapEL1
bool condGenericTimerSystemAccessTrapEL1(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:890
gem5::ArmISA::unflattenMiscReg
int unflattenMiscReg(int reg)
Definition: misc.cc:722
gem5::ArmISA::snsBankedIndex
int snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
Definition: misc.cc:670
gem5::ArmISA::canWriteCoprocReg
std::tuple< bool, bool > canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
Check for permission to write coprocessor registers.
Definition: misc.cc:611
gem5::ArmISA::snsBankedIndex64
int snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc)
Definition: misc.cc:688
gem5::ArmISA::decodeCP15Reg64
MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1)
Definition: misc.cc:552
gem5::ArmISA::lookUpMiscReg
std::vector< struct MiscRegLUTEntry > lookUpMiscReg(NUM_MISCREGS)
Definition: misc.hh:1576
gem5::ArmISA::defaultFaultE2H_EL2
static Fault defaultFaultE2H_EL2(const MiscRegLUTEntry &entry, ThreadContext *tc, const MiscRegOp64 &inst)
Definition: misc.cc:2032
gem5::ArmISA::canReadCoprocReg
std::tuple< bool, bool > canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
Check for permission to read coprocessor registers.
Definition: misc.cc:564
gem5::ArmISA::defaultFaultE2H_EL3
static Fault defaultFaultE2H_EL3(const MiscRegLUTEntry &entry, ThreadContext *tc, const MiscRegOp64 &inst)
Definition: misc.cc:2044
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:776
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:38
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:253
gem5::ArmISA::MiscRegLUTEntry
MiscReg metadata.
Definition: misc.hh:1151
gem5::ArmISA::MiscRegLUTEntry::defaultFault
static Fault defaultFault(const MiscRegLUTEntry &entry, ThreadContext *tc, const MiscRegOp64 &inst)
Definition: misc.cc:2021
gem5::ArmISA::MiscRegLUTEntry::faultRead
std::array< FaultCB, EL3+1 > faultRead
Definition: misc.hh:1166
gem5::ArmISA::MiscRegLUTEntry::info
std::bitset< NUM_MISCREG_INFOS > info
Definition: misc.hh:1159
gem5::ArmISA::MiscRegLUTEntry::faultWrite
std::array< FaultCB, EL3+1 > faultWrite
Definition: misc.hh:1167
gem5::ArmISA::MiscRegLUTEntry::checkFault
Fault checkFault(ThreadContext *tc, const MiscRegOp64 &inst, ExceptionLevel el)
Definition: misc.cc:2012
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