gem5  v21.2.1.1
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gem5::ArmISA::MMU Class Reference

#include <mmu.hh>

Inheritance diagram for gem5::ArmISA::MMU:
gem5::BaseMMU gem5::SimObject gem5::EventManager gem5::Serializable gem5::Drainable gem5::statistics::Group gem5::Named

Classes

struct  CachedState
 
struct  Stats
 

Public Types

enum  ArmFlags {
  AlignmentMask = 0x7, AlignByte = 0x0, AlignHalfWord = 0x1, AlignWord = 0x2,
  AlignDoubleWord = 0x3, AlignQuadWord = 0x4, AlignOctWord = 0x5, AllowUnaligned = 0x8,
  UserMode = 0x10
}
 
enum  ArmTranslationType {
  NormalTran = 0, S1CTran = 0x1, HypMode = 0x2, S1S2NsTran = 0x4,
  S1E0Tran = 0x8, S1E1Tran = 0x10, S1E2Tran = 0x20, S1E3Tran = 0x40,
  S12E0Tran = 0x80, S12E1Tran = 0x100
}
 
- Public Types inherited from gem5::BaseMMU
enum  Mode { Read, Write, Execute }
 
- Public Types inherited from gem5::SimObject
typedef SimObjectParams Params
 

Public Member Functions

TranslationGenPtr translateFunctional (Addr start, Addr size, ThreadContext *tc, Mode mode, Request::Flags flags) override
 Returns a translation generator for a region of virtual addresses, instead of directly translating a specific address. More...
 
 MMU (const ArmMMUParams &p)
 
void init () override
 init() is called after all C++ SimObjects have been created and all ports are connected. More...
 
bool translateFunctional (ThreadContext *tc, Addr vaddr, Addr &paddr)
 Do a functional lookup on the TLB (for debugging) and don't modify any internal state. More...
 
Fault translateFunctional (const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override
 
Fault translateFunctional (const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, ArmTranslationType tran_type)
 Do a functional lookup on the TLB (for checker cpu) that behaves like a normal lookup without modifying any page table state. More...
 
Fault translateFunctional (const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, ArmTranslationType tran_type, bool stage2)
 
Fault translateAtomic (const RequestPtr &req, ThreadContext *tc, Mode mode) override
 
Fault translateAtomic (const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, ArmTranslationType tran_type, bool stage2)
 
Fault translateAtomic (const RequestPtr &req, ThreadContext *tc, Mode mode, ArmTranslationType tran_type)
 
void translateTiming (const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode) override
 
void translateTiming (const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode, bool stage2)
 
void translateTiming (const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, ArmTranslationType tran_type, bool stage2)
 
Fault translateMmuOff (ThreadContext *tc, const RequestPtr &req, Mode mode, ArmTranslationType tran_type, Addr vaddr, bool long_desc_format, CachedState &state)
 
Fault translateMmuOn (ThreadContext *tc, const RequestPtr &req, Mode mode, Translation *translation, bool &delay, bool timing, bool functional, Addr vaddr, ArmFault::TranMethod tranMethod, CachedState &state)
 
Fault translateFs (const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing, ArmTranslationType tran_type, bool functional, CachedState &state)
 
Fault translateSe (const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing, CachedState &state)
 
Fault translateComplete (const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, ArmTranslationType tran_type, bool call_from_s2)
 
Fault translateComplete (const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, ArmTranslationType tran_type, bool call_from_s2, CachedState &state)
 
Fault finalizePhysical (const RequestPtr &req, ThreadContext *tc, Mode mode) const override
 
void drainResume () override
 Resume execution after a successful drain. More...
 
void takeOverFrom (BaseMMU *old_mmu) override
 
void invalidateMiscReg ()
 
template<typename OP >
void flush (const OP &tlbi_op)
 
template<typename OP >
void flushStage1 (const OP &tlbi_op)
 
template<typename OP >
void flushStage2 (const OP &tlbi_op)
 
template<typename OP >
void iflush (const OP &tlbi_op)
 
template<typename OP >
void dflush (const OP &tlbi_op)
 
void flushAll () override
 
uint64_t getAttr () const
 
void setAttr (uint64_t attr)
 Accessor functions for memory attributes for last accessed TLB entry. More...
 
const ArmReleaserelease () const
 
bool hasWalkCache () const
 
TlbEntrylookup (Addr vpn, uint16_t asn, vmid_t vmid, bool hyp, bool secure, bool functional, bool ignore_asn, ExceptionLevel target_el, bool in_host, bool stage2, BaseMMU::Mode mode)
 Lookup an entry in the TLB. More...
 
Fault getTE (TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, bool is_secure, ArmTranslationType tran_type, bool stage2)
 
Fault getTE (TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, bool is_secure, ArmTranslationType tran_type, CachedState &state)
 
Fault getResultTe (TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, TlbEntry *mergeTe, CachedState &state)
 
Fault checkPermissions (TlbEntry *te, const RequestPtr &req, Mode mode, bool stage2)
 
Fault checkPermissions (TlbEntry *te, const RequestPtr &req, Mode mode, CachedState &state)
 
Fault checkPermissions64 (TlbEntry *te, const RequestPtr &req, Mode mode, ThreadContext *tc, bool stage2)
 
Fault checkPermissions64 (TlbEntry *te, const RequestPtr &req, Mode mode, ThreadContext *tc, CachedState &state)
 
void setTestInterface (SimObject *ti)
 
Fault testTranslation (const RequestPtr &req, Mode mode, TlbEntry::DomainType domain, CachedState &state)
 
Fault testWalk (Addr pa, Addr size, Addr va, bool is_secure, Mode mode, TlbEntry::DomainType domain, LookupLevel lookup_level, bool stage2)
 
Fault testWalk (Addr pa, Addr size, Addr va, bool is_secure, Mode mode, TlbEntry::DomainType domain, LookupLevel lookup_level, CachedState &state)
 
virtual Fault translateFunctional (const RequestPtr &req, ThreadContext *tc, Mode mode)
 
virtual TranslationGenPtr translateFunctional (Addr start, Addr size, ThreadContext *tc, BaseMMU::Mode mode, Request::Flags flags)=0
 Returns a translation generator for a region of virtual addresses, instead of directly translating a specific address. More...
 
- Public Member Functions inherited from gem5::BaseMMU
void init () override
 Called at init time, this method is traversing the TLB hierarchy and pupulating the instruction/data/unified containers accordingly. More...
 
void demapPage (Addr vaddr, uint64_t asn)
 
- Public Member Functions inherited from gem5::SimObject
const Paramsparams () const
 
 SimObject (const Params &p)
 
virtual ~SimObject ()
 
virtual void loadState (CheckpointIn &cp)
 loadState() is called on each SimObject when restoring from a checkpoint. More...
 
virtual void initState ()
 initState() is called on each SimObject when not restoring from a checkpoint. More...
 
virtual void regProbePoints ()
 Register probe points for this object. More...
 
virtual void regProbeListeners ()
 Register probe listeners for this object. More...
 
ProbeManagergetProbeManager ()
 Get the probe manager for this object. More...
 
virtual PortgetPort (const std::string &if_name, PortID idx=InvalidPortID)
 Get a port with a given name and index. More...
 
virtual void startup ()
 startup() is the final initialization call before simulation. More...
 
DrainState drain () override
 Provide a default implementation of the drain interface for objects that don't need draining. More...
 
virtual void memWriteback ()
 Write back dirty buffers to memory using functional writes. More...
 
virtual void memInvalidate ()
 Invalidate the contents of memory buffers. More...
 
void serialize (CheckpointOut &cp) const override
 Serialize an object. More...
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
 
- Public Member Functions inherited from gem5::EventManager
EventQueueeventQueue () const
 
void schedule (Event &event, Tick when)
 
void deschedule (Event &event)
 
void reschedule (Event &event, Tick when, bool always=false)
 
void schedule (Event *event, Tick when)
 
void deschedule (Event *event)
 
void reschedule (Event *event, Tick when, bool always=false)
 
void wakeupEventQueue (Tick when=(Tick) -1)
 This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...
 
void setCurTick (Tick newVal)
 
 EventManager (EventManager &em)
 Event manger manages events in the event queue. More...
 
 EventManager (EventManager *em)
 
 EventManager (EventQueue *eq)
 
- Public Member Functions inherited from gem5::Serializable
 Serializable ()
 
virtual ~Serializable ()
 
void serializeSection (CheckpointOut &cp, const char *name) const
 Serialize an object into a new section. More...
 
void serializeSection (CheckpointOut &cp, const std::string &name) const
 
void unserializeSection (CheckpointIn &cp, const char *name)
 Unserialize an a child object. More...
 
void unserializeSection (CheckpointIn &cp, const std::string &name)
 
- Public Member Functions inherited from gem5::Drainable
DrainState drainState () const
 Return the current drain state of an object. More...
 
virtual void notifyFork ()
 Notify a child process of a fork. More...
 
- Public Member Functions inherited from gem5::statistics::Group
 Group (Group *parent, const char *name=nullptr)
 Construct a new statistics group. More...
 
virtual ~Group ()
 
virtual void regStats ()
 Callback to set stat parameters. More...
 
virtual void resetStats ()
 Callback to reset stats. More...
 
virtual void preDumpStats ()
 Callback before stats are dumped. More...
 
void addStat (statistics::Info *info)
 Register a stat with this group. More...
 
const std::map< std::string, Group * > & getStatGroups () const
 Get all child groups associated with this object. More...
 
const std::vector< Info * > & getStats () const
 Get all stats associated with this object. More...
 
void addStatGroup (const char *name, Group *block)
 Add a stat block as a child of this block. More...
 
const InforesolveStat (std::string name) const
 Resolve a stat by its name within this group. More...
 
void mergeStatGroup (Group *block)
 Merge the contents (stats & children) of a block to this block. More...
 
 Group ()=delete
 
 Group (const Group &)=delete
 
Groupoperator= (const Group &)=delete
 
- Public Member Functions inherited from gem5::Named
 Named (const std::string &name_)
 
virtual ~Named ()=default
 
virtual std::string name () const
 

Static Public Member Functions

static ExceptionLevel tranTypeEL (CPSR cpsr, ArmTranslationType type)
 Determine the EL to use for the purpose of a translation given a specific translation type. More...
 
- Static Public Member Functions inherited from gem5::SimObject
static void serializeAll (const std::string &cpt_dir)
 Create a checkpoint by serializing all SimObjects in the system. More...
 
static SimObjectfind (const char *name)
 Find the SimObject with the given name and return a pointer to it. More...
 
static void setSimObjectResolver (SimObjectResolver *resolver)
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
 
static SimObjectResolvergetSimObjectResolver ()
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
 
- Static Public Member Functions inherited from gem5::Serializable
static const std::string & currentSection ()
 Gets the fully-qualified name of the active section. More...
 
static void generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
 Generate a checkpoint file so that the serialization can be routed to it. More...
 

Public Attributes

TlbTestInterfacetest
 
CachedState s1State
 
CachedState s2State
 
- Public Attributes inherited from gem5::BaseMMU
BaseTLBdtb
 
BaseTLBitb
 

Protected Types

using LookupLevel = enums::ArmLookupLevel
 
- Protected Types inherited from gem5::BaseMMU
typedef BaseMMUParams Params
 

Protected Member Functions

ArmISA::TLBgetDTBPtr () const
 
ArmISA::TLBgetITBPtr () const
 
TLBgetTlb (BaseMMU::Mode mode, bool stage2) const
 
TableWalkergetTableWalker (BaseMMU::Mode mode, bool stage2) const
 
bool checkPAN (ThreadContext *tc, uint8_t ap, const RequestPtr &req, Mode mode, const bool is_priv, CachedState &state)
 
bool faultPAN (ThreadContext *tc, uint8_t ap, const RequestPtr &req, Mode mode, const bool is_priv, CachedState &state)
 
std::pair< bool, bool > s1PermBits64 (TlbEntry *te, const RequestPtr &req, Mode mode, ThreadContext *tc, CachedState &state, bool r, bool w, bool x)
 
std::pair< bool, bool > s2PermBits64 (TlbEntry *te, const RequestPtr &req, Mode mode, ThreadContext *tc, CachedState &state, bool r, bool w, bool x)
 
bool checkWalkCache () const
 
bool isCompleteTranslation (TlbEntry *te) const
 
CachedStateupdateMiscReg (ThreadContext *tc, ArmTranslationType tran_type, bool stage2)
 
- Protected Member Functions inherited from gem5::BaseMMU
 BaseMMU (const Params &p)
 
BaseTLBgetTlb (Mode mode) const
 
- Protected Member Functions inherited from gem5::Drainable
 Drainable ()
 
virtual ~Drainable ()
 
void signalDrainDone () const
 Signal that an object is drained. More...
 

Protected Attributes

TLBitbStage2
 
TLBdtbStage2
 
TableWalkeritbWalker
 
TableWalkerdtbWalker
 
TableWalkeritbStage2Walker
 
TableWalkerdtbStage2Walker
 
ContextID miscRegContext
 
uint64_t _attr
 
const ArmRelease_release
 
bool haveLargeAsid64
 
uint8_t physAddrRange
 
AddrRange m5opRange
 
bool _hasWalkCache
 
gem5::ArmISA::MMU::Stats stats
 
- Protected Attributes inherited from gem5::BaseMMU
std::set< BaseTLB * > instruction
 It is possible from the MMU to traverse the entire hierarchy of TLBs, starting from the DTB and ITB (generally speaking from the first level) up to the last level via the nextLevel pointer. More...
 
std::set< BaseTLB * > data
 
std::set< BaseTLB * > unified
 
- Protected Attributes inherited from gem5::SimObject
const SimObjectParams & _params
 Cached copy of the object parameters. More...
 
- Protected Attributes inherited from gem5::EventManager
EventQueueeventq
 A pointer to this object's event queue. More...
 

Detailed Description

Definition at line 59 of file mmu.hh.

Member Typedef Documentation

◆ LookupLevel

using gem5::ArmISA::MMU::LookupLevel = enums::ArmLookupLevel
protected

Definition at line 62 of file mmu.hh.

Member Enumeration Documentation

◆ ArmFlags

Enumerator
AlignmentMask 
AlignByte 
AlignHalfWord 
AlignWord 
AlignDoubleWord 
AlignQuadWord 
AlignOctWord 
AllowUnaligned 
UserMode 

Definition at line 97 of file mmu.hh.

◆ ArmTranslationType

Enumerator
NormalTran 
S1CTran 
HypMode 
S1S2NsTran 
S1E0Tran 
S1E1Tran 
S1E2Tran 
S1E3Tran 
S12E0Tran 
S12E1Tran 

Definition at line 113 of file mmu.hh.

Constructor & Destructor Documentation

◆ MMU()

gem5::MMU::MMU ( const ArmMMUParams &  p)

Member Function Documentation

◆ checkPAN()

bool gem5::MMU::checkPAN ( ThreadContext tc,
uint8_t  ap,
const RequestPtr req,
Mode  mode,
const bool  is_priv,
CachedState state 
)
protected

◆ checkPermissions() [1/2]

Fault gem5::MMU::checkPermissions ( TlbEntry te,
const RequestPtr req,
Mode  mode,
bool  stage2 
)

Definition at line 274 of file mmu.cc.

References gem5::ArmISA::mode, s1State, s2State, and gem5::ArmISA::te.

Referenced by getResultTe(), and gem5::ArmISA::Stage2LookUp::getTe().

◆ checkPermissions() [2/2]

Fault gem5::MMU::checkPermissions ( TlbEntry te,
const RequestPtr req,
Mode  mode,
CachedState state 
)

◆ checkPermissions64() [1/2]

Fault gem5::MMU::checkPermissions64 ( TlbEntry te,
const RequestPtr req,
Mode  mode,
ThreadContext tc,
bool  stage2 
)

Definition at line 460 of file mmu.cc.

References gem5::ArmISA::mode, s1State, s2State, and gem5::ArmISA::te.

Referenced by getResultTe(), and gem5::ArmISA::Stage2LookUp::getTe().

◆ checkPermissions64() [2/2]

Fault gem5::MMU::checkPermissions64 ( TlbEntry te,
const RequestPtr req,
Mode  mode,
ThreadContext tc,
CachedState state 
)

◆ checkWalkCache()

bool gem5::MMU::checkWalkCache ( ) const
protected

Definition at line 111 of file mmu.cc.

References gem5::BaseMMU::data, gem5::BaseMMU::instruction, gem5::ArmISA::tlb, and gem5::BaseMMU::unified.

Referenced by init().

◆ dflush()

template<typename OP >
void gem5::ArmISA::MMU::dflush ( const OP &  tlbi_op)
inline

◆ drainResume()

void gem5::MMU::drainResume ( )
overridevirtual

Resume execution after a successful drain.

Reimplemented from gem5::Drainable.

Definition at line 130 of file mmu.cc.

References gem5::ArmISA::MMU::CachedState::miscRegValid, s1State, and s2State.

◆ faultPAN()

bool gem5::MMU::faultPAN ( ThreadContext tc,
uint8_t  ap,
const RequestPtr req,
Mode  mode,
const bool  is_priv,
CachedState state 
)
protected

◆ finalizePhysical()

Fault gem5::MMU::finalizePhysical ( const RequestPtr req,
ThreadContext tc,
Mode  mode 
) const
overridevirtual

◆ flush()

template<typename OP >
void gem5::ArmISA::MMU::flush ( const OP &  tlbi_op)
inline

◆ flushAll()

void gem5::ArmISA::MMU::flushAll ( )
inlineoverridevirtual

Reimplemented from gem5::BaseMMU.

Definition at line 324 of file mmu.hh.

References dtbStage2, gem5::BaseMMU::flushAll(), gem5::ArmISA::TLB::flushAll(), and itbStage2.

◆ flushStage1()

template<typename OP >
void gem5::ArmISA::MMU::flushStage1 ( const OP &  tlbi_op)
inline

◆ flushStage2()

template<typename OP >
void gem5::ArmISA::MMU::flushStage2 ( const OP &  tlbi_op)
inline

Definition at line 293 of file mmu.hh.

References dtbStage2, gem5::ArmISA::TLB::flush(), and itbStage2.

Referenced by flush(), and gem5::ArmISA::TLBIIPA::operator()().

◆ getAttr()

uint64_t gem5::ArmISA::MMU::getAttr ( ) const
inline

Definition at line 332 of file mmu.hh.

References _attr.

Referenced by gem5::ArmISA::ISA::addressTranslation(), and gem5::ArmISA::ISA::addressTranslation64().

◆ getDTBPtr()

ArmISA::TLB* gem5::ArmISA::MMU::getDTBPtr ( ) const
inlineprotected

Definition at line 65 of file mmu.hh.

References gem5::BaseMMU::dtb.

Referenced by getTlb(), and init().

◆ getITBPtr()

ArmISA::TLB* gem5::ArmISA::MMU::getITBPtr ( ) const
inlineprotected

Definition at line 71 of file mmu.hh.

References gem5::BaseMMU::itb.

Referenced by getTlb(), and init().

◆ getResultTe()

Fault gem5::MMU::getResultTe ( TlbEntry **  te,
const RequestPtr req,
ThreadContext tc,
Mode  mode,
Translation translation,
bool  timing,
bool  functional,
TlbEntry mergeTe,
CachedState state 
)

◆ getTableWalker()

TableWalker * gem5::MMU::getTableWalker ( BaseMMU::Mode  mode,
bool  stage2 
) const
protected

Definition at line 153 of file mmu.cc.

References dtbStage2Walker, dtbWalker, gem5::BaseMMU::Execute, itbStage2Walker, itbWalker, and gem5::ArmISA::mode.

Referenced by getTE().

◆ getTE() [1/2]

Fault gem5::MMU::getTE ( TlbEntry **  te,
const RequestPtr req,
ThreadContext tc,
Mode  mode,
Translation translation,
bool  timing,
bool  functional,
bool  is_secure,
ArmTranslationType  tran_type,
bool  stage2 
)

◆ getTE() [2/2]

Fault gem5::MMU::getTE ( TlbEntry **  te,
const RequestPtr req,
ThreadContext tc,
Mode  mode,
Translation translation,
bool  timing,
bool  functional,
bool  is_secure,
ArmTranslationType  tran_type,
CachedState state 
)

◆ getTlb()

TLB * gem5::MMU::getTlb ( BaseMMU::Mode  mode,
bool  stage2 
) const
protected

Definition at line 137 of file mmu.cc.

References dtbStage2, gem5::BaseMMU::Execute, getDTBPtr(), getITBPtr(), itbStage2, and gem5::ArmISA::mode.

Referenced by lookup(), and translateFunctional().

◆ hasWalkCache()

bool gem5::ArmISA::MMU::hasWalkCache ( ) const
inline

Definition at line 347 of file mmu.hh.

References _hasWalkCache.

Referenced by gem5::ArmISA::TableWalker::doLongDescriptor().

◆ iflush()

template<typename OP >
void gem5::ArmISA::MMU::iflush ( const OP &  tlbi_op)
inline

◆ init()

void gem5::MMU::init ( )
overridevirtual

init() is called after all C++ SimObjects have been created and all ports are connected.

Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.

Reimplemented from gem5::SimObject.

Definition at line 92 of file mmu.cc.

References _hasWalkCache, checkWalkCache(), dtbStage2, dtbStage2Walker, dtbWalker, getDTBPtr(), getITBPtr(), gem5::BaseMMU::init(), itbStage2, itbStage2Walker, itbWalker, gem5::ArmISA::TableWalker::setMmu(), and gem5::ArmISA::TLB::setTableWalker().

◆ invalidateMiscReg()

void gem5::MMU::invalidateMiscReg ( )

◆ isCompleteTranslation()

bool gem5::MMU::isCompleteTranslation ( TlbEntry te) const
protected

Definition at line 1563 of file mmu.cc.

References gem5::ArmISA::TlbEntry::partial.

Referenced by getResultTe(), getTE(), and translateMmuOn().

◆ lookup()

TlbEntry * gem5::MMU::lookup ( Addr  vpn,
uint16_t  asn,
vmid_t  vmid,
bool  hyp,
bool  secure,
bool  functional,
bool  ignore_asn,
ExceptionLevel  target_el,
bool  in_host,
bool  stage2,
BaseMMU::Mode  mode 
)

Lookup an entry in the TLB.

Parameters
vpnvirtual address
asncontext id/address space id to use
vmidThe virtual machine ID used for stage 2 translation
secureif the lookup is secure
hypif the lookup is done from hyp mode
functionalif the lookup should modify state
ignore_asnif on lookup asn should be ignored
target_elselecting the translation regime
in_hostif we are in host (EL2&0 regime)
modeto differentiate between read/writes/fetches.
Returns
pointer to TLB entry if it exists

Definition at line 1407 of file mmu.cc.

References gem5::ArmISA::asid, gem5::ArmISA::TlbEntry::Lookup::asn, gem5::ArmISA::TlbEntry::Lookup::functional, getTlb(), gem5::ArmISA::TlbEntry::Lookup::hyp, gem5::ArmISA::TlbEntry::Lookup::ignoreAsn, gem5::ArmISA::TlbEntry::Lookup::inHost, gem5::ArmISA::mode, gem5::ArmISA::TlbEntry::Lookup::mode, gem5::ArmISA::TlbEntry::Lookup::secure, gem5::ArmISA::TlbEntry::Lookup::targetEL, gem5::ArmISA::tlb, gem5::ArmISA::TlbEntry::Lookup::va, gem5::ArmISA::va, and gem5::ArmISA::TlbEntry::Lookup::vmid.

Referenced by getTE(), and gem5::ArmISA::TableWalker::processWalkWrapper().

◆ release()

const ArmRelease* gem5::ArmISA::MMU::release ( ) const
inline

Definition at line 345 of file mmu.hh.

References _release.

Referenced by gem5::ArmISA::TableWalker::setMmu().

◆ s1PermBits64()

std::pair< bool, bool > gem5::MMU::s1PermBits64 ( TlbEntry te,
const RequestPtr req,
Mode  mode,
ThreadContext tc,
CachedState state,
bool  r,
bool  w,
bool  x 
)
protected

◆ s2PermBits64()

std::pair< bool, bool > gem5::MMU::s2PermBits64 ( TlbEntry te,
const RequestPtr req,
Mode  mode,
ThreadContext tc,
CachedState state,
bool  r,
bool  w,
bool  x 
)
protected

◆ setAttr()

void gem5::ArmISA::MMU::setAttr ( uint64_t  attr)
inline

Accessor functions for memory attributes for last accessed TLB entry.

Definition at line 340 of file mmu.hh.

References _attr, and gem5::ArmISA::attr.

Referenced by translateMmuOff(), and translateMmuOn().

◆ setTestInterface()

void gem5::MMU::setTestInterface ( SimObject ti)

Definition at line 1583 of file mmu.cc.

References fatal_if, gem5::Named::name(), and gem5::MipsISA::ti.

◆ takeOverFrom()

void gem5::MMU::takeOverFrom ( BaseMMU old_mmu)
overridevirtual

Reimplemented from gem5::BaseMMU.

Definition at line 1569 of file mmu.cc.

References _attr, s1State, s2State, and gem5::BaseMMU::takeOverFrom().

◆ testTranslation()

Fault gem5::MMU::testTranslation ( const RequestPtr req,
Mode  mode,
TlbEntry::DomainType  domain,
CachedState state 
)

◆ testWalk() [1/2]

Fault gem5::MMU::testWalk ( Addr  pa,
Addr  size,
Addr  va,
bool  is_secure,
Mode  mode,
TlbEntry::DomainType  domain,
LookupLevel  lookup_level,
bool  stage2 
)

◆ testWalk() [2/2]

Fault gem5::MMU::testWalk ( Addr  pa,
Addr  size,
Addr  va,
bool  is_secure,
Mode  mode,
TlbEntry::DomainType  domain,
LookupLevel  lookup_level,
CachedState state 
)

◆ translateAtomic() [1/3]

Fault gem5::MMU::translateAtomic ( const RequestPtr req,
ThreadContext tc,
BaseMMU::Mode  mode,
ArmTranslationType  tran_type,
bool  stage2 
)

◆ translateAtomic() [2/3]

Fault gem5::ArmISA::MMU::translateAtomic ( const RequestPtr req,
ThreadContext tc,
Mode  mode 
)
inlineoverridevirtual

◆ translateAtomic() [3/3]

Fault gem5::MMU::translateAtomic ( const RequestPtr req,
ThreadContext tc,
Mode  mode,
ArmTranslationType  tran_type 
)

Definition at line 1024 of file mmu.cc.

References gem5::ArmISA::mode, and translateAtomic().

◆ translateComplete() [1/2]

Fault gem5::MMU::translateComplete ( const RequestPtr req,
ThreadContext tc,
Translation translation,
Mode  mode,
ArmTranslationType  tran_type,
bool  call_from_s2 
)

Definition at line 1091 of file mmu.cc.

References gem5::ArmISA::mode, and s1State.

Referenced by gem5::ArmISA::Stage2LookUp::finish(), and translateTiming().

◆ translateComplete() [2/2]

Fault gem5::MMU::translateComplete ( const RequestPtr req,
ThreadContext tc,
Translation translation,
Mode  mode,
ArmTranslationType  tran_type,
bool  call_from_s2,
CachedState state 
)

◆ translateFs()

Fault gem5::MMU::translateFs ( const RequestPtr req,
ThreadContext tc,
Mode  mode,
Translation translation,
bool &  delay,
bool  timing,
ArmTranslationType  tran_type,
bool  functional,
CachedState state 
)

◆ translateFunctional() [1/7]

virtual TranslationGenPtr gem5::BaseMMU::translateFunctional

Returns a translation generator for a region of virtual addresses, instead of directly translating a specific address.

◆ translateFunctional() [2/7]

TranslationGenPtr gem5::ArmISA::MMU::translateFunctional ( Addr  start,
Addr  size,
ThreadContext tc,
Mode  mode,
Request::Flags  flags 
)
inlineoverridevirtual

Returns a translation generator for a region of virtual addresses, instead of directly translating a specific address.

Implements gem5::BaseMMU.

Definition at line 90 of file mmu.hh.

References gem5::ArmISA::mode, and gem5::ArmISA::PageBytes.

Referenced by gem5::ArmISA::ISA::addressTranslation(), gem5::ArmISA::ISA::addressTranslation64(), gem5::ArmISA::TableWalker::readDataUntimed(), gem5::Trace::TarmacTracerRecordV8::TraceMemEntryV8::TraceMemEntryV8(), and translateFunctional().

◆ translateFunctional() [3/7]

Fault gem5::MMU::translateFunctional ( const RequestPtr req,
ThreadContext tc,
BaseMMU::Mode  mode 
)
overridevirtual

Reimplemented from gem5::BaseMMU.

Definition at line 1048 of file mmu.cc.

References gem5::ArmISA::mode, NormalTran, and translateFunctional().

◆ translateFunctional() [4/7]

Fault gem5::MMU::translateFunctional ( const RequestPtr req,
ThreadContext tc,
BaseMMU::Mode  mode,
ArmTranslationType  tran_type 
)

Do a functional lookup on the TLB (for checker cpu) that behaves like a normal lookup without modifying any page table state.

Definition at line 1054 of file mmu.cc.

References gem5::ArmISA::mode, and translateFunctional().

◆ translateFunctional() [5/7]

Fault gem5::MMU::translateFunctional ( const RequestPtr req,
ThreadContext tc,
BaseMMU::Mode  mode,
ArmTranslationType  tran_type,
bool  stage2 
)

◆ translateFunctional() [6/7]

Fault gem5::BaseMMU::translateFunctional

Definition at line 118 of file mmu.cc.

◆ translateFunctional() [7/7]

bool gem5::MMU::translateFunctional ( ThreadContext tc,
Addr  vaddr,
Addr paddr 
)

◆ translateMmuOff()

Fault gem5::MMU::translateMmuOff ( ThreadContext tc,
const RequestPtr req,
Mode  mode,
ArmTranslationType  tran_type,
Addr  vaddr,
bool  long_desc_format,
CachedState state 
)

◆ translateMmuOn()

Fault gem5::MMU::translateMmuOn ( ThreadContext tc,
const RequestPtr req,
Mode  mode,
Translation translation,
bool &  delay,
bool  timing,
bool  functional,
Addr  vaddr,
ArmFault::TranMethod  tranMethod,
CachedState state 
)

◆ translateSe()

Fault gem5::MMU::translateSe ( const RequestPtr req,
ThreadContext tc,
Mode  mode,
Translation translation,
bool &  delay,
bool  timing,
CachedState state 
)

◆ translateTiming() [1/3]

void gem5::ArmISA::MMU::translateTiming ( const RequestPtr req,
ThreadContext tc,
BaseMMU::Translation translation,
BaseMMU::Mode  mode,
bool  stage2 
)

◆ translateTiming() [2/3]

void gem5::ArmISA::MMU::translateTiming ( const RequestPtr req,
ThreadContext tc,
Translation translation,
Mode  mode 
)
inlineoverridevirtual

◆ translateTiming() [3/3]

void gem5::MMU::translateTiming ( const RequestPtr req,
ThreadContext tc,
Translation translation,
Mode  mode,
ArmTranslationType  tran_type,
bool  stage2 
)

Definition at line 1078 of file mmu.cc.

References gem5::ArmISA::mode, translateComplete(), and updateMiscReg().

◆ tranTypeEL()

ExceptionLevel gem5::MMU::tranTypeEL ( CPSR  cpsr,
ArmTranslationType  type 
)
static

Determine the EL to use for the purpose of a translation given a specific translation type.

If the translation type doesn't specify an EL, we use the current EL.

Definition at line 1368 of file mmu.cc.

References gem5::ArmISA::currEL(), gem5::ArmISA::EL0, gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL3, HypMode, NormalTran, panic, S12E0Tran, S12E1Tran, S1CTran, S1E0Tran, S1E1Tran, S1E2Tran, S1E3Tran, S1S2NsTran, and gem5::X86ISA::type.

Referenced by gem5::ArmISA::MMU::CachedState::updateMiscReg(), and gem5::ArmISA::TableWalker::walk().

◆ updateMiscReg()

MMU::CachedState & gem5::MMU::updateMiscReg ( ThreadContext tc,
ArmTranslationType  tran_type,
bool  stage2 
)
protected

Member Data Documentation

◆ _attr

uint64_t gem5::ArmISA::MMU::_attr
protected

Definition at line 445 of file mmu.hh.

Referenced by getAttr(), setAttr(), and takeOverFrom().

◆ _hasWalkCache

bool gem5::ArmISA::MMU::_hasWalkCache
protected

Definition at line 454 of file mmu.hh.

Referenced by hasWalkCache(), and init().

◆ _release

const ArmRelease* gem5::ArmISA::MMU::_release
protected

Definition at line 448 of file mmu.hh.

Referenced by MMU(), and release().

◆ dtbStage2

TLB* gem5::ArmISA::MMU::dtbStage2
protected

Definition at line 81 of file mmu.hh.

Referenced by flushAll(), flushStage2(), getTlb(), init(), and updateMiscReg().

◆ dtbStage2Walker

TableWalker* gem5::ArmISA::MMU::dtbStage2Walker
protected

Definition at line 86 of file mmu.hh.

Referenced by getTableWalker(), and init().

◆ dtbWalker

TableWalker* gem5::ArmISA::MMU::dtbWalker
protected

Definition at line 84 of file mmu.hh.

Referenced by getTableWalker(), and init().

◆ haveLargeAsid64

bool gem5::ArmISA::MMU::haveLargeAsid64
protected

Definition at line 449 of file mmu.hh.

Referenced by MMU().

◆ itbStage2

TLB* gem5::ArmISA::MMU::itbStage2
protected

Definition at line 80 of file mmu.hh.

Referenced by flushAll(), flushStage2(), getTlb(), init(), and updateMiscReg().

◆ itbStage2Walker

TableWalker* gem5::ArmISA::MMU::itbStage2Walker
protected

Definition at line 85 of file mmu.hh.

Referenced by getTableWalker(), and init().

◆ itbWalker

TableWalker* gem5::ArmISA::MMU::itbWalker
protected

Definition at line 83 of file mmu.hh.

Referenced by getTableWalker(), and init().

◆ m5opRange

AddrRange gem5::ArmISA::MMU::m5opRange
protected

Definition at line 452 of file mmu.hh.

Referenced by finalizePhysical(), and MMU().

◆ miscRegContext

ContextID gem5::ArmISA::MMU::miscRegContext
protected

Definition at line 439 of file mmu.hh.

Referenced by updateMiscReg().

◆ physAddrRange

uint8_t gem5::ArmISA::MMU::physAddrRange
protected

Definition at line 450 of file mmu.hh.

Referenced by MMU(), and translateMmuOff().

◆ s1State

CachedState gem5::ArmISA::MMU::s1State

◆ s2State

CachedState gem5::ArmISA::MMU::s2State

◆ stats

gem5::ArmISA::MMU::Stats gem5::ArmISA::MMU::stats
protected

◆ test

TlbTestInterface* gem5::ArmISA::MMU::test

Definition at line 416 of file mmu.hh.


The documentation for this class was generated from the following files:

Generated on Wed May 4 2022 12:14:56 for gem5 by doxygen 1.8.17