gem5  v21.1.0.2
mmu.cc
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37 
38 #include "arch/arm/mmu.hh"
39 #include "arch/arm/table_walker.hh"
40 #include "arch/arm/tlbi_op.hh"
41 
42 namespace gem5
43 {
44 
45 using namespace ArmISA;
46 
47 MMU::MMU(const ArmMMUParams &p)
48  : BaseMMU(p),
49  itbStage2(p.stage2_itb), dtbStage2(p.stage2_dtb),
50  iport(p.itb_walker, p.sys->getRequestorId(p.itb_walker)),
51  dport(p.dtb_walker, p.sys->getRequestorId(p.dtb_walker)),
52  itbWalker(p.itb_walker), dtbWalker(p.dtb_walker),
53  itbStage2Walker(p.stage2_itb_walker),
54  dtbStage2Walker(p.stage2_dtb_walker)
55 {
60 }
61 
62 void
64 {
65  itbWalker->setMmu(this);
66  dtbWalker->setMmu(this);
67  itbStage2Walker->setMmu(this);
68  dtbStage2Walker->setMmu(this);
69 
72 
77 }
78 
79 TLB *
80 MMU::getTlb(BaseMMU::Mode mode, bool stage2) const
81 {
82  if (mode == BaseMMU::Execute) {
83  if (stage2)
84  return itbStage2;
85  else
86  return getITBPtr();
87  } else {
88  if (stage2)
89  return dtbStage2;
90  else
91  return getDTBPtr();
92  }
93 }
94 
95 bool
97 {
98  return getDTBPtr()->translateFunctional(tc, vaddr, paddr);
99 }
100 
101 Fault
104 {
105  return translateFunctional(req, tc, mode, tran_type, false);
106 }
107 
108 Fault
111  bool stage2)
112 {
113  return getTlb(mode, stage2)->translateFunctional(
114  req, tc, mode, tran_type);
115 }
116 
117 Fault
119  BaseMMU::Mode mode, bool stage2)
120 {
121  return getTlb(mode, stage2)->translateAtomic(req, tc, mode);
122 }
123 
124 void
126  BaseMMU::Translation *translation, BaseMMU::Mode mode, bool stage2)
127 {
128  return getTlb(mode, stage2)->translateTiming(req, tc, translation, mode);
129 }
130 
131 void
133 {
134  if (type & TLBType::I_TLBS) {
136  }
137  if (type & TLBType::D_TLBS) {
139  }
140 }
141 
142 } // namespace gem5
gem5::ArmISA::MMU::itbWalker
TableWalker * itbWalker
Definition: mmu.hh:76
gem5::ArmISA::MMU::translateAtomic
Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, bool stage2)
Definition: mmu.cc:118
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:53
gem5::ArmISA::MMU::dtbStage2Walker
TableWalker * dtbStage2Walker
Definition: mmu.hh:79
gem5::ArmISA::MMU::iport
TableWalker::Port iport
Definition: mmu.hh:73
gem5::ArmISA::TLB
Definition: tlb.hh:109
gem5::ArmISA::MMU::getDTBPtr
ArmISA::TLB * getDTBPtr() const
Definition: mmu.hh:56
gem5::ArmISA::TLB::setStage2Tlb
void setStage2Tlb(TLB *stage2_tlb)
Definition: tlb.hh:236
gem5::ArmISA::TLB::invalidateMiscReg
void invalidateMiscReg()
Definition: tlb.hh:453
table_walker.hh
gem5::ArmISA::MMU::dtbWalker
TableWalker * dtbWalker
Definition: mmu.hh:77
gem5::ArmISA::MMU::TLBType
TLBType
Definition: mmu.hh:82
gem5::ArmISA::MMU::MMU
MMU(const ArmMMUParams &p)
Definition: mmu.cc:47
gem5::ArmISA::MMU::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: mmu.cc:63
gem5::BaseMMU::Execute
@ Execute
Definition: mmu.hh:53
gem5::BaseMMU
Definition: mmu.hh:50
gem5::ArmISA::MMU::itbStage2Walker
TableWalker * itbStage2Walker
Definition: mmu.hh:78
gem5::ArmISA::MMU::dport
TableWalker::Port dport
Definition: mmu.hh:74
mmu.hh
gem5::ArmISA::MMU::itbStage2
TLB * itbStage2
Definition: mmu.hh:70
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::ArmISA::TLB::translateAtomic
Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, ArmTranslationType tranType)
Definition: tlb.cc:1256
gem5::ArmISA::MMU::translateTiming
void translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode, bool stage2)
Definition: mmu.cc:125
gem5::ArmISA::TLB::translateFunctional
bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr)
Do a functional lookup on the TLB (for debugging) and don't modify any internal state.
Definition: tlb.cc:119
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::X86ISA::type
type
Definition: misc.hh:733
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::ArmISA::TLB::translateTiming
void translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode, ArmTranslationType tranType)
Definition: tlb.cc:1298
tlbi_op.hh
gem5::ArmISA::MMU::translateFunctional
bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr)
Definition: mmu.cc:96
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::MMU::getITBPtr
ArmISA::TLB * getITBPtr() const
Definition: mmu.hh:62
gem5::BaseMMU::Translation
Definition: mmu.hh:55
gem5::ArmISA::MMU::getTlb
TLB * getTlb(BaseMMU::Mode mode, bool stage2) const
Definition: mmu.cc:80
gem5::ArmISA::TableWalker::setPort
void setPort(Port *_port)
Definition: table_walker.hh:1040
gem5::ArmISA::TLB::setTableWalker
void setTableWalker(TableWalker *table_walker)
Definition: tlb.cc:112
gem5::ArmISA::TLB::ArmTranslationType
ArmTranslationType
Definition: tlb.hh:128
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::ArmISA::MMU::dtbStage2
TLB * dtbStage2
Definition: mmu.hh:71
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::MMU::invalidateMiscReg
void invalidateMiscReg(TLBType type=ALL_TLBS)
Definition: mmu.cc:132
gem5::ArmISA::TableWalker::setMmu
void setMmu(MMU *_mmu)
Definition: table_walker.hh:1038
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73

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