gem5  v22.0.0.2
utility.cc
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1 /*
2  * Copyright (c) 2009-2014, 2016-2020, 2022 Arm Limited
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37 
38 #include "arch/arm/utility.hh"
39 
40 #include <memory>
41 
42 #include "arch/arm/faults.hh"
43 #include "arch/arm/interrupts.hh"
44 #include "arch/arm/mmu.hh"
45 #include "arch/arm/page_size.hh"
46 #include "arch/arm/regs/cc.hh"
47 #include "arch/arm/regs/int.hh"
48 #include "arch/arm/regs/vec.hh"
49 #include "arch/arm/system.hh"
50 #include "base/compiler.hh"
51 #include "cpu/base.hh"
52 #include "cpu/checker/cpu.hh"
53 #include "cpu/thread_context.hh"
54 #include "mem/port_proxy.hh"
55 #include "sim/full_system.hh"
56 
57 namespace gem5
58 {
59 
60 namespace ArmISA
61 {
62 
63 void
65 {
66  if (tc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
67  // Post Interrupt and wake cpu if needed
68  tc->getCpuPtr()->postInterrupt(tc->threadId(), INT_SEV, 0);
69  }
70 }
71 
72 bool
74 {
75  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
76  if (ArmSystem::haveEL(tc, EL3) && !cpsr.width && currEL(tc) == EL3)
77  return true;
78  if (ArmSystem::haveEL(tc, EL3) && cpsr.width && cpsr.mode == MODE_MON)
79  return true;
80  else
81  return isSecureBelowEL3(tc);
82 }
83 
84 bool
86 {
87  return ArmSystem::haveEL(tc, EL3) &&
88  static_cast<SCR>(tc->readMiscRegNoEffect(MISCREG_SCR)).ns == 0;
89 }
90 
92 debugTargetFrom(ThreadContext *tc, bool secure)
93 {
94  bool route_to_el2;
95  if (ArmSystem::haveEL(tc, EL2) &&
96  (!secure || HaveExt(tc, ArmExtension::FEAT_SEL2))) {
97  if (ELIs32(tc, EL2)) {
98  const HCR hcr = tc->readMiscReg(MISCREG_HCR);
99  const HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
100  route_to_el2 = (hdcr.tde == 1 || hcr.tge == 1);
101  } else {
102  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
103  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
104  route_to_el2 = (mdcr.tde == 1 || hcr.tge == 1);
105  }
106  }else{
107  route_to_el2 = false;
108  }
109  ExceptionLevel target;
110  if (route_to_el2) {
111  target = EL2;
112  } else if (ArmSystem::haveEL(tc, EL3) && !ArmSystem::highestELIs64(tc)
113  && secure) {
114  target = EL3;
115  } else {
116  target = EL1;
117  }
118  return target;
119 }
120 
121 bool
123 {
124  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
125  return opModeIs64((OperatingMode) (uint8_t) cpsr.mode);
126 }
127 
130 {
131  return static_cast<ArmISA::ISA *>(
132  const_cast<ThreadContext *>(tc)->getIsaPtr())->currEL();
133 }
134 
135 bool
137 {
138  TTBCR ttbcr = tc->readMiscReg(MISCREG_TTBCR);
139  return ArmSystem::has(ArmExtension::LPAE, tc) && ttbcr.eae;
140 }
141 
142 RegVal
144 {
145  const ExceptionLevel current_el = currEL(tc);
146 
147  const bool is_secure = isSecureBelowEL3(tc);
148 
149  switch (current_el) {
150  case EL0:
151  // Note: in MsrMrs instruction we read the register value before
152  // checking access permissions. This means that EL0 entry must
153  // be part of the table even if MPIDR is not accessible in user
154  // mode.
155  warn_once("Trying to read MPIDR at EL0\n");
156  [[fallthrough]];
157  case EL1:
158  if (ArmSystem::haveEL(tc, EL2) && !is_secure)
159  return tc->readMiscReg(MISCREG_VMPIDR_EL2);
160  else
161  return getMPIDR(arm_sys, tc);
162  case EL2:
163  case EL3:
164  return getMPIDR(arm_sys, tc);
165  default:
166  panic("Invalid EL for reading MPIDR register\n");
167  }
168 }
169 
170 RegVal
172 {
173  // Multiprocessor Affinity Register MPIDR from Cortex(tm)-A15 Technical
174  // Reference Manual
175  //
176  // bit 31 - Multi-processor extensions available
177  // bit 30 - Uni-processor system
178  // bit 24 - Multi-threaded cores
179  // bit 11-8 - Cluster ID
180  // bit 1-0 - CPU ID
181  //
182  // We deliberately extend both the Cluster ID and CPU ID fields to allow
183  // for simulation of larger systems
184  assert((0 <= tc->cpuId()) && (tc->cpuId() < 256));
185  assert(tc->socketId() < 65536);
186 
187  RegVal mpidr = 0x80000000;
188 
189  if (!arm_sys->multiProc)
190  replaceBits(mpidr, 30, 1);
191 
192  if (arm_sys->multiThread)
193  replaceBits(mpidr, 24, 1);
194 
195  // Get Affinity numbers
196  mpidr |= getAffinity(arm_sys, tc);
197  return mpidr;
198 }
199 
200 static RegVal
202 {
203  return arm_sys->multiThread ? tc->socketId() : 0;
204 }
205 
206 static RegVal
208 {
209  return arm_sys->multiThread ? tc->cpuId() : tc->socketId();
210 }
211 
212 static RegVal
214 {
215  return arm_sys->multiThread ? tc->threadId() : tc->cpuId();
216 }
217 
218 Affinity
220 {
221  Affinity aff = 0;
222  aff.aff0 = getAff0(arm_sys, tc);
223  aff.aff1 = getAff1(arm_sys, tc);
224  aff.aff2 = getAff2(arm_sys, tc);
225  return aff;
226 }
227 
228 bool
229 HaveExt(ThreadContext* tc, ArmExtension ext)
230 {
231  auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
232  return isa->getRelease()->has(ext);
233 }
234 
237 {
238  if (el != EL0)
239  return el;
240  else if (ArmSystem::haveEL(tc, EL3) && ELIs32(tc, EL3) &&
241  static_cast<SCR>(tc->readMiscRegNoEffect(MISCREG_SCR)).ns == 0)
242  return EL3;
243  else if (HaveExt(tc, ArmExtension::FEAT_VHE) && ELIsInHost(tc, el))
244  return EL2;
245  else
246  return EL1;
247 }
248 
249 bool
251 {
252  if (ArmSystem::haveEL(tc, EL2) && HaveExt(tc, ArmExtension::FEAT_SEL2) &&
253  !ELIs32(tc, EL2)) {
254  if (ArmSystem::haveEL(tc, EL3))
255  return !ELIs32(tc, EL3) && static_cast<SCR>(
257  else
258  return isSecure(tc);
259  }
260  return false;
261 }
262 
263 bool
265 {
266  return ArmSystem::haveEL(tc, EL2) &&
267  (!ArmSystem::haveEL(tc, EL3) || static_cast<SCR>(
269  IsSecureEL2Enabled(tc));
270 }
271 
272 bool
274 {
275  return !ELIs32(tc, el);
276 }
277 
278 bool
280 {
281  auto [known, aarch32] = ELUsingAArch32K(tc, el);
282  panic_if(!known, "EL state is UNKNOWN");
283  return aarch32;
284 }
285 
286 bool
288 {
289  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
290  return (ArmSystem::haveEL(tc, EL2) &&
291  (IsSecureEL2Enabled(tc) || !isSecureBelowEL3(tc)) &&
292  HaveExt(tc, ArmExtension::FEAT_VHE) &&
293  !ELIs32(tc, EL2) && hcr.e2h == 1 &&
294  (el == EL2 || (el == EL0 && hcr.tge == 1)));
295 }
296 
299 {
300  bool secure = isSecureBelowEL3(tc);
301  return ELStateUsingAArch32K(tc, el, secure);
302 }
303 
304 bool
306 {
307  if (!ArmSystem::haveEL(tc, el))
308  return false;
309  else if (!ArmSystem::highestELIs64(tc))
310  return true;
311  else if (ArmSystem::highestEL(tc) == el)
312  return false;
313  else if (el == EL0)
314  return true;
315  return true;
316 }
317 
320 {
321  // Return true if the specified EL is in aarch32 state.
322  const bool have_el3 = ArmSystem::haveEL(tc, EL3);
323  const bool have_el2 = ArmSystem::haveEL(tc, EL2);
324 
325  panic_if(el == EL2 && !have_el2, "Asking for EL2 when it doesn't exist");
326  panic_if(el == EL3 && !have_el3, "Asking for EL3 when it doesn't exist");
327 
328  bool known, aarch32;
329  known = aarch32 = false;
330  if (!haveAArch32EL(tc, el)) {
331  // Target EL is the highest one in a system where
332  // the highest is using AArch64.
333  known = true; aarch32 = false;
334  } else if (secure && el == EL2) {
335  known = true; aarch32 = false;
336  } else if (!ArmSystem::highestELIs64(tc)) {
337  // All ELs are using AArch32:
338  known = true; aarch32 = true;
339  } else if (ArmSystem::highestEL(tc) == el) {
340  known = true; aarch32 = false;
341  } else {
342  SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
343  bool aarch32_below_el3 = have_el3 && scr.rw == 0 &&
344  (!secure || !HaveExt(tc, ArmExtension::FEAT_SEL2) || !scr.eel2);
345 
346  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
347  bool sec_el2 = HaveExt(tc, ArmExtension::FEAT_SEL2) && scr.eel2;
348  bool aarch32_at_el1 = (aarch32_below_el3 ||
349  (have_el2 && (sec_el2 || !secure) &&
350  hcr.rw == 0 &&
351  !(hcr.e2h && hcr.tge &&
352  HaveExt(tc, ArmExtension::FEAT_VHE))));
353 
354  // Only know if EL0 using AArch32 from PSTATE
355  if (el == EL0 && !aarch32_at_el1) {
356  // EL0 controlled by PSTATE
357  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
358  known = (currEL(tc) == EL0);
359  aarch32 = (cpsr.width == 1);
360  } else {
361  known = true;
362  aarch32 = (aarch32_below_el3 && el != EL3) ||
363  (aarch32_at_el1 && (el == EL0 || el == EL1) );
364  }
365  }
366 
367  return std::make_pair(known, aarch32);
368 }
369 
370 bool
372 {
373  auto [known, aarch32] = ELStateUsingAArch32K(tc, el, secure);
374  panic_if(!known, "EL state is UNKNOWN");
375  return aarch32;
376 }
377 
378 bool
380 {
381  switch (currEL(tc)) {
382  case EL3:
383  return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL3)).ee;
384  case EL2:
385  return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL2)).ee;
386  case EL1:
387  return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL1)).ee;
388  case EL0:
389  return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL1)).e0e;
390  default:
391  panic("Invalid exception level");
392  break;
393  }
394 }
395 
396 bool
398 {
400 }
401 
402 bool
404 {
406 }
407 
408 int
409 computeAddrTop(ThreadContext *tc, bool selbit, bool is_instr,
410  TCR tcr, ExceptionLevel el)
411 {
412  bool tbi = false;
413  bool tbid = false;
414  ExceptionLevel regime = s1TranslationRegime(tc, el);
415  if (ELIs32(tc, regime)) {
416  return 31;
417  } else {
418  switch (regime) {
419  case EL1:
420  {
421  //TCR tcr = tc->readMiscReg(MISCREG_TCR_EL1);
422  tbi = selbit? tcr.tbi1 : tcr.tbi0;
423  tbid = selbit? tcr.tbid1 : tcr.tbid0;
424  break;
425  }
426  case EL2:
427  {
428  TCR tcr = tc->readMiscReg(MISCREG_TCR_EL2);
429  if (HaveExt(tc, ArmExtension::FEAT_VHE) && ELIsInHost(tc, el)) {
430  tbi = selbit? tcr.tbi1 : tcr.tbi0;
431  tbid = selbit? tcr.tbid1 : tcr.tbid0;
432  } else {
433  tbi = tcr.tbi;
434  tbid = tcr.tbid;
435  }
436  break;
437  }
438  case EL3:
439  {
440  TCR tcr = tc->readMiscReg(MISCREG_TCR_EL3);
441  tbi = tcr.tbi;
442  tbid = tcr.tbid;
443  break;
444  }
445  default:
446  break;
447  }
448 
449  }
450  int res = (tbi && (!tbid || !is_instr))? 55: 63;
451  return res;
452 }
453 
454 Addr
456  int topbit)
457 {
458  if (topbit == 63) {
459  return addr;
460  } else if (bits(addr,55) && (el <= EL1 || ELIsInHost(tc, el))) {
461  uint64_t mask = ((uint64_t)0x1 << topbit) -1;
462  addr = addr | ~mask;
463  } else {
464  addr = bits(addr, topbit, 0);
465  }
466  return addr; // Nothing to do if this is not a tagged address
467 }
468 
469 Addr
471  TCR tcr, bool is_instr)
472 {
473  bool selbit = bits(addr, 55);
474  int topbit = computeAddrTop(tc, selbit, is_instr, tcr, el);
475 
476  return maskTaggedAddr(addr, tc, el, topbit);
477 }
478 
479 Addr
481  bool is_instr)
482 {
483 
484  TCR tcr = tc->readMiscReg(MISCREG_TCR_EL1);
485  return purifyTaggedAddr(addr, tc, el, tcr, is_instr);
486 }
487 
488 Addr
490 {
491  return addr & ~(PageBytes - 1);
492 }
493 
494 Addr
496 {
497  return (addr + PageBytes - 1) & ~(PageBytes - 1);
498 }
499 
500 Fault
501 mcrMrc15Trap(const MiscRegIndex misc_reg, ExtMachInst mach_inst,
502  ThreadContext *tc, uint32_t imm)
503 {
505  if (mcrMrc15TrapToHyp(misc_reg, tc, imm, &ec))
506  return std::make_shared<HypervisorTrap>(mach_inst, imm, ec);
507  return AArch64AArch32SystemAccessTrap(misc_reg, mach_inst, tc, imm, ec);
508 }
509 
510 bool
511 mcrMrc15TrapToHyp(const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss,
513 {
514  bool is_read;
515  uint32_t crm;
516  RegIndex rt;
517  uint32_t crn;
518  uint32_t opc1;
519  uint32_t opc2;
520  bool trap_to_hyp = false;
521 
522  const HCR hcr = tc->readMiscReg(MISCREG_HCR);
523  const HDCR hdcr = tc->readMiscReg(MISCREG_HDCR);
524  const HSTR hstr = tc->readMiscReg(MISCREG_HSTR);
525  const HCPTR hcptr = tc->readMiscReg(MISCREG_HCPTR);
526 
527  if (EL2Enabled(tc) && (currEL(tc) < EL2)) {
528  mcrMrcIssExtract(iss, is_read, crm, rt, crn, opc1, opc2);
529  trap_to_hyp = ((uint32_t) hstr) & (1 << crn);
530  trap_to_hyp |= hdcr.tpm && (crn == 9) && (crm >= 12);
531  trap_to_hyp |= hcr.tidcp && (
532  ((crn == 9) && ((crm <= 2) || ((crm >= 5) && (crm <= 8)))) ||
533  ((crn == 10) && ((crm <= 1) || (crm == 4) || (crm == 8))) ||
534  ((crn == 11) && ((crm <= 8) || (crm == 15))));
535 
536  if (!trap_to_hyp) {
537  switch (unflattenMiscReg(misc_reg)) {
538  case MISCREG_CPACR:
539  trap_to_hyp = hcptr.tcpac;
540  break;
541  case MISCREG_REVIDR:
542  case MISCREG_TCMTR:
543  case MISCREG_TLBTR:
544  case MISCREG_AIDR:
545  trap_to_hyp = hcr.tid1;
546  break;
547  case MISCREG_CTR:
548  case MISCREG_CCSIDR:
549  case MISCREG_CLIDR:
550  case MISCREG_CSSELR:
551  trap_to_hyp = hcr.tid2;
552  break;
553  case MISCREG_ID_PFR0:
554  case MISCREG_ID_PFR1:
555  case MISCREG_ID_DFR0:
556  case MISCREG_ID_AFR0:
557  case MISCREG_ID_MMFR0:
558  case MISCREG_ID_MMFR1:
559  case MISCREG_ID_MMFR2:
560  case MISCREG_ID_MMFR3:
561  case MISCREG_ID_MMFR4:
562  case MISCREG_ID_ISAR0:
563  case MISCREG_ID_ISAR1:
564  case MISCREG_ID_ISAR2:
565  case MISCREG_ID_ISAR3:
566  case MISCREG_ID_ISAR4:
567  case MISCREG_ID_ISAR5:
568  case MISCREG_ID_ISAR6:
569  trap_to_hyp = hcr.tid3;
570  break;
571  case MISCREG_DCISW:
572  case MISCREG_DCCSW:
573  case MISCREG_DCCISW:
574  trap_to_hyp = hcr.tsw;
575  break;
576  case MISCREG_DCIMVAC:
577  case MISCREG_DCCIMVAC:
578  case MISCREG_DCCMVAC:
579  trap_to_hyp = hcr.tpc;
580  break;
581  case MISCREG_ICIMVAU:
582  case MISCREG_ICIALLU:
583  case MISCREG_ICIALLUIS:
584  case MISCREG_DCCMVAU:
585  trap_to_hyp = hcr.tpu;
586  break;
587  case MISCREG_TLBIALLIS:
588  case MISCREG_TLBIMVAIS:
589  case MISCREG_TLBIASIDIS:
590  case MISCREG_TLBIMVAAIS:
591  case MISCREG_TLBIMVALIS:
592  case MISCREG_TLBIMVAALIS:
593  case MISCREG_DTLBIALL:
594  case MISCREG_ITLBIALL:
595  case MISCREG_DTLBIMVA:
596  case MISCREG_ITLBIMVA:
597  case MISCREG_DTLBIASID:
598  case MISCREG_ITLBIASID:
599  case MISCREG_TLBIMVAA:
600  case MISCREG_TLBIALL:
601  case MISCREG_TLBIMVA:
602  case MISCREG_TLBIMVAL:
603  case MISCREG_TLBIMVAAL:
604  case MISCREG_TLBIASID:
605  trap_to_hyp = hcr.ttlb;
606  break;
607  case MISCREG_ACTLR:
608  trap_to_hyp = hcr.tac;
609  break;
610  case MISCREG_SCTLR:
611  case MISCREG_TTBR0:
612  case MISCREG_TTBR1:
613  case MISCREG_TTBCR:
614  case MISCREG_DACR:
615  case MISCREG_DFSR:
616  case MISCREG_IFSR:
617  case MISCREG_DFAR:
618  case MISCREG_IFAR:
619  case MISCREG_ADFSR:
620  case MISCREG_AIFSR:
621  case MISCREG_PRRR:
622  case MISCREG_NMRR:
623  case MISCREG_MAIR0:
624  case MISCREG_MAIR1:
625  case MISCREG_CONTEXTIDR:
626  trap_to_hyp = hcr.tvm & !is_read;
627  break;
628  case MISCREG_PMCR:
629  trap_to_hyp = hdcr.tpmcr;
630  break;
631  // GICv3 regs
632  case MISCREG_ICC_SGI0R:
633  {
634  auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
635  if (isa->haveGICv3CpuIfc())
636  trap_to_hyp = hcr.fmo;
637  }
638  break;
639  case MISCREG_ICC_SGI1R:
640  case MISCREG_ICC_ASGI1R:
641  {
642  auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
643  if (isa->haveGICv3CpuIfc())
644  trap_to_hyp = hcr.imo;
645  }
646  break;
648  // CNTFRQ may be trapped only on reads
649  // CNTPCT and CNTVCT are read-only
650  if (MISCREG_CNTFRQ <= misc_reg && misc_reg <= MISCREG_CNTVCT &&
651  !is_read)
652  break;
653  trap_to_hyp = isGenericTimerHypTrap(misc_reg, tc, ec);
654  break;
655  // No default action needed
656  default:
657  break;
658  }
659  }
660  }
661  return trap_to_hyp;
662 }
663 
664 
665 bool
666 mcrMrc14TrapToHyp(const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss)
667 {
668  bool is_read;
669  uint32_t crm;
670  RegIndex rt;
671  uint32_t crn;
672  uint32_t opc1;
673  uint32_t opc2;
674 
675  const HCR hcr = tc->readMiscReg(MISCREG_HCR);
676  const HDCR hdcr = tc->readMiscReg(MISCREG_HDCR);
677  const HSTR hstr = tc->readMiscReg(MISCREG_HSTR);
678  const HCPTR hcptr = tc->readMiscReg(MISCREG_HCPTR);
679 
680  bool trap_to_hyp = false;
681 
682  if (EL2Enabled(tc) && (currEL(tc) < EL2)) {
683  mcrMrcIssExtract(iss, is_read, crm, rt, crn, opc1, opc2);
684  inform("trap check M:%x N:%x 1:%x 2:%x hdcr %x, hcptr %x, hstr %x\n",
685  crm, crn, opc1, opc2, hdcr, hcptr, hstr);
686  trap_to_hyp = hdcr.tda && (opc1 == 0);
687  trap_to_hyp |= hcptr.tta && (opc1 == 1);
688  if (!trap_to_hyp) {
689  switch (unflattenMiscReg(misc_reg)) {
690  case MISCREG_DBGOSLSR:
691  case MISCREG_DBGOSLAR:
692  case MISCREG_DBGOSDLR:
693  case MISCREG_DBGPRCR:
694  trap_to_hyp = hdcr.tdosa;
695  break;
696  case MISCREG_DBGDRAR:
697  case MISCREG_DBGDSAR:
698  trap_to_hyp = hdcr.tdra;
699  break;
700  case MISCREG_JIDR:
701  trap_to_hyp = hcr.tid0;
702  break;
703  case MISCREG_JOSCR:
704  case MISCREG_JMCR:
705  trap_to_hyp = hstr.tjdbx;
706  break;
707  case MISCREG_TEECR:
708  case MISCREG_TEEHBR:
709  trap_to_hyp = hstr.ttee;
710  break;
711  // No default action needed
712  default:
713  break;
714  }
715  }
716  }
717  return trap_to_hyp;
718 }
719 
720 Fault
721 mcrrMrrc15Trap(const MiscRegIndex misc_reg, ExtMachInst mach_inst,
722  ThreadContext *tc, uint32_t imm)
723 {
725  if (mcrrMrrc15TrapToHyp(misc_reg, tc, imm, &ec))
726  return std::make_shared<HypervisorTrap>(mach_inst, imm, ec);
727  return AArch64AArch32SystemAccessTrap(misc_reg, mach_inst, tc, imm, ec);
728 }
729 
730 bool
732  uint32_t iss, ExceptionClass *ec)
733 {
734  uint32_t crm;
735  RegIndex rt;
736  uint32_t crn;
737  uint32_t opc1;
738  uint32_t opc2;
739  bool is_read;
740  bool trap_to_hyp = false;
741 
742  const HCR hcr = tc->readMiscReg(MISCREG_HCR);
743  const HSTR hstr = tc->readMiscReg(MISCREG_HSTR);
744 
745  if (EL2Enabled(tc) && (currEL(tc) < EL2)) {
746  // This is technically the wrong function, but we can re-use it for
747  // the moment because we only need one field, which overlaps with the
748  // mcrmrc layout
749  mcrMrcIssExtract(iss, is_read, crm, rt, crn, opc1, opc2);
750  trap_to_hyp = ((uint32_t)hstr) & (1 << crm);
751 
752  if (!trap_to_hyp) {
753  switch (unflattenMiscReg(misc_reg)) {
754  case MISCREG_SCTLR:
755  case MISCREG_TTBR0:
756  case MISCREG_TTBR1:
757  case MISCREG_TTBCR:
758  case MISCREG_DACR:
759  case MISCREG_DFSR:
760  case MISCREG_IFSR:
761  case MISCREG_DFAR:
762  case MISCREG_IFAR:
763  case MISCREG_ADFSR:
764  case MISCREG_AIFSR:
765  case MISCREG_PRRR:
766  case MISCREG_NMRR:
767  case MISCREG_MAIR0:
768  case MISCREG_MAIR1:
769  case MISCREG_CONTEXTIDR:
770  trap_to_hyp = hcr.tvm & !is_read;
771  break;
773  // CNTFRQ may be trapped only on reads
774  // CNTPCT and CNTVCT are read-only
775  if (MISCREG_CNTFRQ <= misc_reg && misc_reg <= MISCREG_CNTVCT &&
776  !is_read) {
777  break;
778  }
779  trap_to_hyp = isGenericTimerHypTrap(misc_reg, tc, ec);
780  break;
781  // No default action needed
782  default:
783  break;
784  }
785  }
786  }
787  return trap_to_hyp;
788 }
789 
790 Fault
792  ExtMachInst mach_inst, ThreadContext *tc,
793  uint32_t imm, ExceptionClass ec)
794 {
795  if (currEL(tc) <= EL1 && !ELIs32(tc, EL1) &&
797  return std::make_shared<SupervisorTrap>(mach_inst, imm, ec);
798  if (currEL(tc) <= EL2 && EL2Enabled(tc) && !ELIs32(tc, EL2) &&
800  return std::make_shared<HypervisorTrap>(mach_inst, imm, ec);
801  return NoFault;
802 }
803 
804 bool
806  ThreadContext *tc)
807 {
808  switch (misc_reg) {
810  return currEL(tc) == EL0 &&
811  isGenericTimerSystemAccessTrapEL1(misc_reg, tc);
812  default:
813  break;
814  }
815  return false;
816 }
817 
818 bool
821 {
822  if (currEL(tc) <= EL2 && EL2Enabled(tc) && ELIs32(tc, EL2)) {
823  switch (misc_reg) {
825  if (currEL(tc) == EL0 &&
826  isGenericTimerCommonEL0HypTrap(misc_reg, tc, ec))
827  return true;
828  switch (misc_reg) {
829  case MISCREG_CNTPCT:
831  return currEL(tc) <= EL1 &&
832  isGenericTimerPhysHypTrap(misc_reg, tc, ec);
833  default:
834  break;
835  }
836  break;
837  default:
838  break;
839  }
840  }
841  return false;
842 }
843 
844 bool
847 {
848  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
849  bool trap_cond = condGenericTimerSystemAccessTrapEL1(misc_reg, tc);
850  if (ELIs32(tc, EL1) && trap_cond && hcr.tge) {
851  // As per the architecture, this hyp trap should have uncategorized
852  // exception class
853  if (ec)
854  *ec = EC_UNKNOWN;
855  return true;
856  }
857  return false;
858 }
859 
860 bool
863 {
864  return condGenericTimerPhysHypTrap(misc_reg, tc);
865 }
866 
867 bool
869 {
870  const CNTHCTL cnthctl = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
871  switch (misc_reg) {
872  case MISCREG_CNTPCT:
873  return !cnthctl.el1pcten;
875  return !cnthctl.el1pcen;
876  default:
877  break;
878  }
879  return false;
880 }
881 
882 bool
884  ThreadContext *tc)
885 {
886  switch (misc_reg) {
889  {
890  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
891  bool trap_cond = condGenericTimerSystemAccessTrapEL1(misc_reg, tc);
892  return !(EL2Enabled(tc) && hcr.e2h && hcr.tge) && trap_cond &&
893  !(EL2Enabled(tc) && !ELIs32(tc, EL2) && hcr.tge);
894  }
895  default:
896  break;
897  }
898  return false;
899 }
900 
901 bool
903  ThreadContext *tc)
904 {
905  const CNTKCTL cntkctl = tc->readMiscReg(MISCREG_CNTKCTL_EL1);
906  switch (misc_reg) {
907  case MISCREG_CNTFRQ:
908  case MISCREG_CNTFRQ_EL0:
909  return !cntkctl.el0pcten && !cntkctl.el0vcten;
910  case MISCREG_CNTPCT:
911  case MISCREG_CNTPCT_EL0:
912  return !cntkctl.el0pcten;
913  case MISCREG_CNTVCT:
914  case MISCREG_CNTVCT_EL0:
915  return !cntkctl.el0vcten;
918  return !cntkctl.el0pten;
921  return !cntkctl.el0vten;
922  default:
923  break;
924  }
925  return false;
926 }
927 
928 bool
930  ThreadContext *tc)
931 {
932  switch (misc_reg) {
934  return currEL(tc) <= EL1 &&
935  isGenericTimerSystemAccessTrapEL2(misc_reg, tc);
936  default:
937  break;
938  }
939  return false;
940 }
941 
942 bool
944  ThreadContext *tc)
945 {
946  switch (misc_reg) {
949  if (currEL(tc) == EL0 &&
951  return true;
952  switch (misc_reg) {
953  case MISCREG_CNTPCT:
954  case MISCREG_CNTPCT_EL0:
957  return (currEL(tc) == EL0 &&
959  (currEL(tc) == EL1 &&
961  case MISCREG_CNTVCT:
962  case MISCREG_CNTVCT_EL0:
965  return isGenericTimerVirtSystemAccessTrapEL2(misc_reg, tc);
966  default:
967  break;
968  }
969  break;
970  default:
971  break;
972  }
973  return false;
974 }
975 
976 bool
978  ThreadContext *tc)
979 {
980  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
981  bool trap_cond_el1 = condGenericTimerSystemAccessTrapEL1(misc_reg, tc);
982  bool trap_cond_el2 = condGenericTimerCommonEL0SystemAccessTrapEL2(misc_reg,
983  tc);
984  return (!ELIs32(tc, EL1) && !hcr.e2h && trap_cond_el1 && hcr.tge) ||
985  (ELIs32(tc, EL1) && trap_cond_el1 && hcr.tge) ||
986  (hcr.e2h && hcr.tge && trap_cond_el2);
987 }
988 
989 bool
991  ThreadContext *tc)
992 {
993  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
995  misc_reg, tc);
997  misc_reg, tc);
998 
999  switch (misc_reg) {
1000  case MISCREG_CNTPCT:
1001  case MISCREG_CNTPCT_EL0:
1002  return !hcr.e2h && trap_cond_1;
1005  return (!hcr.e2h && trap_cond_0) ||
1006  (hcr.e2h && !hcr.tge && trap_cond_1);
1007  default:
1008  break;
1009  }
1010 
1011  return false;
1012 }
1013 
1014 bool
1016  ThreadContext *tc)
1017 {
1018  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1019  bool trap_cond_0 = condGenericTimerPhysEL1SystemAccessTrapEL2(
1020  misc_reg, tc);
1022  misc_reg, tc);
1023 
1024  switch (misc_reg) {
1025  case MISCREG_CNTPCT:
1026  case MISCREG_CNTPCT_EL0:
1027  return trap_cond_1;
1030  return (!hcr.e2h && trap_cond_0) ||
1031  (hcr.e2h && trap_cond_1);
1032  default:
1033  break;
1034  }
1035  return false;
1036 }
1037 
1038 bool
1040  ThreadContext *tc)
1041 {
1042  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1044  misc_reg, tc);
1045  return !ELIs32(tc, EL1) && !(hcr.e2h && hcr.tge) && trap_cond;
1046 }
1047 
1048 bool
1050  ThreadContext *tc)
1051 {
1052  const CNTHCTL_E2H cnthctl = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1053  switch (misc_reg) {
1054  case MISCREG_CNTFRQ:
1055  case MISCREG_CNTFRQ_EL0:
1056  return !cnthctl.el0pcten && !cnthctl.el0vcten;
1057  case MISCREG_CNTPCT:
1058  case MISCREG_CNTPCT_EL0:
1059  return !cnthctl.el0pcten;
1060  case MISCREG_CNTVCT:
1061  case MISCREG_CNTVCT_EL0:
1062  return !cnthctl.el0vcten;
1065  return !cnthctl.el0pten;
1068  return !cnthctl.el0vten;
1069  default:
1070  break;
1071  }
1072  return false;
1073 }
1074 
1075 bool
1077  ThreadContext *tc)
1078 {
1079  const AA64MMFR0 mmfr0 = tc->readMiscRegNoEffect(MISCREG_ID_AA64MMFR0_EL1);
1080  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1081  const RegVal cnthctl_val = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1082  const CNTHCTL cnthctl = cnthctl_val;
1083  const CNTHCTL_E2H cnthctl_e2h = cnthctl_val;
1084  switch (misc_reg) {
1085  case MISCREG_CNTPCT:
1086  case MISCREG_CNTPCT_EL0:
1087  return hcr.e2h ? !cnthctl_e2h.el1pcten : !cnthctl.el1pcten;
1088  case MISCREG_CNTVCT:
1089  case MISCREG_CNTVCT_EL0:
1090  if (!mmfr0.ecv)
1091  return false;
1092  else
1093  return hcr.e2h ? cnthctl_e2h.el1tvct : cnthctl.el1tvct;
1096  return hcr.e2h ? !cnthctl_e2h.el1pten : false;
1099  if (!mmfr0.ecv)
1100  return false;
1101  else
1102  return hcr.e2h ? cnthctl_e2h.el1tvt : cnthctl.el1tvt;
1103  default:
1104  break;
1105  }
1106  return false;
1107 }
1108 
1109 bool
1111  ThreadContext *tc)
1112 {
1113  const CNTHCTL cnthctl = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1114  return !cnthctl.el1pcen;
1115 }
1116 
1117 bool
1119  ThreadContext *tc)
1120 {
1121  switch (misc_reg) {
1123  {
1124  const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
1125  return currEL(tc) == EL1 && !scr.ns && !scr.st;
1126  }
1127  default:
1128  break;
1129  }
1130  return false;
1131 }
1132 
1133 bool
1134 decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx,
1135  CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
1136 {
1138  bool ok = true;
1139 
1140  // R mostly indicates if its a int register or a misc reg, we override
1141  // below if the few corner cases
1142  isIntReg = !r;
1143  // Loosely based on ARM ARM issue C section B9.3.10
1144  if (r) {
1145  switch (sysM) {
1146  case 0xE:
1147  regIdx = MISCREG_SPSR_FIQ;
1148  mode = MODE_FIQ;
1149  break;
1150  case 0x10:
1151  regIdx = MISCREG_SPSR_IRQ;
1152  mode = MODE_IRQ;
1153  break;
1154  case 0x12:
1155  regIdx = MISCREG_SPSR_SVC;
1156  mode = MODE_SVC;
1157  break;
1158  case 0x14:
1159  regIdx = MISCREG_SPSR_ABT;
1160  mode = MODE_ABORT;
1161  break;
1162  case 0x16:
1163  regIdx = MISCREG_SPSR_UND;
1164  mode = MODE_UNDEFINED;
1165  break;
1166  case 0x1C:
1167  regIdx = MISCREG_SPSR_MON;
1168  mode = MODE_MON;
1169  break;
1170  case 0x1E:
1171  regIdx = MISCREG_SPSR_HYP;
1172  mode = MODE_HYP;
1173  break;
1174  default:
1175  ok = false;
1176  break;
1177  }
1178  } else {
1179  int sysM4To3 = bits(sysM, 4, 3);
1180 
1181  if (sysM4To3 == 0) {
1182  mode = MODE_USER;
1183  regIdx = int_reg::regInMode(mode, bits(sysM, 2, 0) + 8);
1184  } else if (sysM4To3 == 1) {
1185  mode = MODE_FIQ;
1186  regIdx = int_reg::regInMode(mode, bits(sysM, 2, 0) + 8);
1187  } else if (sysM4To3 == 3) {
1188  if (bits(sysM, 1) == 0) {
1189  mode = MODE_MON;
1190  regIdx = int_reg::regInMode(mode, 14 - bits(sysM, 0));
1191  } else {
1192  mode = MODE_HYP;
1193  if (bits(sysM, 0) == 1) {
1194  regIdx = int_reg::regInMode(mode, 13); // R13 in HYP
1195  } else {
1196  isIntReg = false;
1197  regIdx = MISCREG_ELR_HYP;
1198  }
1199  }
1200  } else { // Other Banked registers
1201  int sysM2 = bits(sysM, 2);
1202  int sysM1 = bits(sysM, 1);
1203 
1204  mode = (OperatingMode)(((sysM2 || sysM1) << 0) |
1205  (1 << 1) |
1206  ((sysM2 && !sysM1) << 2) |
1207  ((sysM2 && sysM1) << 3) |
1208  (1 << 4));
1209  regIdx = int_reg::regInMode(mode, 14 - bits(sysM, 0));
1210  // Don't flatten the register here. This is going to go through
1211  // setReg() which will do the flattening
1212  ok &= mode != cpsr.mode;
1213  }
1214  }
1215 
1216  // Check that the requested register is accessable from the current mode
1217  if (ok && checkSecurity && mode != cpsr.mode) {
1218  switch (cpsr.mode) {
1219  case MODE_USER:
1220  ok = false;
1221  break;
1222  case MODE_FIQ:
1223  ok &= mode != MODE_HYP;
1224  ok &= (mode != MODE_MON) || !scr.ns;
1225  break;
1226  case MODE_HYP:
1227  ok &= mode != MODE_MON;
1228  ok &= (mode != MODE_FIQ) || !nsacr.rfr;
1229  break;
1230  case MODE_IRQ:
1231  case MODE_SVC:
1232  case MODE_ABORT:
1233  case MODE_UNDEFINED:
1234  case MODE_SYSTEM:
1235  ok &= mode != MODE_HYP;
1236  ok &= (mode != MODE_MON) || !scr.ns;
1237  ok &= (mode != MODE_FIQ) || !nsacr.rfr;
1238  break;
1239  // can access everything, no further checks required
1240  case MODE_MON:
1241  break;
1242  default:
1243  panic("unknown Mode 0x%x\n", cpsr.mode);
1244  break;
1245  }
1246  }
1247  return ok;
1248 }
1249 
1250 bool
1252 {
1253  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1254  const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1255 
1256  // NV Extension not implemented yet
1257  bool have_nv_ext = false;
1258  bool unpriv_el1 = currEL(tc) == EL1 &&
1259  !(ArmSystem::haveEL(tc, EL2) &&
1260  have_nv_ext && hcr.nv == 1 && hcr.nv1 == 1);
1261  bool unpriv_el2 = ArmSystem::haveEL(tc, EL2) &&
1262  HaveExt(tc, ArmExtension::FEAT_VHE) &&
1263  currEL(tc) == EL2 && hcr.e2h == 1 && hcr.tge == 1;
1264 
1265  return (unpriv_el1 || unpriv_el2) && !cpsr.uao;
1266 }
1267 
1268 bool
1270 {
1271  ExceptionLevel regime = s1TranslationRegime(tc, currEL(tc));
1272 
1273  switch (currEL(tc)) {
1274  case EL3:
1275  return ((SCTLR)tc->readMiscReg(MISCREG_SCTLR_EL3)).sa;
1276  case EL2:
1277  return ((SCTLR)tc->readMiscReg(MISCREG_SCTLR_EL2)).sa;
1278  case EL1:
1279  return ((SCTLR)tc->readMiscReg(MISCREG_SCTLR_EL1)).sa;
1280  case EL0:
1281  {
1282  SCTLR sc = (regime == EL2) ? tc->readMiscReg(MISCREG_SCTLR_EL2):
1284  return sc.sa0;
1285  }
1286  default:
1287  panic("Invalid exception level");
1288  break;
1289  }
1290 }
1291 
1292 int
1293 decodePhysAddrRange64(uint8_t pa_enc)
1294 {
1295  switch (pa_enc) {
1296  case 0x0:
1297  return 32;
1298  case 0x1:
1299  return 36;
1300  case 0x2:
1301  return 40;
1302  case 0x3:
1303  return 42;
1304  case 0x4:
1305  return 44;
1306  case 0x5:
1307  return 48;
1308  case 0x6:
1309  return 52;
1310  default:
1311  panic("Invalid phys. address range encoding");
1312  }
1313 }
1314 
1315 uint8_t
1317 {
1318  switch (pa_size) {
1319  case 32:
1320  return 0x0;
1321  case 36:
1322  return 0x1;
1323  case 40:
1324  return 0x2;
1325  case 42:
1326  return 0x3;
1327  case 44:
1328  return 0x4;
1329  case 48:
1330  return 0x5;
1331  case 52:
1332  return 0x6;
1333  default:
1334  panic("Invalid phys. address range");
1335  }
1336 }
1337 
1338 void
1340 {
1341  int ei = 0;
1342  for (int ri = 0; ri < NumVecRegs; ri++) {
1343  RegId reg_id(VecRegClass, ri);
1345  tc->getReg(reg_id, &reg);
1346  for (int j = 0; j < NumVecElemPerVecReg; j++, ei++) {
1347  RegId elem_id(VecElemClass, ei);
1348  tc->setReg(elem_id, reg.as<VecElem>()[j]);
1349  }
1350  }
1351 }
1352 
1353 void
1355 {
1356  int ei = 0;
1357  for (int ri = 0; ri < NumVecRegs; ri++) {
1359  for (int j = 0; j < NumVecElemPerVecReg; j++, ei++) {
1360  RegId elem_id(VecElemClass, ei);
1361  reg.as<VecElem>()[j] = tc->getReg(elem_id);
1362  }
1363  RegId reg_id(VecRegClass, ri);
1364  tc->setReg(reg_id, &reg);
1365  }
1366 }
1367 
1368 } // namespace ArmISA
1369 } // namespace gem5
gem5::ArmISA::MISCREG_DCCMVAU
@ MISCREG_DCCMVAU
Definition: misc.hh:317
gem5::ArmISA::MISCREG_DFAR
@ MISCREG_DFAR
Definition: misc.hh:284
gem5::ArmISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition: vec.hh:58
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ArmISA::MISCREG_ID_MMFR4
@ MISCREG_ID_MMFR4
Definition: misc.hh:220
gem5::ArmISA::mcrMrcIssExtract
static void mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, RegIndex &rt, uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
Definition: utility.hh:246
gem5::ArmISA::MISCREG_TLBIMVALIS
@ MISCREG_TLBIMVALIS
Definition: misc.hh:326
gem5::ArmISA::MISCREG_PMCR
@ MISCREG_PMCR
Definition: misc.hh:352
gem5::ArmISA::MISCREG_CNTV_TVAL
@ MISCREG_CNTV_TVAL
Definition: misc.hh:428
gem5::ArmISA::MISCREG_CSSELR
@ MISCREG_CSSELR
Definition: misc.hh:231
gem5::ArmISA::MISCREG_DCCMVAC
@ MISCREG_DCCMVAC
Definition: misc.hh:313
gem5::ArmISA::maskTaggedAddr
Addr maskTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el, int topbit)
Definition: utility.cc:455
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ArmISA::MODE_SVC
@ MODE_SVC
Definition: types.hh:291
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:253
gem5::ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:292
gem5::ArmISA::MISCREG_TLBIALL
@ MISCREG_TLBIALL
Definition: misc.hh:334
gem5::ArmISA::MISCREG_HSTR
@ MISCREG_HSTR
Definition: misc.hh:253
gem5::ArmISA::ELIs64
bool ELIs64(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:273
gem5::ArmISA::MISCREG_ID_ISAR5
@ MISCREG_ID_ISAR5
Definition: misc.hh:226
gem5::ArmISA::getAffinity
Affinity getAffinity(ArmSystem *arm_sys, ThreadContext *tc)
Retrieves MPIDR_EL1.
Definition: utility.cc:219
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ArmISA::MISCREG_SCTLR_EL3
@ MISCREG_SCTLR_EL3
Definition: misc.hh:592
gem5::ArmISA::MISCREG_ICIALLU
@ MISCREG_ICIALLU
Definition: misc.hh:298
gem5::ArmISA::MODE_FIQ
@ MODE_FIQ
Definition: types.hh:289
gem5::ArmISA::MISCREG_CNTPS_CTL_EL1
@ MISCREG_CNTPS_CTL_EL1
Definition: misc.hh:771
gem5::ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:183
gem5::ArmISA::MISCREG_TTBR0
@ MISCREG_TTBR0
Definition: misc.hh:255
gem5::ArmISA::MISCREG_CNTVCT
@ MISCREG_CNTVCT
Definition: misc.hh:416
gem5::ArmISA::NumVecRegs
const int NumVecRegs
Definition: vec.hh:80
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:73
gem5::ArmISA::MISCREG_CNTFRQ
@ MISCREG_CNTFRQ
Definition: misc.hh:414
gem5::ArmISA::MISCREG_CONTEXTIDR
@ MISCREG_CONTEXTIDR
Definition: misc.hh:400
gem5::ArmISA::MISCREG_CNTV_CTL_EL0
@ MISCREG_CNTV_CTL_EL0
Definition: misc.hh:760
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:63
gem5::ArmISA::isGenericTimerPhysEL1SystemAccessTrapEL2
bool isGenericTimerPhysEL1SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:1015
gem5::ArmISA::MISCREG_TCR_EL2
@ MISCREG_TCR_EL2
Definition: misc.hh:605
gem5::ArmISA::MISCREG_CNTPS_TVAL_EL1
@ MISCREG_CNTPS_TVAL_EL1
Definition: misc.hh:773
gem5::ArmISA::MISCREG_SPSR_FIQ
@ MISCREG_SPSR_FIQ
Definition: misc.hh:63
gem5::ArmISA::MISCREG_CNTP_CTL_EL0
@ MISCREG_CNTP_CTL_EL0
Definition: misc.hh:757
gem5::ArmISA::MISCREG_ITLBIMVA
@ MISCREG_ITLBIMVA
Definition: misc.hh:329
warn_once
#define warn_once(...)
Definition: logging.hh:250
gem5::ThreadContext::getReg
virtual RegVal getReg(const RegId &reg) const
Definition: thread_context.cc:171
gem5::ArmISA::MISCREG_MDCR_EL2
@ MISCREG_MDCR_EL2
Definition: misc.hh:588
gem5::ArmISA::isGenericTimerHypTrap
bool isGenericTimerHypTrap(const MiscRegIndex misc_reg, ThreadContext *tc, ExceptionClass *ec)
Definition: utility.cc:819
gem5::ArmISA::tbi
Bitfield< 20 > tbi
Definition: misc_types.hh:515
gem5::ArmISA::MISCREG_TLBIMVAAL
@ MISCREG_TLBIMVAAL
Definition: misc.hh:339
gem5::ArmISA::ISA
Definition: isa.hh:68
gem5::ArmISA::MISCREG_DCCSW
@ MISCREG_DCCSW
Definition: misc.hh:314
gem5::ArmISA::decodePhysAddrRange64
int decodePhysAddrRange64(uint8_t pa_enc)
Returns the n.
Definition: utility.cc:1293
gem5::ArmISA::MODE_UNDEFINED
@ MODE_UNDEFINED
Definition: types.hh:295
gem5::ArmISA::EC_TRAPPED_CP15_MCR_MRC
@ EC_TRAPPED_CP15_MCR_MRC
Definition: types.hh:305
gem5::ArmISA::MODE_IRQ
@ MODE_IRQ
Definition: types.hh:290
gem5::ArmISA::iss
Bitfield< 24, 0 > iss
Definition: misc_types.hh:672
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: misc.hh:594
gem5::ArmISA::isGenericTimerSystemAccessTrapEL1
bool isGenericTimerSystemAccessTrapEL1(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:883
gem5::ArmISA::isGenericTimerCommonEL0HypTrap
bool isGenericTimerCommonEL0HypTrap(const MiscRegIndex misc_reg, ThreadContext *tc, ExceptionClass *ec)
Definition: utility.cc:845
gem5::ArmISA::encodePhysAddrRange64
uint8_t encodePhysAddrRange64(int pa_size)
Returns the encoding corresponding to the specified n.
Definition: utility.cc:1316
gem5::ArmISA::MISCREG_ICIMVAU
@ MISCREG_ICIMVAU
Definition: misc.hh:299
gem5::replaceBits
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
gem5::ArmISA::isSecureBelowEL3
bool isSecureBelowEL3(ThreadContext *tc)
Definition: utility.cc:85
gem5::ArmISA::isGenericTimerSystemAccessTrapEL2
bool isGenericTimerSystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:943
gem5::ArmISA::MISCREG_TTBCR
@ MISCREG_TTBCR
Definition: misc.hh:261
gem5::ArmISA::MISCREG_TLBIMVAL
@ MISCREG_TLBIMVAL
Definition: misc.hh:338
gem5::ArmISA::MISCREG_JOSCR
@ MISCREG_JOSCR
Definition: misc.hh:202
gem5::ArmISA::MISCREG_DCISW
@ MISCREG_DCISW
Definition: misc.hh:304
gem5::ArmISA::MISCREG_TLBIALLIS
@ MISCREG_TLBIALLIS
Definition: misc.hh:322
gem5::ArmISA::MISCREG_TLBTR
@ MISCREG_TLBTR
Definition: misc.hh:209
gem5::ArmISA::mcrrMrrc15TrapToHyp
bool mcrrMrrc15TrapToHyp(const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec)
Definition: utility.cc:731
gem5::ArmISA::MISCREG_ITLBIASID
@ MISCREG_ITLBIASID
Definition: misc.hh:330
gem5::ArmISA::MISCREG_TCR_EL3
@ MISCREG_TCR_EL3
Definition: misc.hh:611
gem5::ArmISA::ns
Bitfield< 0 > ns
Definition: misc_types.hh:332
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:274
gem5::ArmISA::MISCREG_ID_ISAR3
@ MISCREG_ID_ISAR3
Definition: misc.hh:224
gem5::ArmISA::MISCREG_ID_AA64MMFR0_EL1
@ MISCREG_ID_AA64MMFR0_EL1
Definition: misc.hh:570
gem5::ArmISA::MISCREG_ID_MMFR3
@ MISCREG_ID_MMFR3
Definition: misc.hh:219
vec.hh
gem5::ArmISA::opModeToEL
static ExceptionLevel opModeToEL(OperatingMode mode)
Definition: types.hh:390
gem5::ArmISA::MISCREG_SPSR_MON
@ MISCREG_SPSR_MON
Definition: misc.hh:66
gem5::ArmISA::MISCREG_DBGOSLAR
@ MISCREG_DBGOSLAR
Definition: misc.hh:188
gem5::ArmISA::ELIsInHost
bool ELIsInHost(ThreadContext *tc, ExceptionLevel el)
Returns true if the current exception level el is executing a Host OS or an application of a Host OS ...
Definition: utility.cc:287
gem5::ArmISA::isAArch64AArch32SystemAccessTrapEL2
bool isAArch64AArch32SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:929
gem5::ArmISA::MISCREG_DCCISW
@ MISCREG_DCCISW
Definition: misc.hh:319
gem5::ArmISA::inAArch64
bool inAArch64(ThreadContext *tc)
Definition: utility.cc:122
gem5::ArmISA::MISCREG_ID_ISAR1
@ MISCREG_ID_ISAR1
Definition: misc.hh:222
gem5::VegaISA::r
Bitfield< 5 > r
Definition: pagetable.hh:60
gem5::ArmISA::opc2
Bitfield< 7, 5 > opc2
Definition: types.hh:106
gem5::ArmISA::badMode
bool badMode(ThreadContext *tc, OperatingMode mode)
badMode is checking if the execution mode provided as an argument is valid and implemented.
Definition: utility.cc:403
system.hh
gem5::ArmISA::MISCREG_SCTLR
@ MISCREG_SCTLR
Definition: misc.hh:236
gem5::ArmISA::MISCREG_CNTVCT_EL0
@ MISCREG_CNTVCT_EL0
Definition: misc.hh:756
gem5::ArmISA::MISCREG_CNTPCT_EL0
@ MISCREG_CNTPCT_EL0
Definition: misc.hh:755
gem5::ArmISA::MISCREG_CNTP_CTL
@ MISCREG_CNTP_CTL
Definition: misc.hh:417
gem5::ThreadContext::cpuId
virtual int cpuId() const =0
cc.hh
gem5::ArmISA::MISCREG_JIDR
@ MISCREG_JIDR
Definition: misc.hh:200
gem5::ArmISA::AArch64AArch32SystemAccessTrap
Fault AArch64AArch32SystemAccessTrap(const MiscRegIndex misc_reg, ExtMachInst mach_inst, ThreadContext *tc, uint32_t imm, ExceptionClass ec)
Definition: utility.cc:791
gem5::ArmISA::truncPage
Addr truncPage(Addr addr)
Definition: utility.cc:489
gem5::ArmISA::MISCREG_ID_MMFR1
@ MISCREG_ID_MMFR1
Definition: misc.hh:217
gem5::ArmISA::ELUsingAArch32K
std::pair< bool, bool > ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
This function checks whether selected EL provided as an argument is using the AArch32 ISA.
Definition: utility.cc:298
gem5::ArmISA::condGenericTimerCommonEL0SystemAccessTrapEL2
bool condGenericTimerCommonEL0SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:1049
gem5::ArmISA::condGenericTimerSystemAccessTrapEL1
bool condGenericTimerSystemAccessTrapEL1(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:902
gem5::ArmISA::mcrMrc14TrapToHyp
bool mcrMrc14TrapToHyp(const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss)
Definition: utility.cc:666
gem5::ArmISA::MISCREG_JMCR
@ MISCREG_JMCR
Definition: misc.hh:203
gem5::ArmISA::MISCREG_DACR
@ MISCREG_DACR
Definition: misc.hh:266
gem5::ArmISA::MISCREG_HCPTR
@ MISCREG_HCPTR
Definition: misc.hh:252
gem5::ArmISA::MISCREG_ID_ISAR0
@ MISCREG_ID_ISAR0
Definition: misc.hh:221
gem5::ArmISA::MISCREG_CNTKCTL_EL1
@ MISCREG_CNTKCTL_EL1
Definition: misc.hh:769
gem5::ArmISA::ec
ec
Definition: misc_types.hh:670
gem5::ArmISA::mcrMrc15Trap
Fault mcrMrc15Trap(const MiscRegIndex misc_reg, ExtMachInst mach_inst, ThreadContext *tc, uint32_t imm)
Definition: utility.cc:501
gem5::ArmISA::purifyTaggedAddr
Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el, TCR tcr, bool is_instr)
Removes the tag from tagged addresses if that mode is enabled.
Definition: utility.cc:470
gem5::ArmISA::MISCREG_DBGDSAR
@ MISCREG_DBGDSAR
Definition: misc.hh:192
gem5::ArmISA::MISCREG_ID_MMFR2
@ MISCREG_ID_MMFR2
Definition: misc.hh:218
gem5::ArmISA::MISCREG_IFSR
@ MISCREG_IFSR
Definition: misc.hh:272
gem5::ArmISA::unknownMode32
static bool unknownMode32(OperatingMode mode)
Definition: types.hh:445
gem5::ArmISA::MISCREG_DTLBIASID
@ MISCREG_DTLBIASID
Definition: misc.hh:333
mmu.hh
gem5::ArmISA::isGenericTimerCommonEL0SystemAccessTrapEL2
bool isGenericTimerCommonEL0SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:977
gem5::ArmRelease::has
bool has(ArmExtension ext) const
Definition: system.hh:75
gem5::ArmISA::MISCREG_CNTHCTL_EL2
@ MISCREG_CNTHCTL_EL2
Definition: misc.hh:774
gem5::ArmISA::j
Bitfield< 24 > j
Definition: misc_types.hh:57
gem5::ArmISA::MISCREG_CNTVOFF
@ MISCREG_CNTVOFF
Definition: misc.hh:434
gem5::ArmISA::MISCREG_DTLBIMVA
@ MISCREG_DTLBIMVA
Definition: misc.hh:332
gem5::ArmISA::getAff1
static RegVal getAff1(ArmSystem *arm_sys, ThreadContext *tc)
Definition: utility.cc:207
gem5::ArmSystem::multiProc
bool multiProc
true if this a multiprocessor system
Definition: system.hh:150
gem5::ArmISA::MISCREG_PRRR
@ MISCREG_PRRR
Definition: misc.hh:370
gem5::ArmISA::getAff2
static RegVal getAff2(ArmSystem *arm_sys, ThreadContext *tc)
Definition: utility.cc:201
gem5::ArmISA::MISCREG_DBGDRAR
@ MISCREG_DBGDRAR
Definition: misc.hh:171
gem5::ArmSystem::highestEL
ArmISA::ExceptionLevel highestEL() const
Returns the highest implemented exception level.
Definition: system.hh:187
gem5::VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:123
gem5::ThreadContext::socketId
virtual uint32_t socketId() const =0
interrupts.hh
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ArmISA::EC_UNKNOWN
@ EC_UNKNOWN
Definition: types.hh:303
gem5::ArmISA::MODE_HYP
@ MODE_HYP
Definition: types.hh:294
gem5::ArmISA::mcrrMrrc15Trap
Fault mcrrMrrc15Trap(const MiscRegIndex misc_reg, ExtMachInst mach_inst, ThreadContext *tc, uint32_t imm)
Definition: utility.cc:721
gem5::ArmISA::condGenericTimerPhysHypTrap
bool condGenericTimerPhysHypTrap(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:868
gem5::ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition: misc.hh:580
gem5::ArmISA::MISCREG_ID_ISAR2
@ MISCREG_ID_ISAR2
Definition: misc.hh:223
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::ArmISA::MISCREG_HDCR
@ MISCREG_HDCR
Definition: misc.hh:251
gem5::ArmISA::MISCREG_ID_ISAR4
@ MISCREG_ID_ISAR4
Definition: misc.hh:225
gem5::PowerISA::ri
Bitfield< 1 > ri
Definition: misc.hh:120
gem5::ArmISA::roundPage
Addr roundPage(Addr addr)
Definition: utility.cc:495
gem5::ArmISA::rt
Bitfield< 15, 12 > rt
Definition: types.hh:115
gem5::ArmISA::MISCREG_MAIR1
@ MISCREG_MAIR1
Definition: misc.hh:379
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:275
gem5::ArmISA::MISCREG_CNTPCT
@ MISCREG_CNTPCT
Definition: misc.hh:415
gem5::ArmISA::MISCREG_SPSR_IRQ
@ MISCREG_SPSR_IRQ
Definition: misc.hh:64
gem5::ArmISA::MISCREG_SCTLR_EL2
@ MISCREG_SCTLR_EL2
Definition: misc.hh:585
gem5::ArmISA::unknownMode
static bool unknownMode(OperatingMode mode)
Definition: types.hh:419
gem5::ArmISA::EC_TRAPPED_CP15_MCRR_MRRC
@ EC_TRAPPED_CP15_MCRR_MRRC
Definition: types.hh:306
gem5::ArmISA::ELIs32
bool ELIs32(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:279
gem5::ArmISA::MISCREG_CCSIDR
@ MISCREG_CCSIDR
Definition: misc.hh:228
cpu.hh
gem5::ArmISA::syncVecElemsToRegs
void syncVecElemsToRegs(ThreadContext *tc)
Definition: utility.cc:1354
gem5::ArmISA::MISCREG_ICIALLUIS
@ MISCREG_ICIALLUIS
Definition: misc.hh:293
port_proxy.hh
gem5::ArmISA::MISCREG_DCCIMVAC
@ MISCREG_DCCIMVAC
Definition: misc.hh:318
gem5::ArmISA::tbid
Bitfield< 29 > tbid
Definition: misc_types.hh:538
gem5::ArmISA::EL2Enabled
bool EL2Enabled(ThreadContext *tc)
Definition: utility.cc:264
gem5::ArmISA::MISCREG_TEEHBR
@ MISCREG_TEEHBR
Definition: misc.hh:201
gem5::ArmISA::MISCREG_ACTLR
@ MISCREG_ACTLR
Definition: misc.hh:239
gem5::ArmISA::MISCREG_IFAR
@ MISCREG_IFAR
Definition: misc.hh:287
gem5::ArmISA::MISCREG_ICC_ASGI1R
@ MISCREG_ICC_ASGI1R
Definition: misc.hh:976
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition: pcstate.hh:63
gem5::ArmISA::MISCREG_ID_AFR0
@ MISCREG_ID_AFR0
Definition: misc.hh:215
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
compiler.hh
gem5::ArmISA::SPAlignmentCheckEnabled
bool SPAlignmentCheckEnabled(ThreadContext *tc)
Definition: utility.cc:1269
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:276
gem5::ArmISA::mcrMrc15TrapToHyp
bool mcrMrc15TrapToHyp(const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec)
Definition: utility.cc:511
gem5::ArmISA::ext
Bitfield< 12 > ext
Definition: misc_types.hh:428
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::ArmISA::MODE_USER
@ MODE_USER
Definition: types.hh:288
gem5::ArmISA::MISCREG_DBGPRCR
@ MISCREG_DBGPRCR
Definition: misc.hh:191
std::pair
STL pair class.
Definition: stl.hh:58
gem5::ArmISA::MISCREG_ID_PFR1
@ MISCREG_ID_PFR1
Definition: misc.hh:213
gem5::ArmISA::s1TranslationRegime
ExceptionLevel s1TranslationRegime(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:236
faults.hh
gem5::ArmISA::debugTargetFrom
ExceptionLevel debugTargetFrom(ThreadContext *tc, bool secure)
Definition: utility.cc:92
gem5::ArmISA::MISCREG_ICC_SGI1R
@ MISCREG_ICC_SGI1R
Definition: misc.hh:1002
gem5::ArmISA::MISCREG_TCMTR
@ MISCREG_TCMTR
Definition: misc.hh:208
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::MISCREG_TLBIMVA
@ MISCREG_TLBIMVA
Definition: misc.hh:335
gem5::ArmISA::MISCREG_DBGOSDLR
@ MISCREG_DBGOSDLR
Definition: misc.hh:190
gem5::ArmISA::MISCREG_DFSR
@ MISCREG_DFSR
Definition: misc.hh:269
gem5::ArmISA::MISCREG_NMRR
@ MISCREG_NMRR
Definition: misc.hh:376
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmISA::MISCREG_CNTP_TVAL_EL0
@ MISCREG_CNTP_TVAL_EL0
Definition: misc.hh:759
gem5::ArmISA::MISCREG_TTBR1
@ MISCREG_TTBR1
Definition: misc.hh:258
gem5::ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:73
gem5::ArmISA::ELStateUsingAArch32K
std::pair< bool, bool > ELStateUsingAArch32K(ThreadContext *tc, ExceptionLevel el, bool secure)
Definition: utility.cc:319
utility.hh
gem5::ArmISA::ExceptionClass
ExceptionClass
Definition: types.hh:300
full_system.hh
gem5::ArmISA::MISCREG_MAIR0
@ MISCREG_MAIR0
Definition: misc.hh:373
gem5::ArmISA::currEL
ExceptionLevel currEL(const ThreadContext *tc)
Returns the current Exception Level (EL) of the provided ThreadContext.
Definition: utility.cc:129
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::X86ISA::ExtMachInst
Definition: types.hh:212
gem5::ArmISA::MISCREG_TLBIASIDIS
@ MISCREG_TLBIASIDIS
Definition: misc.hh:324
gem5::System::multiThread
const bool multiThread
Definition: system.hh:316
gem5::ArmSystem::has
bool has(ArmExtension ext) const
Definition: system.hh:154
gem5::ArmISA::MISCREG_AIDR
@ MISCREG_AIDR
Definition: misc.hh:230
gem5::ArmISA::MISCREG_ICC_SGI0R
@ MISCREG_ICC_SGI0R
Definition: misc.hh:1001
gem5::ArmISA::IsSecureEL2Enabled
bool IsSecureEL2Enabled(ThreadContext *tc)
Definition: utility.cc:250
gem5::ArmISA::MISCREG_AIFSR
@ MISCREG_AIFSR
Definition: misc.hh:278
gem5::ArmISA::MISCREG_DCIMVAC
@ MISCREG_DCIMVAC
Definition: misc.hh:303
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:273
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
gem5::ArmISA::MISCREG_CTR
@ MISCREG_CTR
Definition: misc.hh:207
gem5::ArmSystem
Definition: system.hh:91
gem5::ArmISA::imm
Bitfield< 7, 0 > imm
Definition: types.hh:132
gem5::ArmISA::MISCREG_TEECR
@ MISCREG_TEECR
Definition: misc.hh:199
gem5::ArmISA::MISCREG_DTLBIALL
@ MISCREG_DTLBIALL
Definition: misc.hh:331
gem5::ArmISA::MISCREG_HCR
@ MISCREG_HCR
Definition: misc.hh:249
gem5::ArmISA::MISCREG_ADFSR
@ MISCREG_ADFSR
Definition: misc.hh:275
inform
#define inform(...)
Definition: logging.hh:247
gem5::ArmISA::syncVecRegsToElems
void syncVecRegsToElems(ThreadContext *tc)
Definition: utility.cc:1339
gem5::ArmISA::decodeMrsMsrBankedReg
bool decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx, CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
Definition: utility.cc:1134
gem5::ArmISA::MISCREG_SPSR_SVC
@ MISCREG_SPSR_SVC
Definition: misc.hh:65
gem5::ArmISA::isUnpriviledgeAccess
bool isUnpriviledgeAccess(ThreadContext *tc)
Definition: utility.cc:1251
base.hh
gem5::ArmISA::VecElem
uint32_t VecElem
Definition: vec.hh:60
gem5::ArmISA::MISCREG_CLIDR
@ MISCREG_CLIDR
Definition: misc.hh:229
gem5::ArmISA::getAff0
static RegVal getAff0(ArmSystem *arm_sys, ThreadContext *tc)
Definition: utility.cc:213
gem5::ArmISA::isGenericTimerSystemAccessTrapEL3
bool isGenericTimerSystemAccessTrapEL3(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:1118
gem5::ArmISA::MISCREG_TLBIMVAALIS
@ MISCREG_TLBIMVAALIS
Definition: misc.hh:327
gem5::ArmISA::sendEvent
void sendEvent(ThreadContext *tc)
Send an event (SEV) to a specific PE if there isn't already a pending event.
Definition: utility.cc:64
gem5::ArmISA::ELStateUsingAArch32
bool ELStateUsingAArch32(ThreadContext *tc, ExceptionLevel el, bool secure)
Definition: utility.cc:371
gem5::ArmISA::MISCREG_DBGOSLSR
@ MISCREG_DBGOSLSR
Definition: misc.hh:189
gem5::ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition: misc.hh:244
gem5::ArmISA::longDescFormatInUse
bool longDescFormatInUse(ThreadContext *tc)
Definition: utility.cc:136
gem5::ArmISA::MISCREG_ID_PFR0
@ MISCREG_ID_PFR0
Definition: misc.hh:212
gem5::ArmISA::MODE_SYSTEM
@ MODE_SYSTEM
Definition: types.hh:296
gem5::ArmISA::PageBytes
const Addr PageBytes
Definition: page_size.hh:53
gem5::ArmISA::MISCREG_VMPIDR_EL2
@ MISCREG_VMPIDR_EL2
Definition: misc.hh:579
gem5::ArmISA::MISCREG_REVIDR
@ MISCREG_REVIDR
Definition: misc.hh:211
gem5::ArmISA::badMode32
bool badMode32(ThreadContext *tc, OperatingMode mode)
badMode is checking if the execution mode provided as an argument is valid and implemented for AArch3...
Definition: utility.cc:397
gem5::ArmISA::MISCREG_SPSR_ABT
@ MISCREG_SPSR_ABT
Definition: misc.hh:67
gem5::ArmISA::MISCREG_ELR_HYP
@ MISCREG_ELR_HYP
Definition: misc.hh:70
gem5::ArmISA::haveAArch32EL
bool haveAArch32EL(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:305
gem5::ArmISA::isGenericTimerVirtSystemAccessTrapEL2
bool isGenericTimerVirtSystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:1039
gem5::ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
gem5::ArmISA::MISCREG_SEV_MAILBOX
@ MISCREG_SEV_MAILBOX
Definition: misc.hh:92
gem5::ThreadContext::threadId
virtual int threadId() const =0
gem5::ArmISA::MISCREG_ID_ISAR6
@ MISCREG_ID_ISAR6
Definition: misc.hh:227
gem5::ArmISA::MISCREG_CNTP_TVAL_S
@ MISCREG_CNTP_TVAL_S
Definition: misc.hh:425
gem5::ArmISA::condGenericTimerPhysEL1SystemAccessTrapEL2
bool condGenericTimerPhysEL1SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:1110
page_size.hh
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:61
gem5::ArmISA::MISCREG_CNTFRQ_EL0
@ MISCREG_CNTFRQ_EL0
Definition: misc.hh:754
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr() const =0
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::ArmISA::MISCREG_TLBIMVAIS
@ MISCREG_TLBIMVAIS
Definition: misc.hh:323
gem5::ArmSystem::haveEL
static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el)
Return true if the system implements a specific exception level.
Definition: system.cc:131
gem5::ArmISA::MODE_ABORT
@ MODE_ABORT
Definition: types.hh:293
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: misc.hh:587
gem5::ArmISA::condGenericTimerCommonEL1SystemAccessTrapEL2
bool condGenericTimerCommonEL1SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:1076
gem5::ArmISA::MISCREG_TLBIASID
@ MISCREG_TLBIASID
Definition: misc.hh:336
gem5::ArmISA::MISCREG_TLBIMVAA
@ MISCREG_TLBIMVAA
Definition: misc.hh:337
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ArmISA::MISCREG_TLBIMVAAIS
@ MISCREG_TLBIMVAAIS
Definition: misc.hh:325
gem5::ArmISA::computeAddrTop
int computeAddrTop(ThreadContext *tc, bool selbit, bool is_instr, TCR tcr, ExceptionLevel el)
Definition: utility.cc:409
gem5::ArmISA::isGenericTimerPhysHypTrap
bool isGenericTimerPhysHypTrap(const MiscRegIndex misc_reg, ThreadContext *tc, ExceptionClass *ec)
Definition: utility.cc:861
gem5::ArmISA::MISCREG_CNTV_CTL
@ MISCREG_CNTV_CTL
Definition: misc.hh:426
gem5::ArmISA::isBigEndian64
bool isBigEndian64(const ThreadContext *tc)
Definition: utility.cc:379
gem5::ArmISA::isAArch64AArch32SystemAccessTrapEL1
bool isAArch64AArch32SystemAccessTrapEL1(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:805
gem5::ArmISA::ISA::getRelease
const ArmRelease * getRelease() const
Definition: isa.hh:641
gem5::ArmISA::MISCREG_ID_MMFR0
@ MISCREG_ID_MMFR0
Definition: misc.hh:216
int.hh
gem5::ArmISA::MISCREG_CPACR
@ MISCREG_CPACR
Definition: misc.hh:242
gem5::ArmISA::HaveExt
bool HaveExt(ThreadContext *tc, ArmExtension ext)
Returns true if the provided ThreadContext supports the ArmExtension passed as a second argument.
Definition: utility.cc:229
gem5::ArmISA::MISCREG_SPSR_HYP
@ MISCREG_SPSR_HYP
Definition: misc.hh:68
gem5::ArmISA::eel2
Bitfield< 18 > eel2
Definition: misc_types.hh:313
gem5::ArmISA::isGenericTimerPhysEL0SystemAccessTrapEL2
bool isGenericTimerPhysEL0SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:990
thread_context.hh
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:279
gem5::ArmISA::readMPIDR
RegVal readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
This helper function is either returing the value of MPIDR_EL1 (by calling getMPIDR),...
Definition: utility.cc:143
gem5::ArmISA::MISCREG_ID_DFR0
@ MISCREG_ID_DFR0
Definition: misc.hh:214
gem5::ArmISA::MISCREG_ITLBIALL
@ MISCREG_ITLBIALL
Definition: misc.hh:328
gem5::ArmISA::unflattenMiscReg
int unflattenMiscReg(int reg)
Definition: misc.cc:718
gem5::ArmISA::getMPIDR
RegVal getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
This helper function is returning the value of MPIDR_EL1.
Definition: utility.cc:171
gem5::ArmISA::MISCREG_TCR_EL1
@ MISCREG_TCR_EL1
Definition: misc.hh:602
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:271
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::ArmISA::INT_SEV
@ INT_SEV
Definition: interrupts.hh:65
gem5::ArmISA::MISCREG_CNTV_TVAL_EL0
@ MISCREG_CNTV_TVAL_EL0
Definition: misc.hh:762
gem5::ThreadContext::setReg
virtual void setReg(const RegId &reg, RegVal val)
Definition: thread_context.cc:183
gem5::ArmISA::MISCREG_SPSR_UND
@ MISCREG_SPSR_UND
Definition: misc.hh:69

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