gem5  v21.1.0.2
utility.cc
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1 /*
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37 
38 #include "arch/arm/utility.hh"
39 
40 #include <memory>
41 
42 #include "arch/arm/faults.hh"
43 #include "arch/arm/interrupts.hh"
44 #include "arch/arm/mmu.hh"
45 #include "arch/arm/page_size.hh"
46 #include "arch/arm/regs/cc.hh"
47 #include "arch/arm/regs/int.hh"
48 #include "arch/arm/system.hh"
49 #include "base/compiler.hh"
50 #include "cpu/base.hh"
51 #include "cpu/checker/cpu.hh"
52 #include "cpu/thread_context.hh"
53 #include "mem/port_proxy.hh"
54 #include "sim/full_system.hh"
55 
56 namespace gem5
57 {
58 
59 namespace ArmISA
60 {
61 
62 void
64 {
65  if (tc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
66  // Post Interrupt and wake cpu if needed
67  tc->getCpuPtr()->postInterrupt(tc->threadId(), INT_SEV, 0);
68  }
69 }
70 
71 bool
73 {
74  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
75  if (ArmSystem::haveEL(tc, EL3) && !cpsr.width && currEL(tc) == EL3)
76  return true;
77  if (ArmSystem::haveEL(tc, EL3) && cpsr.width && cpsr.mode == MODE_MON)
78  return true;
79  else
80  return isSecureBelowEL3(tc);
81 }
82 
83 bool
85 {
86  SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
87  return ArmSystem::haveEL(tc, EL3) && scr.ns == 0;
88 }
89 
91 debugTargetFrom(ThreadContext *tc, bool secure)
92 {
93  bool route_to_el2;
94  if (ArmSystem::haveEL(tc, EL2) && (!secure || HaveSecureEL2Ext(tc))) {
95  if (ELIs32(tc, EL2)) {
96  const HCR hcr = tc->readMiscReg(MISCREG_HCR);
97  const HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
98  route_to_el2 = (hdcr.tde == 1 || hcr.tge == 1);
99  } else {
100  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
101  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
102  route_to_el2 = (mdcr.tde == 1 || hcr.tge == 1);
103  }
104  }else{
105  route_to_el2 = false;
106  }
107  ExceptionLevel target;
108  if (route_to_el2) {
109  target = EL2;
110  } else if (ArmSystem::haveEL(tc, EL3) && !ArmSystem::highestELIs64(tc)
111  && secure) {
112  target = EL3;
113  } else {
114  target = EL1;
115  }
116  return target;
117 }
118 
119 bool
121 {
122  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
123  return opModeIs64((OperatingMode) (uint8_t) cpsr.mode);
124 }
125 
126 bool
128 {
129  TTBCR ttbcr = tc->readMiscReg(MISCREG_TTBCR);
130  return ArmSystem::haveLPAE(tc) && ttbcr.eae;
131 }
132 
133 RegVal
135 {
136  const ExceptionLevel current_el = currEL(tc);
137 
138  const bool is_secure = isSecureBelowEL3(tc);
139 
140  switch (current_el) {
141  case EL0:
142  // Note: in MsrMrs instruction we read the register value before
143  // checking access permissions. This means that EL0 entry must
144  // be part of the table even if MPIDR is not accessible in user
145  // mode.
146  warn_once("Trying to read MPIDR at EL0\n");
148  case EL1:
149  if (ArmSystem::haveEL(tc, EL2) && !is_secure)
150  return tc->readMiscReg(MISCREG_VMPIDR_EL2);
151  else
152  return getMPIDR(arm_sys, tc);
153  case EL2:
154  case EL3:
155  return getMPIDR(arm_sys, tc);
156  default:
157  panic("Invalid EL for reading MPIDR register\n");
158  }
159 }
160 
161 RegVal
163 {
164  // Multiprocessor Affinity Register MPIDR from Cortex(tm)-A15 Technical
165  // Reference Manual
166  //
167  // bit 31 - Multi-processor extensions available
168  // bit 30 - Uni-processor system
169  // bit 24 - Multi-threaded cores
170  // bit 11-8 - Cluster ID
171  // bit 1-0 - CPU ID
172  //
173  // We deliberately extend both the Cluster ID and CPU ID fields to allow
174  // for simulation of larger systems
175  assert((0 <= tc->cpuId()) && (tc->cpuId() < 256));
176  assert(tc->socketId() < 65536);
177 
178  RegVal mpidr = 0x80000000;
179 
180  if (!arm_sys->multiProc)
181  replaceBits(mpidr, 30, 1);
182 
183  if (arm_sys->multiThread)
184  replaceBits(mpidr, 24, 1);
185 
186  // Get Affinity numbers
187  mpidr |= getAffinity(arm_sys, tc);
188  return mpidr;
189 }
190 
191 static RegVal
193 {
194  return arm_sys->multiThread ? tc->socketId() << 16 : 0;
195 }
196 
197 static RegVal
199 {
200  return arm_sys->multiThread ? tc->cpuId() << 8 : tc->socketId() << 8;
201 }
202 
203 static RegVal
205 {
206  return arm_sys->multiThread ? tc->threadId() : tc->cpuId();
207 }
208 
209 RegVal
211 {
212  return getAff2(arm_sys, tc) | getAff1(arm_sys, tc) | getAff0(arm_sys, tc);
213 }
214 
215 bool
217 {
218  AA64ISAR1 id_aa64isar1 = tc->readMiscReg(MISCREG_ID_AA64ISAR1_EL1);
219  return id_aa64isar1.api | id_aa64isar1.apa |
220  id_aa64isar1.gpi | id_aa64isar1.gpa;
221 }
222 
223 bool
225 {
226  AA64MMFR1 id_aa64mmfr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1);
227  return id_aa64mmfr1.vh;
228 }
229 
230 bool
232 {
233  const AA64MMFR2 mm_fr2 = tc->readMiscReg(MISCREG_ID_AA64MMFR2_EL1);
234  return (bool)mm_fr2.varange;
235 }
236 
239 {
240 
241  SCR scr = tc->readMiscReg(MISCREG_SCR);
242  if (el != EL0)
243  return el;
244  else if (ArmSystem::haveEL(tc, EL3) && ELIs32(tc, EL3) && scr.ns == 0)
245  return EL3;
246  else if (HaveVirtHostExt(tc) && ELIsInHost(tc, el))
247  return EL2;
248  else
249  return EL1;
250 }
251 
252 bool
254 {
255  AA64PFR0 id_aa64pfr0 = tc->readMiscReg(MISCREG_ID_AA64PFR0_EL1);
256  return id_aa64pfr0.sel2;
257 }
258 
259 bool
261 {
262  SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
263  if (ArmSystem::haveEL(tc, EL2) && HaveSecureEL2Ext(tc) &&
264  !ELIs32(tc, EL2)) {
265  if (ArmSystem::haveEL(tc, EL3))
266  return !ELIs32(tc, EL3) && scr.eel2;
267  else
268  return isSecure(tc);
269  }
270  return false;
271 }
272 
273 bool
275 {
276  SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
277  return ArmSystem::haveEL(tc, EL2) &&
278  (!ArmSystem::haveEL(tc, EL3) || scr.ns || IsSecureEL2Enabled(tc));
279 }
280 
281 bool
283 {
284  return !ELIs32(tc, el);
285 }
286 
287 bool
289 {
290  bool known, aarch32;
291  std::tie(known, aarch32) = ELUsingAArch32K(tc, el);
292  panic_if(!known, "EL state is UNKNOWN");
293  return aarch32;
294 }
295 
296 bool
298 {
299  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
300  return (ArmSystem::haveEL(tc, EL2) &&
301  (IsSecureEL2Enabled(tc) || !isSecureBelowEL3(tc)) &&
302  HaveVirtHostExt(tc) && !ELIs32(tc, EL2) && hcr.e2h == 1 &&
303  (el == EL2 || (el == EL0 && hcr.tge == 1)));
304 }
305 
308 {
309  bool secure = isSecureBelowEL3(tc);
310  return ELStateUsingAArch32K(tc, el, secure);
311 }
312 
313 bool
315 {
316  if (!ArmSystem::haveEL(tc, el))
317  return false;
318  else if (!ArmSystem::highestELIs64(tc))
319  return true;
320  else if (ArmSystem::highestEL(tc) == el)
321  return false;
322  else if (el == EL0)
323  return true;
324  return true;
325 }
326 
329 {
330  // Return true if the specified EL is in aarch32 state.
331  const bool have_el3 = ArmSystem::haveSecurity(tc);
332  const bool have_el2 = ArmSystem::haveVirtualization(tc);
333 
334  panic_if(el == EL2 && !have_el2, "Asking for EL2 when it doesn't exist");
335  panic_if(el == EL3 && !have_el3, "Asking for EL3 when it doesn't exist");
336 
337  bool known, aarch32;
338  known = aarch32 = false;
339  if (!haveAArch32EL(tc, el)) {
340  // Target EL is the highest one in a system where
341  // the highest is using AArch64.
342  known = true; aarch32 = false;
343  } else if (secure && el == EL2) {
344  known = true; aarch32 = false;
345  } else if (!ArmSystem::highestELIs64(tc)) {
346  // All ELs are using AArch32:
347  known = true; aarch32 = true;
348  } else if (ArmSystem::highestEL(tc) == el) {
349  known = true; aarch32 = false;
350  } else {
351  SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
352  bool aarch32_below_el3 = have_el3 && scr.rw == 0 &&
353  (!secure || !HaveSecureEL2Ext(tc) || !scr.eel2);
354 
355  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
356  bool sec_el2 = HaveSecureEL2Ext(tc) && scr.eel2;
357  bool aarch32_at_el1 = (aarch32_below_el3 ||
358  (have_el2 && (sec_el2 || !secure) &&
359  hcr.rw == 0 && !(hcr.e2h && hcr.tge &&
360  HaveVirtHostExt(tc))));
361 
362  // Only know if EL0 using AArch32 from PSTATE
363  if (el == EL0 && !aarch32_at_el1) {
364  // EL0 controlled by PSTATE
365  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
366  known = (currEL(tc) == EL0);
367  aarch32 = (cpsr.width == 1);
368  } else {
369  known = true;
370  aarch32 = (aarch32_below_el3 && el != EL3)
371  || (aarch32_at_el1 && (el == EL0 || el == EL1) );
372  }
373  }
374 
375  return std::make_pair(known, aarch32);
376 }
377 
379 {
380 
381  bool known, aarch32;
382  std::tie(known, aarch32) = ELStateUsingAArch32K(tc, el, secure);
383  panic_if(!known, "EL state is UNKNOWN");
384  return aarch32;
385 }
386 
387 bool
389 {
390  switch (currEL(tc)) {
391  case EL3:
392  return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL3)).ee;
393  case EL2:
394  return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL2)).ee;
395  case EL1:
396  return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL1)).ee;
397  case EL0:
398  return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL1)).e0e;
399  default:
400  panic("Invalid exception level");
401  break;
402  }
403 }
404 
405 bool
407 {
409 }
410 
411 bool
413 {
415 }
416 
417 int
418 computeAddrTop(ThreadContext *tc, bool selbit, bool isInstr,
419  TCR tcr, ExceptionLevel el)
420 {
421  bool tbi = false;
422  bool tbid = false;
423  ExceptionLevel regime = s1TranslationRegime(tc, el);
424  if (ELIs32(tc, regime)) {
425  return 31;
426  } else {
427  switch (regime) {
428  case EL1:
429  {
430  //TCR tcr = tc->readMiscReg(MISCREG_TCR_EL1);
431  tbi = selbit? tcr.tbi1 : tcr.tbi0;
432  tbid = selbit? tcr.tbid1 : tcr.tbid0;
433  break;
434  }
435  case EL2:
436  {
437  TCR tcr = tc->readMiscReg(MISCREG_TCR_EL2);
438  if (HaveVirtHostExt(tc) && ELIsInHost(tc, el)) {
439  tbi = selbit? tcr.tbi1 : tcr.tbi0;
440  tbid = selbit? tcr.tbid1 : tcr.tbid0;
441  } else {
442  tbi = tcr.tbi;
443  tbid = tcr.tbid;
444  }
445  break;
446  }
447  case EL3:
448  {
449  TCR tcr = tc->readMiscReg(MISCREG_TCR_EL3);
450  tbi = tcr.tbi;
451  tbid = tcr.tbid;
452  break;
453  }
454  default:
455  break;
456  }
457 
458  }
459  int res = (tbi && (!tbid || !isInstr))? 55: 63;
460  return res;
461 }
462 Addr
464  TCR tcr, bool isInstr)
465 {
466  bool selbit = bits(addr, 55);
467  int topbit = computeAddrTop(tc, selbit, isInstr, tcr, el);
468 
469  if (topbit == 63) {
470  return addr;
471  } else if (selbit && (el == EL1 || el == EL0 || ELIsInHost(tc, el))) {
472  uint64_t mask = ((uint64_t)0x1 << topbit) -1;
473  addr = addr | ~mask;
474  } else {
475  addr = bits(addr, topbit, 0);
476  }
477  return addr; // Nothing to do if this is not a tagged address
478 }
479 
480 Addr
482  bool isInstr)
483 {
484 
485  TCR tcr = tc->readMiscReg(MISCREG_TCR_EL1);
486  return purifyTaggedAddr(addr, tc, el, tcr, isInstr);
487 }
488 
489 Addr
491 {
492  return addr & ~(PageBytes - 1);
493 }
494 
495 Addr
497 {
498  return (addr + PageBytes - 1) & ~(PageBytes - 1);
499 }
500 
501 Fault
502 mcrMrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst,
503  ThreadContext *tc, uint32_t imm)
504 {
506  if (mcrMrc15TrapToHyp(miscReg, tc, imm, &ec))
507  return std::make_shared<HypervisorTrap>(machInst, imm, ec);
508  return AArch64AArch32SystemAccessTrap(miscReg, machInst, tc, imm, ec);
509 }
510 
511 bool
512 mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss,
514 {
515  bool isRead;
516  uint32_t crm;
517  IntRegIndex rt;
518  uint32_t crn;
519  uint32_t opc1;
520  uint32_t opc2;
521  bool trapToHype = false;
522 
523  const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
524  const HCR hcr = tc->readMiscReg(MISCREG_HCR);
525  const SCR scr = tc->readMiscReg(MISCREG_SCR);
526  const HDCR hdcr = tc->readMiscReg(MISCREG_HDCR);
527  const HSTR hstr = tc->readMiscReg(MISCREG_HSTR);
528  const HCPTR hcptr = tc->readMiscReg(MISCREG_HCPTR);
529 
530  if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
531  mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
532  trapToHype = ((uint32_t) hstr) & (1 << crn);
533  trapToHype |= hdcr.tpm && (crn == 9) && (crm >= 12);
534  trapToHype |= hcr.tidcp && (
535  ((crn == 9) && ((crm <= 2) || ((crm >= 5) && (crm <= 8)))) ||
536  ((crn == 10) && ((crm <= 1) || (crm == 4) || (crm == 8))) ||
537  ((crn == 11) && ((crm <= 8) || (crm == 15))) );
538 
539  if (!trapToHype) {
540  switch (unflattenMiscReg(miscReg)) {
541  case MISCREG_CPACR:
542  trapToHype = hcptr.tcpac;
543  break;
544  case MISCREG_REVIDR:
545  case MISCREG_TCMTR:
546  case MISCREG_TLBTR:
547  case MISCREG_AIDR:
548  trapToHype = hcr.tid1;
549  break;
550  case MISCREG_CTR:
551  case MISCREG_CCSIDR:
552  case MISCREG_CLIDR:
553  case MISCREG_CSSELR:
554  trapToHype = hcr.tid2;
555  break;
556  case MISCREG_ID_PFR0:
557  case MISCREG_ID_PFR1:
558  case MISCREG_ID_DFR0:
559  case MISCREG_ID_AFR0:
560  case MISCREG_ID_MMFR0:
561  case MISCREG_ID_MMFR1:
562  case MISCREG_ID_MMFR2:
563  case MISCREG_ID_MMFR3:
564  case MISCREG_ID_MMFR4:
565  case MISCREG_ID_ISAR0:
566  case MISCREG_ID_ISAR1:
567  case MISCREG_ID_ISAR2:
568  case MISCREG_ID_ISAR3:
569  case MISCREG_ID_ISAR4:
570  case MISCREG_ID_ISAR5:
571  case MISCREG_ID_ISAR6:
572  trapToHype = hcr.tid3;
573  break;
574  case MISCREG_DCISW:
575  case MISCREG_DCCSW:
576  case MISCREG_DCCISW:
577  trapToHype = hcr.tsw;
578  break;
579  case MISCREG_DCIMVAC:
580  case MISCREG_DCCIMVAC:
581  case MISCREG_DCCMVAC:
582  trapToHype = hcr.tpc;
583  break;
584  case MISCREG_ICIMVAU:
585  case MISCREG_ICIALLU:
586  case MISCREG_ICIALLUIS:
587  case MISCREG_DCCMVAU:
588  trapToHype = hcr.tpu;
589  break;
590  case MISCREG_TLBIALLIS:
591  case MISCREG_TLBIMVAIS:
592  case MISCREG_TLBIASIDIS:
593  case MISCREG_TLBIMVAAIS:
594  case MISCREG_TLBIMVALIS:
595  case MISCREG_TLBIMVAALIS:
596  case MISCREG_DTLBIALL:
597  case MISCREG_ITLBIALL:
598  case MISCREG_DTLBIMVA:
599  case MISCREG_ITLBIMVA:
600  case MISCREG_DTLBIASID:
601  case MISCREG_ITLBIASID:
602  case MISCREG_TLBIMVAA:
603  case MISCREG_TLBIALL:
604  case MISCREG_TLBIMVA:
605  case MISCREG_TLBIMVAL:
606  case MISCREG_TLBIMVAAL:
607  case MISCREG_TLBIASID:
608  trapToHype = hcr.ttlb;
609  break;
610  case MISCREG_ACTLR:
611  trapToHype = hcr.tac;
612  break;
613  case MISCREG_SCTLR:
614  case MISCREG_TTBR0:
615  case MISCREG_TTBR1:
616  case MISCREG_TTBCR:
617  case MISCREG_DACR:
618  case MISCREG_DFSR:
619  case MISCREG_IFSR:
620  case MISCREG_DFAR:
621  case MISCREG_IFAR:
622  case MISCREG_ADFSR:
623  case MISCREG_AIFSR:
624  case MISCREG_PRRR:
625  case MISCREG_NMRR:
626  case MISCREG_MAIR0:
627  case MISCREG_MAIR1:
628  case MISCREG_CONTEXTIDR:
629  trapToHype = hcr.tvm & !isRead;
630  break;
631  case MISCREG_PMCR:
632  trapToHype = hdcr.tpmcr;
633  break;
634  // GICv3 regs
635  case MISCREG_ICC_SGI0R:
636  {
637  auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
638  if (isa->haveGICv3CpuIfc())
639  trapToHype = hcr.fmo;
640  }
641  break;
642  case MISCREG_ICC_SGI1R:
643  case MISCREG_ICC_ASGI1R:
644  {
645  auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
646  if (isa->haveGICv3CpuIfc())
647  trapToHype = hcr.imo;
648  }
649  break;
651  // CNTFRQ may be trapped only on reads
652  // CNTPCT and CNTVCT are read-only
653  if (MISCREG_CNTFRQ <= miscReg && miscReg <= MISCREG_CNTVCT &&
654  !isRead)
655  break;
656  trapToHype = isGenericTimerHypTrap(miscReg, tc, ec);
657  break;
658  // No default action needed
659  default:
660  break;
661  }
662  }
663  }
664  return trapToHype;
665 }
666 
667 
668 bool
669 mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
670  HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
671 {
672  bool isRead;
673  uint32_t crm;
674  IntRegIndex rt;
675  uint32_t crn;
676  uint32_t opc1;
677  uint32_t opc2;
678  bool trapToHype = false;
679 
680  if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
681  mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
682  inform("trap check M:%x N:%x 1:%x 2:%x hdcr %x, hcptr %x, hstr %x\n",
683  crm, crn, opc1, opc2, hdcr, hcptr, hstr);
684  trapToHype = hdcr.tda && (opc1 == 0);
685  trapToHype |= hcptr.tta && (opc1 == 1);
686  if (!trapToHype) {
687  switch (unflattenMiscReg(miscReg)) {
688  case MISCREG_DBGOSLSR:
689  case MISCREG_DBGOSLAR:
690  case MISCREG_DBGOSDLR:
691  case MISCREG_DBGPRCR:
692  trapToHype = hdcr.tdosa;
693  break;
694  case MISCREG_DBGDRAR:
695  case MISCREG_DBGDSAR:
696  trapToHype = hdcr.tdra;
697  break;
698  case MISCREG_JIDR:
699  trapToHype = hcr.tid0;
700  break;
701  case MISCREG_JOSCR:
702  case MISCREG_JMCR:
703  trapToHype = hstr.tjdbx;
704  break;
705  case MISCREG_TEECR:
706  case MISCREG_TEEHBR:
707  trapToHype = hstr.ttee;
708  break;
709  // No default action needed
710  default:
711  break;
712  }
713  }
714  }
715  return trapToHype;
716 }
717 
718 Fault
719 mcrrMrrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst,
720  ThreadContext *tc, uint32_t imm)
721 {
723  if (mcrrMrrc15TrapToHyp(miscReg, tc, imm, &ec))
724  return std::make_shared<HypervisorTrap>(machInst, imm, ec);
725  return AArch64AArch32SystemAccessTrap(miscReg, machInst, tc, imm, ec);
726 }
727 
728 bool
730  uint32_t iss, ExceptionClass *ec)
731 {
732  uint32_t crm;
733  IntRegIndex rt;
734  uint32_t crn;
735  uint32_t opc1;
736  uint32_t opc2;
737  bool isRead;
738  bool trapToHype = false;
739 
740  const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
741  const HCR hcr = tc->readMiscReg(MISCREG_HCR);
742  const SCR scr = tc->readMiscReg(MISCREG_SCR);
743  const HSTR hstr = tc->readMiscReg(MISCREG_HSTR);
744 
745  if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
746  // This is technically the wrong function, but we can re-use it for
747  // the moment because we only need one field, which overlaps with the
748  // mcrmrc layout
749  mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
750  trapToHype = ((uint32_t) hstr) & (1 << crm);
751 
752  if (!trapToHype) {
753  switch (unflattenMiscReg(miscReg)) {
754  case MISCREG_SCTLR:
755  case MISCREG_TTBR0:
756  case MISCREG_TTBR1:
757  case MISCREG_TTBCR:
758  case MISCREG_DACR:
759  case MISCREG_DFSR:
760  case MISCREG_IFSR:
761  case MISCREG_DFAR:
762  case MISCREG_IFAR:
763  case MISCREG_ADFSR:
764  case MISCREG_AIFSR:
765  case MISCREG_PRRR:
766  case MISCREG_NMRR:
767  case MISCREG_MAIR0:
768  case MISCREG_MAIR1:
769  case MISCREG_CONTEXTIDR:
770  trapToHype = hcr.tvm & !isRead;
771  break;
773  // CNTFRQ may be trapped only on reads
774  // CNTPCT and CNTVCT are read-only
775  if (MISCREG_CNTFRQ <= miscReg && miscReg <= MISCREG_CNTVCT &&
776  !isRead)
777  break;
778  trapToHype = isGenericTimerHypTrap(miscReg, tc, ec);
779  break;
780  // No default action needed
781  default:
782  break;
783  }
784  }
785  }
786  return trapToHype;
787 }
788 
789 Fault
791  ExtMachInst machInst, ThreadContext *tc,
792  uint32_t imm, ExceptionClass ec)
793 {
794  if (currEL(tc) <= EL1 && !ELIs32(tc, EL1) &&
796  return std::make_shared<SupervisorTrap>(machInst, imm, ec);
797  if (currEL(tc) <= EL2 && EL2Enabled(tc) && !ELIs32(tc, EL2) &&
799  return std::make_shared<HypervisorTrap>(machInst, imm, ec);
800  return NoFault;
801 }
802 
803 bool
805  ThreadContext *tc)
806 {
807  switch (miscReg) {
809  return currEL(tc) == EL0 &&
811  default:
812  break;
813  }
814  return false;
815 }
816 
817 bool
820 {
821  if (currEL(tc) <= EL2 && EL2Enabled(tc) && ELIs32(tc, EL2)) {
822  switch (miscReg) {
824  if (currEL(tc) == EL0 &&
825  isGenericTimerCommonEL0HypTrap(miscReg, tc, ec))
826  return true;
827  switch (miscReg) {
828  case MISCREG_CNTPCT:
830  return currEL(tc) <= EL1 &&
831  isGenericTimerPhysHypTrap(miscReg, tc, ec);
832  default:
833  break;
834  }
835  break;
836  default:
837  break;
838  }
839  }
840  return false;
841 }
842 
843 bool
846 {
847  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
848  bool trap_cond = condGenericTimerSystemAccessTrapEL1(miscReg, tc);
849  if (ELIs32(tc, EL1) && trap_cond && hcr.tge) {
850  // As per the architecture, this hyp trap should have uncategorized
851  // exception class
852  if (ec)
853  *ec = EC_UNKNOWN;
854  return true;
855  }
856  return false;
857 }
858 
859 bool
862 {
863  return condGenericTimerPhysHypTrap(miscReg, tc);
864 }
865 
866 bool
868 {
869  const CNTHCTL cnthctl = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
870  switch (miscReg) {
871  case MISCREG_CNTPCT:
872  return !cnthctl.el1pcten;
874  return !cnthctl.el1pcen;
875  default:
876  break;
877  }
878  return false;
879 }
880 
881 bool
883  ThreadContext *tc)
884 {
885  switch (miscReg) {
888  {
889  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
890  bool trap_cond = condGenericTimerSystemAccessTrapEL1(miscReg, tc);
891  return !(EL2Enabled(tc) && hcr.e2h && hcr.tge) && trap_cond &&
892  !(EL2Enabled(tc) && !ELIs32(tc, EL2) && hcr.tge);
893  }
894  default:
895  break;
896  }
897  return false;
898 }
899 
900 bool
902  ThreadContext *tc)
903 {
904  const CNTKCTL cntkctl = tc->readMiscReg(MISCREG_CNTKCTL_EL1);
905  switch (miscReg) {
906  case MISCREG_CNTFRQ:
907  case MISCREG_CNTFRQ_EL0:
908  return !cntkctl.el0pcten && !cntkctl.el0vcten;
909  case MISCREG_CNTPCT:
910  case MISCREG_CNTPCT_EL0:
911  return !cntkctl.el0pcten;
912  case MISCREG_CNTVCT:
913  case MISCREG_CNTVCT_EL0:
914  return !cntkctl.el0vcten;
917  return !cntkctl.el0pten;
920  return !cntkctl.el0vten;
921  default:
922  break;
923  }
924  return false;
925 }
926 
927 bool
929  ThreadContext *tc)
930 {
931  switch (miscReg) {
933  return currEL(tc) <= EL1 &&
935  default:
936  break;
937  }
938  return false;
939 }
940 
941 bool
943  ThreadContext *tc)
944 {
945  switch (miscReg) {
948  if (currEL(tc) == EL0 &&
950  return true;
951  switch (miscReg) {
952  case MISCREG_CNTPCT:
953  case MISCREG_CNTPCT_EL0:
956  return (currEL(tc) == EL0 &&
958  (currEL(tc) == EL1 &&
960  case MISCREG_CNTVCT:
961  case MISCREG_CNTVCT_EL0:
964  return isGenericTimerVirtSystemAccessTrapEL2(miscReg, tc);
965  default:
966  break;
967  }
968  break;
969  default:
970  break;
971  }
972  return false;
973 }
974 
975 bool
977  ThreadContext *tc)
978 {
979  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
980  bool trap_cond_el1 = condGenericTimerSystemAccessTrapEL1(miscReg, tc);
981  bool trap_cond_el2 = condGenericTimerCommonEL0SystemAccessTrapEL2(miscReg,
982  tc);
983  return (!ELIs32(tc, EL1) && !hcr.e2h && trap_cond_el1 && hcr.tge) ||
984  (ELIs32(tc, EL1) && trap_cond_el1 && hcr.tge) ||
985  (hcr.e2h && hcr.tge && trap_cond_el2);
986 }
987 
988 bool
990  ThreadContext *tc)
991 {
992  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
993  bool trap_cond_0 = condGenericTimerPhysEL1SystemAccessTrapEL2(miscReg, tc);
994  bool trap_cond_1 = condGenericTimerCommonEL1SystemAccessTrapEL2(miscReg,
995  tc);
996  switch (miscReg) {
997  case MISCREG_CNTPCT:
998  case MISCREG_CNTPCT_EL0:
999  return !hcr.e2h && trap_cond_1;
1002  return (!hcr.e2h && trap_cond_0) ||
1003  (hcr.e2h && !hcr.tge && trap_cond_1);
1004  default:
1005  break;
1006  }
1007 
1008  return false;
1009 }
1010 
1011 bool
1013  ThreadContext *tc)
1014 {
1015  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1016  bool trap_cond_0 = condGenericTimerPhysEL1SystemAccessTrapEL2(miscReg, tc);
1017  bool trap_cond_1 = condGenericTimerCommonEL1SystemAccessTrapEL2(miscReg,
1018  tc);
1019  switch (miscReg) {
1020  case MISCREG_CNTPCT:
1021  case MISCREG_CNTPCT_EL0:
1022  return trap_cond_1;
1025  return (!hcr.e2h && trap_cond_0) ||
1026  (hcr.e2h && trap_cond_1);
1027  default:
1028  break;
1029  }
1030  return false;
1031 }
1032 
1033 bool
1035  ThreadContext *tc)
1036 {
1037  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1038  bool trap_cond = condGenericTimerCommonEL1SystemAccessTrapEL2(miscReg, tc);
1039  return !ELIs32(tc, EL1) && !(hcr.e2h && hcr.tge) && trap_cond;
1040 }
1041 
1042 bool
1044  ThreadContext *tc)
1045 {
1046  const CNTHCTL_E2H cnthctl = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1047  switch (miscReg) {
1048  case MISCREG_CNTFRQ:
1049  case MISCREG_CNTFRQ_EL0:
1050  return !cnthctl.el0pcten && !cnthctl.el0vcten;
1051  case MISCREG_CNTPCT:
1052  case MISCREG_CNTPCT_EL0:
1053  return !cnthctl.el0pcten;
1054  case MISCREG_CNTVCT:
1055  case MISCREG_CNTVCT_EL0:
1056  return !cnthctl.el0vcten;
1059  return !cnthctl.el0pten;
1062  return !cnthctl.el0vten;
1063  default:
1064  break;
1065  }
1066  return false;
1067 }
1068 
1069 bool
1071  ThreadContext *tc)
1072 {
1073  const AA64MMFR0 mmfr0 = tc->readMiscRegNoEffect(MISCREG_ID_AA64MMFR0_EL1);
1074  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1075  const RegVal cnthctl_val = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1076  const CNTHCTL cnthctl = cnthctl_val;
1077  const CNTHCTL_E2H cnthctl_e2h = cnthctl_val;
1078  switch (miscReg) {
1079  case MISCREG_CNTPCT:
1080  case MISCREG_CNTPCT_EL0:
1081  return hcr.e2h ? !cnthctl_e2h.el1pcten : !cnthctl.el1pcten;
1082  case MISCREG_CNTVCT:
1083  case MISCREG_CNTVCT_EL0:
1084  if (!mmfr0.ecv)
1085  return false;
1086  else
1087  return hcr.e2h ? cnthctl_e2h.el1tvct : cnthctl.el1tvct;
1090  return hcr.e2h ? !cnthctl_e2h.el1pten : false;
1093  if (!mmfr0.ecv)
1094  return false;
1095  else
1096  return hcr.e2h ? cnthctl_e2h.el1tvt : cnthctl.el1tvt;
1097  default:
1098  break;
1099  }
1100  return false;
1101 }
1102 
1103 bool
1105  ThreadContext *tc)
1106 {
1107  const CNTHCTL cnthctl = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1108  return !cnthctl.el1pcen;
1109 }
1110 
1111 bool
1113  ThreadContext *tc)
1114 {
1115  switch (miscReg) {
1117  {
1118  const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
1119  return currEL(tc) == EL1 && !scr.ns && !scr.st;
1120  }
1121  default:
1122  break;
1123  }
1124  return false;
1125 }
1126 
1127 bool
1128 decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx,
1129  CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
1130 {
1132  bool ok = true;
1133 
1134  // R mostly indicates if its a int register or a misc reg, we override
1135  // below if the few corner cases
1136  isIntReg = !r;
1137  // Loosely based on ARM ARM issue C section B9.3.10
1138  if (r) {
1139  switch (sysM)
1140  {
1141  case 0xE:
1142  regIdx = MISCREG_SPSR_FIQ;
1143  mode = MODE_FIQ;
1144  break;
1145  case 0x10:
1146  regIdx = MISCREG_SPSR_IRQ;
1147  mode = MODE_IRQ;
1148  break;
1149  case 0x12:
1150  regIdx = MISCREG_SPSR_SVC;
1151  mode = MODE_SVC;
1152  break;
1153  case 0x14:
1154  regIdx = MISCREG_SPSR_ABT;
1155  mode = MODE_ABORT;
1156  break;
1157  case 0x16:
1158  regIdx = MISCREG_SPSR_UND;
1159  mode = MODE_UNDEFINED;
1160  break;
1161  case 0x1C:
1162  regIdx = MISCREG_SPSR_MON;
1163  mode = MODE_MON;
1164  break;
1165  case 0x1E:
1166  regIdx = MISCREG_SPSR_HYP;
1167  mode = MODE_HYP;
1168  break;
1169  default:
1170  ok = false;
1171  break;
1172  }
1173  } else {
1174  int sysM4To3 = bits(sysM, 4, 3);
1175 
1176  if (sysM4To3 == 0) {
1177  mode = MODE_USER;
1178  regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
1179  } else if (sysM4To3 == 1) {
1180  mode = MODE_FIQ;
1181  regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
1182  } else if (sysM4To3 == 3) {
1183  if (bits(sysM, 1) == 0) {
1184  mode = MODE_MON;
1185  regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
1186  } else {
1187  mode = MODE_HYP;
1188  if (bits(sysM, 0) == 1) {
1189  regIdx = intRegInMode(mode, 13); // R13 in HYP
1190  } else {
1191  isIntReg = false;
1192  regIdx = MISCREG_ELR_HYP;
1193  }
1194  }
1195  } else { // Other Banked registers
1196  int sysM2 = bits(sysM, 2);
1197  int sysM1 = bits(sysM, 1);
1198 
1199  mode = (OperatingMode) ( ((sysM2 || sysM1) << 0) |
1200  (1 << 1) |
1201  ((sysM2 && !sysM1) << 2) |
1202  ((sysM2 && sysM1) << 3) |
1203  (1 << 4) );
1204  regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
1205  // Don't flatten the register here. This is going to go through
1206  // setIntReg() which will do the flattening
1207  ok &= mode != cpsr.mode;
1208  }
1209  }
1210 
1211  // Check that the requested register is accessable from the current mode
1212  if (ok && checkSecurity && mode != cpsr.mode) {
1213  switch (cpsr.mode)
1214  {
1215  case MODE_USER:
1216  ok = false;
1217  break;
1218  case MODE_FIQ:
1219  ok &= mode != MODE_HYP;
1220  ok &= (mode != MODE_MON) || !scr.ns;
1221  break;
1222  case MODE_HYP:
1223  ok &= mode != MODE_MON;
1224  ok &= (mode != MODE_FIQ) || !nsacr.rfr;
1225  break;
1226  case MODE_IRQ:
1227  case MODE_SVC:
1228  case MODE_ABORT:
1229  case MODE_UNDEFINED:
1230  case MODE_SYSTEM:
1231  ok &= mode != MODE_HYP;
1232  ok &= (mode != MODE_MON) || !scr.ns;
1233  ok &= (mode != MODE_FIQ) || !nsacr.rfr;
1234  break;
1235  // can access everything, no further checks required
1236  case MODE_MON:
1237  break;
1238  default:
1239  panic("unknown Mode 0x%x\n", cpsr.mode);
1240  break;
1241  }
1242  }
1243  return (ok);
1244 }
1245 
1246 bool
1248 {
1249  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1250  // NV Extension not implemented yet
1251  bool have_nv_ext = false;
1252  bool unpriv_el1 = currEL(tc) == EL1 &&
1254  have_nv_ext && hcr.nv == 1 && hcr.nv1 == 1);
1255  bool unpriv_el2 = ArmSystem::haveEL(tc, EL2) && HaveVirtHostExt(tc) &&
1256  currEL(tc) == EL2 && hcr.e2h == 1 && hcr.tge == 1;
1257 
1258  // User Access override, or UAO not implemented yet.
1259  bool user_access_override = false;
1260  return (unpriv_el1 || unpriv_el2) && !user_access_override;
1261 }
1262 
1263 bool
1265 {
1266  ExceptionLevel regime = s1TranslationRegime(tc, currEL(tc));
1267 
1268  switch (currEL(tc)) {
1269  case EL3:
1270  return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).sa;
1271  case EL2:
1272  return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).sa;
1273  case EL1:
1274  return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa;
1275  case EL0:
1276  {
1277  SCTLR sc = (regime == EL2) ? tc->readMiscReg(MISCREG_SCTLR_EL2):
1279  return sc.sa0;
1280  }
1281  default:
1282  panic("Invalid exception level");
1283  break;
1284  }
1285 }
1286 
1287 int
1288 decodePhysAddrRange64(uint8_t pa_enc)
1289 {
1290  switch (pa_enc) {
1291  case 0x0:
1292  return 32;
1293  case 0x1:
1294  return 36;
1295  case 0x2:
1296  return 40;
1297  case 0x3:
1298  return 42;
1299  case 0x4:
1300  return 44;
1301  case 0x5:
1302  return 48;
1303  case 0x6:
1304  return 52;
1305  default:
1306  panic("Invalid phys. address range encoding");
1307  }
1308 }
1309 
1310 uint8_t
1312 {
1313  switch (pa_size) {
1314  case 32:
1315  return 0x0;
1316  case 36:
1317  return 0x1;
1318  case 40:
1319  return 0x2;
1320  case 42:
1321  return 0x3;
1322  case 44:
1323  return 0x4;
1324  case 48:
1325  return 0x5;
1326  case 52:
1327  return 0x6;
1328  default:
1329  panic("Invalid phys. address range");
1330  }
1331 }
1332 
1333 } // namespace ArmISA
1334 } // namespace gem5
gem5::ArmISA::MISCREG_DCCMVAU
@ MISCREG_DCCMVAU
Definition: misc.hh:316
gem5::ArmISA::MISCREG_DFAR
@ MISCREG_DFAR
Definition: misc.hh:283
gem5::ArmISA::AArch64AArch32SystemAccessTrap
Fault AArch64AArch32SystemAccessTrap(const MiscRegIndex miscReg, ExtMachInst machInst, ThreadContext *tc, uint32_t imm, ExceptionClass ec)
Definition: utility.cc:790
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ArmISA::MISCREG_ID_MMFR4
@ MISCREG_ID_MMFR4
Definition: misc.hh:219
gem5::ArmISA::condGenericTimerCommonEL0SystemAccessTrapEL2
bool condGenericTimerCommonEL0SystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:1043
gem5::ArmISA::MISCREG_TLBIMVALIS
@ MISCREG_TLBIMVALIS
Definition: misc.hh:325
gem5::ArmISA::intRegInMode
static int intRegInMode(OperatingMode mode, int reg)
Definition: int.hh:476
gem5::ArmISA::MISCREG_PMCR
@ MISCREG_PMCR
Definition: misc.hh:351
gem5::ArmISA::MISCREG_CNTV_TVAL
@ MISCREG_CNTV_TVAL
Definition: misc.hh:427
gem5::ArmISA::MISCREG_CSSELR
@ MISCREG_CSSELR
Definition: misc.hh:230
gem5::ArmISA::MISCREG_DCCMVAC
@ MISCREG_DCCMVAC
Definition: misc.hh:312
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ArmISA::MODE_SVC
@ MODE_SVC
Definition: types.hh:284
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:285
gem5::ArmISA::MISCREG_TLBIALL
@ MISCREG_TLBIALL
Definition: misc.hh:333
gem5::ArmISA::MISCREG_HSTR
@ MISCREG_HSTR
Definition: misc.hh:252
gem5::ArmISA::ELIs64
bool ELIs64(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:282
gem5::ArmISA::MISCREG_ID_ISAR5
@ MISCREG_ID_ISAR5
Definition: misc.hh:225
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ArmISA::MISCREG_SCTLR_EL3
@ MISCREG_SCTLR_EL3
Definition: misc.hh:591
gem5::ArmISA::MISCREG_ICIALLU
@ MISCREG_ICIALLU
Definition: misc.hh:297
gem5::ArmISA::MODE_FIQ
@ MODE_FIQ
Definition: types.hh:282
gem5::ArmISA::MISCREG_CNTPS_CTL_EL1
@ MISCREG_CNTPS_CTL_EL1
Definition: misc.hh:770
gem5::ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:205
gem5::ArmISA::MISCREG_TTBR0
@ MISCREG_TTBR0
Definition: misc.hh:254
gem5::ArmISA::MISCREG_CNTVCT
@ MISCREG_CNTVCT
Definition: misc.hh:415
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:72
gem5::ArmISA::MISCREG_CNTFRQ
@ MISCREG_CNTFRQ
Definition: misc.hh:413
gem5::ArmISA::MISCREG_CONTEXTIDR
@ MISCREG_CONTEXTIDR
Definition: misc.hh:399
gem5::ArmISA::MISCREG_CNTV_CTL_EL0
@ MISCREG_CNTV_CTL_EL0
Definition: misc.hh:759
gem5::ArmISA::MISCREG_TCR_EL2
@ MISCREG_TCR_EL2
Definition: misc.hh:604
gem5::ArmISA::MISCREG_CNTPS_TVAL_EL1
@ MISCREG_CNTPS_TVAL_EL1
Definition: misc.hh:772
gem5::ArmISA::MISCREG_SPSR_FIQ
@ MISCREG_SPSR_FIQ
Definition: misc.hh:63
gem5::ArmISA::MISCREG_CNTP_CTL_EL0
@ MISCREG_CNTP_CTL_EL0
Definition: misc.hh:756
gem5::ArmISA::MISCREG_ITLBIMVA
@ MISCREG_ITLBIMVA
Definition: misc.hh:328
gem5::ArmSystem::haveLPAE
bool haveLPAE() const
Returns true if this system implements the Large Physical Address Extension.
Definition: system.hh:166
warn_once
#define warn_once(...)
Definition: logging.hh:249
gem5::ArmISA::MISCREG_MDCR_EL2
@ MISCREG_MDCR_EL2
Definition: misc.hh:587
gem5::ArmISA::tbi
Bitfield< 20 > tbi
Definition: misc_types.hh:514
gem5::ArmISA::MISCREG_TLBIMVAAL
@ MISCREG_TLBIMVAAL
Definition: misc.hh:338
gem5::ArmISA::ISA
Definition: isa.hh:68
gem5::ArmISA::MISCREG_DCCSW
@ MISCREG_DCCSW
Definition: misc.hh:313
gem5::ArmISA::decodePhysAddrRange64
int decodePhysAddrRange64(uint8_t pa_enc)
Returns the n.
Definition: utility.cc:1288
gem5::ArmISA::MODE_UNDEFINED
@ MODE_UNDEFINED
Definition: types.hh:288
gem5::ArmISA::EC_TRAPPED_CP15_MCR_MRC
@ EC_TRAPPED_CP15_MCR_MRC
Definition: types.hh:298
gem5::ArmISA::MODE_IRQ
@ MODE_IRQ
Definition: types.hh:283
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: misc.hh:593
gem5::ArmISA::isGenericTimerVirtSystemAccessTrapEL2
bool isGenericTimerVirtSystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:1034
gem5::ArmISA::encodePhysAddrRange64
uint8_t encodePhysAddrRange64(int pa_size)
Returns the encoding corresponding to the specified n.
Definition: utility.cc:1311
gem5::ArmISA::MISCREG_ICIMVAU
@ MISCREG_ICIMVAU
Definition: misc.hh:298
gem5::replaceBits
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
gem5::ArmISA::isSecureBelowEL3
bool isSecureBelowEL3(ThreadContext *tc)
Definition: utility.cc:84
gem5::ArmISA::MISCREG_TTBCR
@ MISCREG_TTBCR
Definition: misc.hh:260
gem5::ArmISA::MISCREG_TLBIMVAL
@ MISCREG_TLBIMVAL
Definition: misc.hh:337
gem5::ArmISA::MISCREG_JOSCR
@ MISCREG_JOSCR
Definition: misc.hh:201
gem5::ArmISA::MISCREG_DCISW
@ MISCREG_DCISW
Definition: misc.hh:303
gem5::ArmISA::currEL
static ExceptionLevel currEL(const ThreadContext *tc)
Definition: utility.hh:119
GEM5_FALLTHROUGH
#define GEM5_FALLTHROUGH
Definition: compiler.hh:61
gem5::ArmISA::MISCREG_TLBIALLIS
@ MISCREG_TLBIALLIS
Definition: misc.hh:321
gem5::ArmISA::condGenericTimerPhysHypTrap
bool condGenericTimerPhysHypTrap(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:867
gem5::ArmISA::MISCREG_TLBTR
@ MISCREG_TLBTR
Definition: misc.hh:208
gem5::ArmISA::MISCREG_ITLBIASID
@ MISCREG_ITLBIASID
Definition: misc.hh:329
gem5::ArmISA::MISCREG_TCR_EL3
@ MISCREG_TCR_EL3
Definition: misc.hh:610
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:267
gem5::ArmISA::mcrMrc15TrapToHyp
bool mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec)
Definition: utility.cc:512
gem5::ArmISA::MISCREG_ID_ISAR3
@ MISCREG_ID_ISAR3
Definition: misc.hh:223
gem5::ArmISA::mcrMrc15Trap
Fault mcrMrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst, ThreadContext *tc, uint32_t imm)
Definition: utility.cc:502
gem5::ArmISA::MISCREG_ID_AA64MMFR0_EL1
@ MISCREG_ID_AA64MMFR0_EL1
Definition: misc.hh:569
gem5::ArmISA::MISCREG_ID_MMFR3
@ MISCREG_ID_MMFR3
Definition: misc.hh:218
gem5::ArmISA::opModeToEL
static ExceptionLevel opModeToEL(OperatingMode mode)
Definition: types.hh:383
gem5::ArmISA::MISCREG_SPSR_MON
@ MISCREG_SPSR_MON
Definition: misc.hh:66
gem5::ArmISA::MISCREG_DBGOSLAR
@ MISCREG_DBGOSLAR
Definition: misc.hh:187
gem5::ArmISA::ELIsInHost
bool ELIsInHost(ThreadContext *tc, ExceptionLevel el)
Returns true if the current exception level el is executing a Host OS or an application of a Host OS ...
Definition: utility.cc:297
gem5::ArmISA::mcrrMrrc15Trap
Fault mcrrMrrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst, ThreadContext *tc, uint32_t imm)
Definition: utility.cc:719
gem5::ArmISA::MISCREG_DCCISW
@ MISCREG_DCCISW
Definition: misc.hh:318
gem5::ArmISA::inAArch64
bool inAArch64(ThreadContext *tc)
Definition: utility.cc:120
gem5::ArmISA::MISCREG_ID_ISAR1
@ MISCREG_ID_ISAR1
Definition: misc.hh:221
gem5::ArmISA::mcrrMrrc15TrapToHyp
bool mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec)
Definition: utility.cc:729
gem5::ArmISA::opc2
Bitfield< 7, 5 > opc2
Definition: types.hh:106
gem5::ArmISA::badMode
bool badMode(ThreadContext *tc, OperatingMode mode)
badMode is checking if the execution mode provided as an argument is valid and implemented.
Definition: utility.cc:412
system.hh
gem5::ArmISA::MISCREG_SCTLR
@ MISCREG_SCTLR
Definition: misc.hh:235
gem5::ArmISA::MISCREG_CNTVCT_EL0
@ MISCREG_CNTVCT_EL0
Definition: misc.hh:755
gem5::ArmISA::MISCREG_CNTPCT_EL0
@ MISCREG_CNTPCT_EL0
Definition: misc.hh:754
gem5::ArmISA::MISCREG_CNTP_CTL
@ MISCREG_CNTP_CTL
Definition: misc.hh:416
gem5::ThreadContext::cpuId
virtual int cpuId() const =0
cc.hh
gem5::ArmISA::MISCREG_JIDR
@ MISCREG_JIDR
Definition: misc.hh:199
gem5::ArmISA::truncPage
Addr truncPage(Addr addr)
Definition: utility.cc:490
gem5::ArmISA::MISCREG_ID_MMFR1
@ MISCREG_ID_MMFR1
Definition: misc.hh:216
gem5::ArmISA::isGenericTimerSystemAccessTrapEL3
bool isGenericTimerSystemAccessTrapEL3(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:1112
gem5::ArmISA::condGenericTimerSystemAccessTrapEL1
bool condGenericTimerSystemAccessTrapEL1(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:901
gem5::ArmISA::ELUsingAArch32K
std::pair< bool, bool > ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
This function checks whether selected EL provided as an argument is using the AArch32 ISA.
Definition: utility.cc:307
gem5::ArmISA::MISCREG_JMCR
@ MISCREG_JMCR
Definition: misc.hh:202
gem5::ArmISA::HaveLVA
bool HaveLVA(ThreadContext *tc)
Definition: utility.cc:231
gem5::ArmISA::MISCREG_DACR
@ MISCREG_DACR
Definition: misc.hh:265
gem5::ArmISA::MISCREG_HCPTR
@ MISCREG_HCPTR
Definition: misc.hh:251
gem5::ArmISA::MISCREG_ID_ISAR0
@ MISCREG_ID_ISAR0
Definition: misc.hh:220
gem5::ArmISA::MISCREG_CNTKCTL_EL1
@ MISCREG_CNTKCTL_EL1
Definition: misc.hh:768
gem5::ArmISA::ec
ec
Definition: misc_types.hh:669
gem5::ArmISA::purifyTaggedAddr
Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el, TCR tcr, bool isInstr)
Removes the tag from tagged addresses if that mode is enabled.
Definition: utility.cc:463
gem5::ArmISA::MISCREG_DBGDSAR
@ MISCREG_DBGDSAR
Definition: misc.hh:191
gem5::ArmISA::MISCREG_ID_MMFR2
@ MISCREG_ID_MMFR2
Definition: misc.hh:217
gem5::ArmISA::MISCREG_IFSR
@ MISCREG_IFSR
Definition: misc.hh:271
gem5::ArmISA::HavePACExt
bool HavePACExt(ThreadContext *tc)
Definition: utility.cc:216
gem5::ArmISA::unknownMode32
static bool unknownMode32(OperatingMode mode)
Definition: types.hh:438
gem5::ArmISA::MISCREG_DTLBIASID
@ MISCREG_DTLBIASID
Definition: misc.hh:332
mmu.hh
gem5::ArmISA::MISCREG_CNTHCTL_EL2
@ MISCREG_CNTHCTL_EL2
Definition: misc.hh:773
gem5::ArmISA::MISCREG_CNTVOFF
@ MISCREG_CNTVOFF
Definition: misc.hh:433
gem5::ArmISA::MISCREG_DTLBIMVA
@ MISCREG_DTLBIMVA
Definition: misc.hh:331
gem5::ArmISA::getAff1
static RegVal getAff1(ArmSystem *arm_sys, ThreadContext *tc)
Definition: utility.cc:198
gem5::ArmSystem::multiProc
bool multiProc
true if this a multiprocessor system
Definition: system.hh:159
gem5::ArmISA::MISCREG_PRRR
@ MISCREG_PRRR
Definition: misc.hh:369
gem5::ArmISA::getAff2
static RegVal getAff2(ArmSystem *arm_sys, ThreadContext *tc)
Definition: utility.cc:192
gem5::ArmISA::MISCREG_DBGDRAR
@ MISCREG_DBGDRAR
Definition: misc.hh:170
gem5::ArmSystem::highestEL
ArmISA::ExceptionLevel highestEL() const
Returns the highest implemented exception level.
Definition: system.hh:209
gem5::ThreadContext::socketId
virtual uint32_t socketId() const =0
interrupts.hh
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr()=0
gem5::ArmISA::isGenericTimerPhysEL0SystemAccessTrapEL2
bool isGenericTimerPhysEL0SystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:989
gem5::ArmISA::isGenericTimerHypTrap
bool isGenericTimerHypTrap(const MiscRegIndex miscReg, ThreadContext *tc, ExceptionClass *ec)
Definition: utility.cc:818
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::ArmISA::EC_UNKNOWN
@ EC_UNKNOWN
Definition: types.hh:296
gem5::ArmISA::MODE_HYP
@ MODE_HYP
Definition: types.hh:287
gem5::ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition: misc.hh:579
gem5::ArmISA::MISCREG_ID_AA64MMFR2_EL1
@ MISCREG_ID_AA64MMFR2_EL1
Definition: misc.hh:822
gem5::ArmISA::MISCREG_ID_ISAR2
@ MISCREG_ID_ISAR2
Definition: misc.hh:222
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::ArmISA::MISCREG_HDCR
@ MISCREG_HDCR
Definition: misc.hh:250
gem5::ArmISA::HaveVirtHostExt
bool HaveVirtHostExt(ThreadContext *tc)
Definition: utility.cc:224
gem5::ArmISA::MISCREG_ID_ISAR4
@ MISCREG_ID_ISAR4
Definition: misc.hh:224
gem5::ArmISA::roundPage
Addr roundPage(Addr addr)
Definition: utility.cc:496
gem5::ArmISA::rt
Bitfield< 15, 12 > rt
Definition: types.hh:115
gem5::ArmISA::MISCREG_MAIR1
@ MISCREG_MAIR1
Definition: misc.hh:378
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:268
gem5::ArmISA::MISCREG_CNTPCT
@ MISCREG_CNTPCT
Definition: misc.hh:414
gem5::ArmISA::MISCREG_SPSR_IRQ
@ MISCREG_SPSR_IRQ
Definition: misc.hh:64
gem5::ArmISA::MISCREG_SCTLR_EL2
@ MISCREG_SCTLR_EL2
Definition: misc.hh:584
gem5::ArmISA::unknownMode
static bool unknownMode(OperatingMode mode)
Definition: types.hh:412
gem5::ArmISA::EC_TRAPPED_CP15_MCRR_MRRC
@ EC_TRAPPED_CP15_MCRR_MRRC
Definition: types.hh:299
gem5::ArmISA::ELIs32
bool ELIs32(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:288
gem5::ArmISA::computeAddrTop
int computeAddrTop(ThreadContext *tc, bool selbit, bool isInstr, TCR tcr, ExceptionLevel el)
Definition: utility.cc:418
gem5::ArmISA::MISCREG_CCSIDR
@ MISCREG_CCSIDR
Definition: misc.hh:227
cpu.hh
gem5::ArmISA::MISCREG_ICIALLUIS
@ MISCREG_ICIALLUIS
Definition: misc.hh:292
port_proxy.hh
gem5::ArmISA::condGenericTimerCommonEL1SystemAccessTrapEL2
bool condGenericTimerCommonEL1SystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:1070
gem5::ArmISA::MISCREG_DCCIMVAC
@ MISCREG_DCCIMVAC
Definition: misc.hh:317
gem5::ArmISA::isGenericTimerPhysEL1SystemAccessTrapEL2
bool isGenericTimerPhysEL1SystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:1012
gem5::ArmISA::getAffinity
RegVal getAffinity(ArmSystem *arm_sys, ThreadContext *tc)
Retrieves MPIDR_EL1.
Definition: utility.cc:210
gem5::ArmISA::tbid
Bitfield< 29 > tbid
Definition: misc_types.hh:537
gem5::ArmISA::EL2Enabled
bool EL2Enabled(ThreadContext *tc)
Definition: utility.cc:274
gem5::ArmISA::MISCREG_TEEHBR
@ MISCREG_TEEHBR
Definition: misc.hh:200
gem5::ArmISA::MISCREG_ACTLR
@ MISCREG_ACTLR
Definition: misc.hh:238
gem5::ArmISA::MISCREG_IFAR
@ MISCREG_IFAR
Definition: misc.hh:286
gem5::ArmISA::MISCREG_ICC_ASGI1R
@ MISCREG_ICC_ASGI1R
Definition: misc.hh:975
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition: pcstate.hh:63
gem5::ArmISA::isAArch64AArch32SystemAccessTrapEL1
bool isAArch64AArch32SystemAccessTrapEL1(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:804
gem5::ArmISA::MISCREG_ID_AFR0
@ MISCREG_ID_AFR0
Definition: misc.hh:214
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
compiler.hh
gem5::ArmISA::SPAlignmentCheckEnabled
bool SPAlignmentCheckEnabled(ThreadContext *tc)
Definition: utility.cc:1264
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:269
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::ArmISA::MODE_USER
@ MODE_USER
Definition: types.hh:281
gem5::ArmISA::MISCREG_DBGPRCR
@ MISCREG_DBGPRCR
Definition: misc.hh:190
std::pair
STL pair class.
Definition: stl.hh:58
gem5::ArmISA::MISCREG_ID_PFR1
@ MISCREG_ID_PFR1
Definition: misc.hh:212
gem5::ArmISA::s1TranslationRegime
ExceptionLevel s1TranslationRegime(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:238
faults.hh
gem5::ArmISA::isGenericTimerSystemAccessTrapEL1
bool isGenericTimerSystemAccessTrapEL1(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:882
gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
Definition: misc.hh:570
gem5::ArmISA::debugTargetFrom
ExceptionLevel debugTargetFrom(ThreadContext *tc, bool secure)
Definition: utility.cc:91
gem5::BaseCPU::postInterrupt
void postInterrupt(ThreadID tid, int int_num, int index)
Definition: base.cc:194
gem5::ArmISA::MISCREG_ICC_SGI1R
@ MISCREG_ICC_SGI1R
Definition: misc.hh:1001
gem5::ArmISA::MISCREG_TCMTR
@ MISCREG_TCMTR
Definition: misc.hh:207
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::MISCREG_TLBIMVA
@ MISCREG_TLBIMVA
Definition: misc.hh:334
gem5::ArmISA::MISCREG_DBGOSDLR
@ MISCREG_DBGOSDLR
Definition: misc.hh:189
gem5::ArmISA::MISCREG_DFSR
@ MISCREG_DFSR
Definition: misc.hh:268
gem5::ArmISA::MISCREG_NMRR
@ MISCREG_NMRR
Definition: misc.hh:375
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmISA::MISCREG_CNTP_TVAL_EL0
@ MISCREG_CNTP_TVAL_EL0
Definition: misc.hh:758
gem5::ArmISA::MISCREG_TTBR1
@ MISCREG_TTBR1
Definition: misc.hh:257
gem5::ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:72
gem5::ArmISA::ELStateUsingAArch32K
std::pair< bool, bool > ELStateUsingAArch32K(ThreadContext *tc, ExceptionLevel el, bool secure)
Definition: utility.cc:328
gem5::ArmISA::MISCREG_ID_AA64ISAR1_EL1
@ MISCREG_ID_AA64ISAR1_EL1
Definition: misc.hh:568
utility.hh
gem5::ArmISA::ExceptionClass
ExceptionClass
Definition: types.hh:293
full_system.hh
gem5::ArmISA::MISCREG_MAIR0
@ MISCREG_MAIR0
Definition: misc.hh:372
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::ArmISA::MISCREG_TLBIASIDIS
@ MISCREG_TLBIASIDIS
Definition: misc.hh:323
gem5::System::multiThread
const bool multiThread
Definition: system.hh:318
gem5::ArmISA::MISCREG_AIDR
@ MISCREG_AIDR
Definition: misc.hh:229
gem5::ArmISA::MISCREG_ICC_SGI0R
@ MISCREG_ICC_SGI0R
Definition: misc.hh:1000
gem5::ArmISA::IsSecureEL2Enabled
bool IsSecureEL2Enabled(ThreadContext *tc)
Definition: utility.cc:260
gem5::ArmISA::MISCREG_AIFSR
@ MISCREG_AIFSR
Definition: misc.hh:277
gem5::ArmISA::MISCREG_DCIMVAC
@ MISCREG_DCIMVAC
Definition: misc.hh:302
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:266
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::ArmISA::MISCREG_CTR
@ MISCREG_CTR
Definition: misc.hh:206
gem5::ArmSystem
Definition: system.hh:62
gem5::ArmISA::imm
Bitfield< 7, 0 > imm
Definition: types.hh:132
gem5::ArmISA::MISCREG_TEECR
@ MISCREG_TEECR
Definition: misc.hh:198
gem5::ArmISA::MISCREG_DTLBIALL
@ MISCREG_DTLBIALL
Definition: misc.hh:330
gem5::ArmISA::MISCREG_HCR
@ MISCREG_HCR
Definition: misc.hh:248
gem5::ArmISA::MISCREG_ADFSR
@ MISCREG_ADFSR
Definition: misc.hh:274
inform
#define inform(...)
Definition: logging.hh:246
gem5::ArmISA::decodeMrsMsrBankedReg
bool decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx, CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
Definition: utility.cc:1128
gem5::ArmISA::MISCREG_SPSR_SVC
@ MISCREG_SPSR_SVC
Definition: misc.hh:65
gem5::ArmISA::isUnpriviledgeAccess
bool isUnpriviledgeAccess(ThreadContext *tc)
Definition: utility.cc:1247
base.hh
gem5::ArmISA::MISCREG_CLIDR
@ MISCREG_CLIDR
Definition: misc.hh:228
gem5::ArmISA::getAff0
static RegVal getAff0(ArmSystem *arm_sys, ThreadContext *tc)
Definition: utility.cc:204
gem5::ArmISA::MISCREG_TLBIMVAALIS
@ MISCREG_TLBIMVAALIS
Definition: misc.hh:326
gem5::ArmISA::isGenericTimerCommonEL0SystemAccessTrapEL2
bool isGenericTimerCommonEL0SystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:976
gem5::ArmISA::sendEvent
void sendEvent(ThreadContext *tc)
Send an event (SEV) to a specific PE if there isn't already a pending event.
Definition: utility.cc:63
gem5::ArmISA::ELStateUsingAArch32
bool ELStateUsingAArch32(ThreadContext *tc, ExceptionLevel el, bool secure)
Definition: utility.cc:378
gem5::ArmSystem::haveSecurity
bool haveSecurity() const
Returns true if this system implements the Security Extensions.
Definition: system.hh:162
gem5::ArmISA::MISCREG_DBGOSLSR
@ MISCREG_DBGOSLSR
Definition: misc.hh:188
gem5::ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition: misc.hh:243
gem5::ArmISA::longDescFormatInUse
bool longDescFormatInUse(ThreadContext *tc)
Definition: utility.cc:127
gem5::ArmISA::MISCREG_ID_PFR0
@ MISCREG_ID_PFR0
Definition: misc.hh:211
gem5::ArmISA::MODE_SYSTEM
@ MODE_SYSTEM
Definition: types.hh:289
gem5::ArmISA::PageBytes
const Addr PageBytes
Definition: page_size.hh:53
gem5::ArmISA::inSecureState
static bool inSecureState(SCR scr, CPSR cpsr)
Definition: utility.hh:223
gem5::ArmISA::MISCREG_VMPIDR_EL2
@ MISCREG_VMPIDR_EL2
Definition: misc.hh:578
gem5::ArmISA::mcrMrc14TrapToHyp
bool mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
Definition: utility.cc:669
gem5::ArmISA::HaveSecureEL2Ext
bool HaveSecureEL2Ext(ThreadContext *tc)
Definition: utility.cc:253
gem5::ArmISA::MISCREG_REVIDR
@ MISCREG_REVIDR
Definition: misc.hh:210
gem5::ArmISA::badMode32
bool badMode32(ThreadContext *tc, OperatingMode mode)
badMode is checking if the execution mode provided as an argument is valid and implemented for AArch3...
Definition: utility.cc:406
gem5::ArmISA::MISCREG_SPSR_ABT
@ MISCREG_SPSR_ABT
Definition: misc.hh:67
gem5::ArmISA::MISCREG_ELR_HYP
@ MISCREG_ELR_HYP
Definition: misc.hh:70
gem5::ArmISA::isGenericTimerPhysHypTrap
bool isGenericTimerPhysHypTrap(const MiscRegIndex miscReg, ThreadContext *tc, ExceptionClass *ec)
Definition: utility.cc:860
gem5::MipsISA::r
r
Definition: pra_constants.hh:98
gem5::ArmISA::isAArch64AArch32SystemAccessTrapEL2
bool isAArch64AArch32SystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:928
gem5::ArmISA::haveAArch32EL
bool haveAArch32EL(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:314
gem5::ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
gem5::ArmISA::MISCREG_SEV_MAILBOX
@ MISCREG_SEV_MAILBOX
Definition: misc.hh:92
gem5::ThreadContext::threadId
virtual int threadId() const =0
gem5::ArmISA::MISCREG_ID_ISAR6
@ MISCREG_ID_ISAR6
Definition: misc.hh:226
gem5::ArmISA::MISCREG_CNTP_TVAL_S
@ MISCREG_CNTP_TVAL_S
Definition: misc.hh:424
page_size.hh
gem5::ArmISA::MISCREG_CNTFRQ_EL0
@ MISCREG_CNTFRQ_EL0
Definition: misc.hh:753
gem5::ArmISA::MISCREG_TLBIMVAIS
@ MISCREG_TLBIMVAIS
Definition: misc.hh:322
gem5::ArmISA::isGenericTimerCommonEL0HypTrap
bool isGenericTimerCommonEL0HypTrap(const MiscRegIndex miscReg, ThreadContext *tc, ExceptionClass *ec)
Definition: utility.cc:844
gem5::ArmSystem::haveEL
static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el)
Return true if the system implements a specific exception level.
Definition: system.cc:138
gem5::ArmISA::MODE_ABORT
@ MODE_ABORT
Definition: types.hh:286
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: misc.hh:586
gem5::ArmISA::MISCREG_TLBIASID
@ MISCREG_TLBIASID
Definition: misc.hh:335
gem5::ArmISA::MISCREG_TLBIMVAA
@ MISCREG_TLBIMVAA
Definition: misc.hh:336
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::MISCREG_ID_AA64PFR0_EL1
@ MISCREG_ID_AA64PFR0_EL1
Definition: misc.hh:561
gem5::ArmISA::MISCREG_TLBIMVAAIS
@ MISCREG_TLBIMVAAIS
Definition: misc.hh:324
gem5::ArmISA::MISCREG_CNTV_CTL
@ MISCREG_CNTV_CTL
Definition: misc.hh:425
gem5::ArmISA::condGenericTimerPhysEL1SystemAccessTrapEL2
bool condGenericTimerPhysEL1SystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:1104
gem5::ArmISA::isBigEndian64
bool isBigEndian64(const ThreadContext *tc)
Definition: utility.cc:388
gem5::ArmISA::MISCREG_ID_MMFR0
@ MISCREG_ID_MMFR0
Definition: misc.hh:215
int.hh
gem5::ArmISA::MISCREG_CPACR
@ MISCREG_CPACR
Definition: misc.hh:241
gem5::ArmISA::MISCREG_SPSR_HYP
@ MISCREG_SPSR_HYP
Definition: misc.hh:68
gem5::ArmISA::isGenericTimerSystemAccessTrapEL2
bool isGenericTimerSystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:942
thread_context.hh
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:272
gem5::ArmISA::readMPIDR
RegVal readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
This helper function is either returing the value of MPIDR_EL1 (by calling getMPIDR),...
Definition: utility.cc:134
gem5::ArmISA::MISCREG_ID_DFR0
@ MISCREG_ID_DFR0
Definition: misc.hh:213
gem5::ArmSystem::haveVirtualization
bool haveVirtualization() const
Returns true if this system implements the virtualization Extensions.
Definition: system.hh:171
gem5::ArmISA::MISCREG_ITLBIALL
@ MISCREG_ITLBIALL
Definition: misc.hh:327
gem5::ArmISA::unflattenMiscReg
int unflattenMiscReg(int reg)
Definition: misc.cc:1365
gem5::ArmISA::getMPIDR
RegVal getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
This helper function is returning the value of MPIDR_EL1.
Definition: utility.cc:162
gem5::ArmISA::MISCREG_TCR_EL1
@ MISCREG_TCR_EL1
Definition: misc.hh:601
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::ArmISA::INT_SEV
@ INT_SEV
Definition: interrupts.hh:64
gem5::ArmISA::MISCREG_CNTV_TVAL_EL0
@ MISCREG_CNTV_TVAL_EL0
Definition: misc.hh:761
gem5::ArmISA::MISCREG_SPSR_UND
@ MISCREG_SPSR_UND
Definition: misc.hh:69
gem5::ArmISA::mcrMrcIssExtract
static void mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt, uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
Definition: utility.hh:267

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