gem5  v21.2.1.1
utility.cc
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1 /*
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37 
38 #include "arch/arm/utility.hh"
39 
40 #include <memory>
41 
42 #include "arch/arm/faults.hh"
43 #include "arch/arm/interrupts.hh"
44 #include "arch/arm/mmu.hh"
45 #include "arch/arm/page_size.hh"
46 #include "arch/arm/regs/cc.hh"
47 #include "arch/arm/regs/int.hh"
48 #include "arch/arm/regs/vec.hh"
49 #include "arch/arm/system.hh"
50 #include "base/compiler.hh"
51 #include "cpu/base.hh"
52 #include "cpu/checker/cpu.hh"
53 #include "cpu/thread_context.hh"
54 #include "mem/port_proxy.hh"
55 #include "sim/full_system.hh"
56 
57 namespace gem5
58 {
59 
60 namespace ArmISA
61 {
62 
63 void
65 {
66  if (tc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
67  // Post Interrupt and wake cpu if needed
68  tc->getCpuPtr()->postInterrupt(tc->threadId(), INT_SEV, 0);
69  }
70 }
71 
72 bool
74 {
75  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
76  if (ArmSystem::haveEL(tc, EL3) && !cpsr.width && currEL(tc) == EL3)
77  return true;
78  if (ArmSystem::haveEL(tc, EL3) && cpsr.width && cpsr.mode == MODE_MON)
79  return true;
80  else
81  return isSecureBelowEL3(tc);
82 }
83 
84 bool
86 {
87  SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
88  return ArmSystem::haveEL(tc, EL3) && scr.ns == 0;
89 }
90 
92 debugTargetFrom(ThreadContext *tc, bool secure)
93 {
94  bool route_to_el2;
95  if (ArmSystem::haveEL(tc, EL2) && (!secure || HaveSecureEL2Ext(tc))) {
96  if (ELIs32(tc, EL2)) {
97  const HCR hcr = tc->readMiscReg(MISCREG_HCR);
98  const HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
99  route_to_el2 = (hdcr.tde == 1 || hcr.tge == 1);
100  } else {
101  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
102  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
103  route_to_el2 = (mdcr.tde == 1 || hcr.tge == 1);
104  }
105  }else{
106  route_to_el2 = false;
107  }
108  ExceptionLevel target;
109  if (route_to_el2) {
110  target = EL2;
111  } else if (ArmSystem::haveEL(tc, EL3) && !ArmSystem::highestELIs64(tc)
112  && secure) {
113  target = EL3;
114  } else {
115  target = EL1;
116  }
117  return target;
118 }
119 
120 bool
122 {
123  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
124  return opModeIs64((OperatingMode) (uint8_t) cpsr.mode);
125 }
126 
129 {
130  return static_cast<ArmISA::ISA *>(
131  const_cast<ThreadContext *>(tc)->getIsaPtr())->currEL();
132 }
133 
134 bool
136 {
137  TTBCR ttbcr = tc->readMiscReg(MISCREG_TTBCR);
138  return ArmSystem::has(ArmExtension::LPAE, tc) && ttbcr.eae;
139 }
140 
141 RegVal
143 {
144  const ExceptionLevel current_el = currEL(tc);
145 
146  const bool is_secure = isSecureBelowEL3(tc);
147 
148  switch (current_el) {
149  case EL0:
150  // Note: in MsrMrs instruction we read the register value before
151  // checking access permissions. This means that EL0 entry must
152  // be part of the table even if MPIDR is not accessible in user
153  // mode.
154  warn_once("Trying to read MPIDR at EL0\n");
155  [[fallthrough]];
156  case EL1:
157  if (ArmSystem::haveEL(tc, EL2) && !is_secure)
158  return tc->readMiscReg(MISCREG_VMPIDR_EL2);
159  else
160  return getMPIDR(arm_sys, tc);
161  case EL2:
162  case EL3:
163  return getMPIDR(arm_sys, tc);
164  default:
165  panic("Invalid EL for reading MPIDR register\n");
166  }
167 }
168 
169 RegVal
171 {
172  // Multiprocessor Affinity Register MPIDR from Cortex(tm)-A15 Technical
173  // Reference Manual
174  //
175  // bit 31 - Multi-processor extensions available
176  // bit 30 - Uni-processor system
177  // bit 24 - Multi-threaded cores
178  // bit 11-8 - Cluster ID
179  // bit 1-0 - CPU ID
180  //
181  // We deliberately extend both the Cluster ID and CPU ID fields to allow
182  // for simulation of larger systems
183  assert((0 <= tc->cpuId()) && (tc->cpuId() < 256));
184  assert(tc->socketId() < 65536);
185 
186  RegVal mpidr = 0x80000000;
187 
188  if (!arm_sys->multiProc)
189  replaceBits(mpidr, 30, 1);
190 
191  if (arm_sys->multiThread)
192  replaceBits(mpidr, 24, 1);
193 
194  // Get Affinity numbers
195  mpidr |= getAffinity(arm_sys, tc);
196  return mpidr;
197 }
198 
199 static RegVal
201 {
202  return arm_sys->multiThread ? tc->socketId() << 16 : 0;
203 }
204 
205 static RegVal
207 {
208  return arm_sys->multiThread ? tc->cpuId() << 8 : tc->socketId() << 8;
209 }
210 
211 static RegVal
213 {
214  return arm_sys->multiThread ? tc->threadId() : tc->cpuId();
215 }
216 
217 RegVal
219 {
220  return getAff2(arm_sys, tc) | getAff1(arm_sys, tc) | getAff0(arm_sys, tc);
221 }
222 
223 bool
225 {
226  AA64ISAR1 id_aa64isar1 = tc->readMiscReg(MISCREG_ID_AA64ISAR1_EL1);
227  return id_aa64isar1.api | id_aa64isar1.apa |
228  id_aa64isar1.gpi | id_aa64isar1.gpa;
229 }
230 
231 bool
233 {
234  AA64MMFR1 id_aa64mmfr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1);
235  return id_aa64mmfr1.vh;
236 }
237 
238 bool
240 {
241  const AA64MMFR2 mm_fr2 = tc->readMiscReg(MISCREG_ID_AA64MMFR2_EL1);
242  return (bool)mm_fr2.varange;
243 }
244 
247 {
248 
249  SCR scr = tc->readMiscReg(MISCREG_SCR);
250  if (el != EL0)
251  return el;
252  else if (ArmSystem::haveEL(tc, EL3) && ELIs32(tc, EL3) && scr.ns == 0)
253  return EL3;
254  else if (HaveVirtHostExt(tc) && ELIsInHost(tc, el))
255  return EL2;
256  else
257  return EL1;
258 }
259 
260 bool
262 {
263  AA64PFR0 id_aa64pfr0 = tc->readMiscReg(MISCREG_ID_AA64PFR0_EL1);
264  return id_aa64pfr0.sel2;
265 }
266 
267 bool
269 {
270  SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
271  if (ArmSystem::haveEL(tc, EL2) && HaveSecureEL2Ext(tc) &&
272  !ELIs32(tc, EL2)) {
273  if (ArmSystem::haveEL(tc, EL3))
274  return !ELIs32(tc, EL3) && scr.eel2;
275  else
276  return isSecure(tc);
277  }
278  return false;
279 }
280 
281 bool
283 {
284  SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
285  return ArmSystem::haveEL(tc, EL2) &&
286  (!ArmSystem::haveEL(tc, EL3) || scr.ns || IsSecureEL2Enabled(tc));
287 }
288 
289 bool
291 {
292  return !ELIs32(tc, el);
293 }
294 
295 bool
297 {
298  auto [known, aarch32] = ELUsingAArch32K(tc, el);
299  panic_if(!known, "EL state is UNKNOWN");
300  return aarch32;
301 }
302 
303 bool
305 {
306  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
307  return (ArmSystem::haveEL(tc, EL2) &&
308  (IsSecureEL2Enabled(tc) || !isSecureBelowEL3(tc)) &&
309  HaveVirtHostExt(tc) && !ELIs32(tc, EL2) && hcr.e2h == 1 &&
310  (el == EL2 || (el == EL0 && hcr.tge == 1)));
311 }
312 
315 {
316  bool secure = isSecureBelowEL3(tc);
317  return ELStateUsingAArch32K(tc, el, secure);
318 }
319 
320 bool
322 {
323  if (!ArmSystem::haveEL(tc, el))
324  return false;
325  else if (!ArmSystem::highestELIs64(tc))
326  return true;
327  else if (ArmSystem::highestEL(tc) == el)
328  return false;
329  else if (el == EL0)
330  return true;
331  return true;
332 }
333 
336 {
337  // Return true if the specified EL is in aarch32 state.
338  const bool have_el3 = ArmSystem::haveEL(tc, EL3);
339  const bool have_el2 = ArmSystem::haveEL(tc, EL2);
340 
341  panic_if(el == EL2 && !have_el2, "Asking for EL2 when it doesn't exist");
342  panic_if(el == EL3 && !have_el3, "Asking for EL3 when it doesn't exist");
343 
344  bool known, aarch32;
345  known = aarch32 = false;
346  if (!haveAArch32EL(tc, el)) {
347  // Target EL is the highest one in a system where
348  // the highest is using AArch64.
349  known = true; aarch32 = false;
350  } else if (secure && el == EL2) {
351  known = true; aarch32 = false;
352  } else if (!ArmSystem::highestELIs64(tc)) {
353  // All ELs are using AArch32:
354  known = true; aarch32 = true;
355  } else if (ArmSystem::highestEL(tc) == el) {
356  known = true; aarch32 = false;
357  } else {
358  SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
359  bool aarch32_below_el3 = have_el3 && scr.rw == 0 &&
360  (!secure || !HaveSecureEL2Ext(tc) || !scr.eel2);
361 
362  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
363  bool sec_el2 = HaveSecureEL2Ext(tc) && scr.eel2;
364  bool aarch32_at_el1 = (aarch32_below_el3 ||
365  (have_el2 && (sec_el2 || !secure) &&
366  hcr.rw == 0 && !(hcr.e2h && hcr.tge &&
367  HaveVirtHostExt(tc))));
368 
369  // Only know if EL0 using AArch32 from PSTATE
370  if (el == EL0 && !aarch32_at_el1) {
371  // EL0 controlled by PSTATE
372  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
373  known = (currEL(tc) == EL0);
374  aarch32 = (cpsr.width == 1);
375  } else {
376  known = true;
377  aarch32 = (aarch32_below_el3 && el != EL3) ||
378  (aarch32_at_el1 && (el == EL0 || el == EL1) );
379  }
380  }
381 
382  return std::make_pair(known, aarch32);
383 }
384 
385 bool
387 {
388  auto [known, aarch32] = ELStateUsingAArch32K(tc, el, secure);
389  panic_if(!known, "EL state is UNKNOWN");
390  return aarch32;
391 }
392 
393 bool
395 {
396  switch (currEL(tc)) {
397  case EL3:
398  return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL3)).ee;
399  case EL2:
400  return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL2)).ee;
401  case EL1:
402  return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL1)).ee;
403  case EL0:
404  return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL1)).e0e;
405  default:
406  panic("Invalid exception level");
407  break;
408  }
409 }
410 
411 bool
413 {
415 }
416 
417 bool
419 {
421 }
422 
423 int
424 computeAddrTop(ThreadContext *tc, bool selbit, bool is_instr,
425  TCR tcr, ExceptionLevel el)
426 {
427  bool tbi = false;
428  bool tbid = false;
429  ExceptionLevel regime = s1TranslationRegime(tc, el);
430  if (ELIs32(tc, regime)) {
431  return 31;
432  } else {
433  switch (regime) {
434  case EL1:
435  {
436  //TCR tcr = tc->readMiscReg(MISCREG_TCR_EL1);
437  tbi = selbit? tcr.tbi1 : tcr.tbi0;
438  tbid = selbit? tcr.tbid1 : tcr.tbid0;
439  break;
440  }
441  case EL2:
442  {
443  TCR tcr = tc->readMiscReg(MISCREG_TCR_EL2);
444  if (HaveVirtHostExt(tc) && ELIsInHost(tc, el)) {
445  tbi = selbit? tcr.tbi1 : tcr.tbi0;
446  tbid = selbit? tcr.tbid1 : tcr.tbid0;
447  } else {
448  tbi = tcr.tbi;
449  tbid = tcr.tbid;
450  }
451  break;
452  }
453  case EL3:
454  {
455  TCR tcr = tc->readMiscReg(MISCREG_TCR_EL3);
456  tbi = tcr.tbi;
457  tbid = tcr.tbid;
458  break;
459  }
460  default:
461  break;
462  }
463 
464  }
465  int res = (tbi && (!tbid || !is_instr))? 55: 63;
466  return res;
467 }
468 Addr
470  TCR tcr, bool is_instr)
471 {
472  bool selbit = bits(addr, 55);
473  int topbit = computeAddrTop(tc, selbit, is_instr, tcr, el);
474 
475  if (topbit == 63) {
476  return addr;
477  } else if (selbit && (el == EL1 || el == EL0 || ELIsInHost(tc, el))) {
478  uint64_t mask = ((uint64_t)0x1 << topbit) -1;
479  addr = addr | ~mask;
480  } else {
481  addr = bits(addr, topbit, 0);
482  }
483  return addr; // Nothing to do if this is not a tagged address
484 }
485 
486 Addr
488  bool is_instr)
489 {
490 
491  TCR tcr = tc->readMiscReg(MISCREG_TCR_EL1);
492  return purifyTaggedAddr(addr, tc, el, tcr, is_instr);
493 }
494 
495 Addr
497 {
498  return addr & ~(PageBytes - 1);
499 }
500 
501 Addr
503 {
504  return (addr + PageBytes - 1) & ~(PageBytes - 1);
505 }
506 
507 Fault
508 mcrMrc15Trap(const MiscRegIndex misc_reg, ExtMachInst mach_inst,
509  ThreadContext *tc, uint32_t imm)
510 {
512  if (mcrMrc15TrapToHyp(misc_reg, tc, imm, &ec))
513  return std::make_shared<HypervisorTrap>(mach_inst, imm, ec);
514  return AArch64AArch32SystemAccessTrap(misc_reg, mach_inst, tc, imm, ec);
515 }
516 
517 bool
518 mcrMrc15TrapToHyp(const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss,
520 {
521  bool is_read;
522  uint32_t crm;
523  IntRegIndex rt;
524  uint32_t crn;
525  uint32_t opc1;
526  uint32_t opc2;
527  bool trap_to_hyp = false;
528 
529  const HCR hcr = tc->readMiscReg(MISCREG_HCR);
530  const HDCR hdcr = tc->readMiscReg(MISCREG_HDCR);
531  const HSTR hstr = tc->readMiscReg(MISCREG_HSTR);
532  const HCPTR hcptr = tc->readMiscReg(MISCREG_HCPTR);
533 
534  if (EL2Enabled(tc) && (currEL(tc) < EL2)) {
535  mcrMrcIssExtract(iss, is_read, crm, rt, crn, opc1, opc2);
536  trap_to_hyp = ((uint32_t) hstr) & (1 << crn);
537  trap_to_hyp |= hdcr.tpm && (crn == 9) && (crm >= 12);
538  trap_to_hyp |= hcr.tidcp && (
539  ((crn == 9) && ((crm <= 2) || ((crm >= 5) && (crm <= 8)))) ||
540  ((crn == 10) && ((crm <= 1) || (crm == 4) || (crm == 8))) ||
541  ((crn == 11) && ((crm <= 8) || (crm == 15))));
542 
543  if (!trap_to_hyp) {
544  switch (unflattenMiscReg(misc_reg)) {
545  case MISCREG_CPACR:
546  trap_to_hyp = hcptr.tcpac;
547  break;
548  case MISCREG_REVIDR:
549  case MISCREG_TCMTR:
550  case MISCREG_TLBTR:
551  case MISCREG_AIDR:
552  trap_to_hyp = hcr.tid1;
553  break;
554  case MISCREG_CTR:
555  case MISCREG_CCSIDR:
556  case MISCREG_CLIDR:
557  case MISCREG_CSSELR:
558  trap_to_hyp = hcr.tid2;
559  break;
560  case MISCREG_ID_PFR0:
561  case MISCREG_ID_PFR1:
562  case MISCREG_ID_DFR0:
563  case MISCREG_ID_AFR0:
564  case MISCREG_ID_MMFR0:
565  case MISCREG_ID_MMFR1:
566  case MISCREG_ID_MMFR2:
567  case MISCREG_ID_MMFR3:
568  case MISCREG_ID_MMFR4:
569  case MISCREG_ID_ISAR0:
570  case MISCREG_ID_ISAR1:
571  case MISCREG_ID_ISAR2:
572  case MISCREG_ID_ISAR3:
573  case MISCREG_ID_ISAR4:
574  case MISCREG_ID_ISAR5:
575  case MISCREG_ID_ISAR6:
576  trap_to_hyp = hcr.tid3;
577  break;
578  case MISCREG_DCISW:
579  case MISCREG_DCCSW:
580  case MISCREG_DCCISW:
581  trap_to_hyp = hcr.tsw;
582  break;
583  case MISCREG_DCIMVAC:
584  case MISCREG_DCCIMVAC:
585  case MISCREG_DCCMVAC:
586  trap_to_hyp = hcr.tpc;
587  break;
588  case MISCREG_ICIMVAU:
589  case MISCREG_ICIALLU:
590  case MISCREG_ICIALLUIS:
591  case MISCREG_DCCMVAU:
592  trap_to_hyp = hcr.tpu;
593  break;
594  case MISCREG_TLBIALLIS:
595  case MISCREG_TLBIMVAIS:
596  case MISCREG_TLBIASIDIS:
597  case MISCREG_TLBIMVAAIS:
598  case MISCREG_TLBIMVALIS:
599  case MISCREG_TLBIMVAALIS:
600  case MISCREG_DTLBIALL:
601  case MISCREG_ITLBIALL:
602  case MISCREG_DTLBIMVA:
603  case MISCREG_ITLBIMVA:
604  case MISCREG_DTLBIASID:
605  case MISCREG_ITLBIASID:
606  case MISCREG_TLBIMVAA:
607  case MISCREG_TLBIALL:
608  case MISCREG_TLBIMVA:
609  case MISCREG_TLBIMVAL:
610  case MISCREG_TLBIMVAAL:
611  case MISCREG_TLBIASID:
612  trap_to_hyp = hcr.ttlb;
613  break;
614  case MISCREG_ACTLR:
615  trap_to_hyp = hcr.tac;
616  break;
617  case MISCREG_SCTLR:
618  case MISCREG_TTBR0:
619  case MISCREG_TTBR1:
620  case MISCREG_TTBCR:
621  case MISCREG_DACR:
622  case MISCREG_DFSR:
623  case MISCREG_IFSR:
624  case MISCREG_DFAR:
625  case MISCREG_IFAR:
626  case MISCREG_ADFSR:
627  case MISCREG_AIFSR:
628  case MISCREG_PRRR:
629  case MISCREG_NMRR:
630  case MISCREG_MAIR0:
631  case MISCREG_MAIR1:
632  case MISCREG_CONTEXTIDR:
633  trap_to_hyp = hcr.tvm & !is_read;
634  break;
635  case MISCREG_PMCR:
636  trap_to_hyp = hdcr.tpmcr;
637  break;
638  // GICv3 regs
639  case MISCREG_ICC_SGI0R:
640  {
641  auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
642  if (isa->haveGICv3CpuIfc())
643  trap_to_hyp = hcr.fmo;
644  }
645  break;
646  case MISCREG_ICC_SGI1R:
647  case MISCREG_ICC_ASGI1R:
648  {
649  auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
650  if (isa->haveGICv3CpuIfc())
651  trap_to_hyp = hcr.imo;
652  }
653  break;
655  // CNTFRQ may be trapped only on reads
656  // CNTPCT and CNTVCT are read-only
657  if (MISCREG_CNTFRQ <= misc_reg && misc_reg <= MISCREG_CNTVCT &&
658  !is_read)
659  break;
660  trap_to_hyp = isGenericTimerHypTrap(misc_reg, tc, ec);
661  break;
662  // No default action needed
663  default:
664  break;
665  }
666  }
667  }
668  return trap_to_hyp;
669 }
670 
671 
672 bool
673 mcrMrc14TrapToHyp(const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss)
674 {
675  bool is_read;
676  uint32_t crm;
677  IntRegIndex rt;
678  uint32_t crn;
679  uint32_t opc1;
680  uint32_t opc2;
681 
682  const HCR hcr = tc->readMiscReg(MISCREG_HCR);
683  const HDCR hdcr = tc->readMiscReg(MISCREG_HDCR);
684  const HSTR hstr = tc->readMiscReg(MISCREG_HSTR);
685  const HCPTR hcptr = tc->readMiscReg(MISCREG_HCPTR);
686 
687  bool trap_to_hyp = false;
688 
689  if (EL2Enabled(tc) && (currEL(tc) < EL2)) {
690  mcrMrcIssExtract(iss, is_read, crm, rt, crn, opc1, opc2);
691  inform("trap check M:%x N:%x 1:%x 2:%x hdcr %x, hcptr %x, hstr %x\n",
692  crm, crn, opc1, opc2, hdcr, hcptr, hstr);
693  trap_to_hyp = hdcr.tda && (opc1 == 0);
694  trap_to_hyp |= hcptr.tta && (opc1 == 1);
695  if (!trap_to_hyp) {
696  switch (unflattenMiscReg(misc_reg)) {
697  case MISCREG_DBGOSLSR:
698  case MISCREG_DBGOSLAR:
699  case MISCREG_DBGOSDLR:
700  case MISCREG_DBGPRCR:
701  trap_to_hyp = hdcr.tdosa;
702  break;
703  case MISCREG_DBGDRAR:
704  case MISCREG_DBGDSAR:
705  trap_to_hyp = hdcr.tdra;
706  break;
707  case MISCREG_JIDR:
708  trap_to_hyp = hcr.tid0;
709  break;
710  case MISCREG_JOSCR:
711  case MISCREG_JMCR:
712  trap_to_hyp = hstr.tjdbx;
713  break;
714  case MISCREG_TEECR:
715  case MISCREG_TEEHBR:
716  trap_to_hyp = hstr.ttee;
717  break;
718  // No default action needed
719  default:
720  break;
721  }
722  }
723  }
724  return trap_to_hyp;
725 }
726 
727 Fault
728 mcrrMrrc15Trap(const MiscRegIndex misc_reg, ExtMachInst mach_inst,
729  ThreadContext *tc, uint32_t imm)
730 {
732  if (mcrrMrrc15TrapToHyp(misc_reg, tc, imm, &ec))
733  return std::make_shared<HypervisorTrap>(mach_inst, imm, ec);
734  return AArch64AArch32SystemAccessTrap(misc_reg, mach_inst, tc, imm, ec);
735 }
736 
737 bool
739  uint32_t iss, ExceptionClass *ec)
740 {
741  uint32_t crm;
742  IntRegIndex rt;
743  uint32_t crn;
744  uint32_t opc1;
745  uint32_t opc2;
746  bool is_read;
747  bool trap_to_hyp = false;
748 
749  const HCR hcr = tc->readMiscReg(MISCREG_HCR);
750  const HSTR hstr = tc->readMiscReg(MISCREG_HSTR);
751 
752  if (EL2Enabled(tc) && (currEL(tc) < EL2)) {
753  // This is technically the wrong function, but we can re-use it for
754  // the moment because we only need one field, which overlaps with the
755  // mcrmrc layout
756  mcrMrcIssExtract(iss, is_read, crm, rt, crn, opc1, opc2);
757  trap_to_hyp = ((uint32_t)hstr) & (1 << crm);
758 
759  if (!trap_to_hyp) {
760  switch (unflattenMiscReg(misc_reg)) {
761  case MISCREG_SCTLR:
762  case MISCREG_TTBR0:
763  case MISCREG_TTBR1:
764  case MISCREG_TTBCR:
765  case MISCREG_DACR:
766  case MISCREG_DFSR:
767  case MISCREG_IFSR:
768  case MISCREG_DFAR:
769  case MISCREG_IFAR:
770  case MISCREG_ADFSR:
771  case MISCREG_AIFSR:
772  case MISCREG_PRRR:
773  case MISCREG_NMRR:
774  case MISCREG_MAIR0:
775  case MISCREG_MAIR1:
776  case MISCREG_CONTEXTIDR:
777  trap_to_hyp = hcr.tvm & !is_read;
778  break;
780  // CNTFRQ may be trapped only on reads
781  // CNTPCT and CNTVCT are read-only
782  if (MISCREG_CNTFRQ <= misc_reg && misc_reg <= MISCREG_CNTVCT &&
783  !is_read) {
784  break;
785  }
786  trap_to_hyp = isGenericTimerHypTrap(misc_reg, tc, ec);
787  break;
788  // No default action needed
789  default:
790  break;
791  }
792  }
793  }
794  return trap_to_hyp;
795 }
796 
797 Fault
799  ExtMachInst mach_inst, ThreadContext *tc,
800  uint32_t imm, ExceptionClass ec)
801 {
802  if (currEL(tc) <= EL1 && !ELIs32(tc, EL1) &&
804  return std::make_shared<SupervisorTrap>(mach_inst, imm, ec);
805  if (currEL(tc) <= EL2 && EL2Enabled(tc) && !ELIs32(tc, EL2) &&
807  return std::make_shared<HypervisorTrap>(mach_inst, imm, ec);
808  return NoFault;
809 }
810 
811 bool
813  ThreadContext *tc)
814 {
815  switch (misc_reg) {
817  return currEL(tc) == EL0 &&
818  isGenericTimerSystemAccessTrapEL1(misc_reg, tc);
819  default:
820  break;
821  }
822  return false;
823 }
824 
825 bool
828 {
829  if (currEL(tc) <= EL2 && EL2Enabled(tc) && ELIs32(tc, EL2)) {
830  switch (misc_reg) {
832  if (currEL(tc) == EL0 &&
833  isGenericTimerCommonEL0HypTrap(misc_reg, tc, ec))
834  return true;
835  switch (misc_reg) {
836  case MISCREG_CNTPCT:
838  return currEL(tc) <= EL1 &&
839  isGenericTimerPhysHypTrap(misc_reg, tc, ec);
840  default:
841  break;
842  }
843  break;
844  default:
845  break;
846  }
847  }
848  return false;
849 }
850 
851 bool
854 {
855  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
856  bool trap_cond = condGenericTimerSystemAccessTrapEL1(misc_reg, tc);
857  if (ELIs32(tc, EL1) && trap_cond && hcr.tge) {
858  // As per the architecture, this hyp trap should have uncategorized
859  // exception class
860  if (ec)
861  *ec = EC_UNKNOWN;
862  return true;
863  }
864  return false;
865 }
866 
867 bool
870 {
871  return condGenericTimerPhysHypTrap(misc_reg, tc);
872 }
873 
874 bool
876 {
877  const CNTHCTL cnthctl = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
878  switch (misc_reg) {
879  case MISCREG_CNTPCT:
880  return !cnthctl.el1pcten;
882  return !cnthctl.el1pcen;
883  default:
884  break;
885  }
886  return false;
887 }
888 
889 bool
891  ThreadContext *tc)
892 {
893  switch (misc_reg) {
896  {
897  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
898  bool trap_cond = condGenericTimerSystemAccessTrapEL1(misc_reg, tc);
899  return !(EL2Enabled(tc) && hcr.e2h && hcr.tge) && trap_cond &&
900  !(EL2Enabled(tc) && !ELIs32(tc, EL2) && hcr.tge);
901  }
902  default:
903  break;
904  }
905  return false;
906 }
907 
908 bool
910  ThreadContext *tc)
911 {
912  const CNTKCTL cntkctl = tc->readMiscReg(MISCREG_CNTKCTL_EL1);
913  switch (misc_reg) {
914  case MISCREG_CNTFRQ:
915  case MISCREG_CNTFRQ_EL0:
916  return !cntkctl.el0pcten && !cntkctl.el0vcten;
917  case MISCREG_CNTPCT:
918  case MISCREG_CNTPCT_EL0:
919  return !cntkctl.el0pcten;
920  case MISCREG_CNTVCT:
921  case MISCREG_CNTVCT_EL0:
922  return !cntkctl.el0vcten;
925  return !cntkctl.el0pten;
928  return !cntkctl.el0vten;
929  default:
930  break;
931  }
932  return false;
933 }
934 
935 bool
937  ThreadContext *tc)
938 {
939  switch (misc_reg) {
941  return currEL(tc) <= EL1 &&
942  isGenericTimerSystemAccessTrapEL2(misc_reg, tc);
943  default:
944  break;
945  }
946  return false;
947 }
948 
949 bool
951  ThreadContext *tc)
952 {
953  switch (misc_reg) {
956  if (currEL(tc) == EL0 &&
958  return true;
959  switch (misc_reg) {
960  case MISCREG_CNTPCT:
961  case MISCREG_CNTPCT_EL0:
964  return (currEL(tc) == EL0 &&
966  (currEL(tc) == EL1 &&
968  case MISCREG_CNTVCT:
969  case MISCREG_CNTVCT_EL0:
972  return isGenericTimerVirtSystemAccessTrapEL2(misc_reg, tc);
973  default:
974  break;
975  }
976  break;
977  default:
978  break;
979  }
980  return false;
981 }
982 
983 bool
985  ThreadContext *tc)
986 {
987  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
988  bool trap_cond_el1 = condGenericTimerSystemAccessTrapEL1(misc_reg, tc);
989  bool trap_cond_el2 = condGenericTimerCommonEL0SystemAccessTrapEL2(misc_reg,
990  tc);
991  return (!ELIs32(tc, EL1) && !hcr.e2h && trap_cond_el1 && hcr.tge) ||
992  (ELIs32(tc, EL1) && trap_cond_el1 && hcr.tge) ||
993  (hcr.e2h && hcr.tge && trap_cond_el2);
994 }
995 
996 bool
998  ThreadContext *tc)
999 {
1000  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1001  bool trap_cond_0 = condGenericTimerPhysEL1SystemAccessTrapEL2(
1002  misc_reg, tc);
1004  misc_reg, tc);
1005 
1006  switch (misc_reg) {
1007  case MISCREG_CNTPCT:
1008  case MISCREG_CNTPCT_EL0:
1009  return !hcr.e2h && trap_cond_1;
1012  return (!hcr.e2h && trap_cond_0) ||
1013  (hcr.e2h && !hcr.tge && trap_cond_1);
1014  default:
1015  break;
1016  }
1017 
1018  return false;
1019 }
1020 
1021 bool
1023  ThreadContext *tc)
1024 {
1025  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1026  bool trap_cond_0 = condGenericTimerPhysEL1SystemAccessTrapEL2(
1027  misc_reg, tc);
1029  misc_reg, tc);
1030 
1031  switch (misc_reg) {
1032  case MISCREG_CNTPCT:
1033  case MISCREG_CNTPCT_EL0:
1034  return trap_cond_1;
1037  return (!hcr.e2h && trap_cond_0) ||
1038  (hcr.e2h && trap_cond_1);
1039  default:
1040  break;
1041  }
1042  return false;
1043 }
1044 
1045 bool
1047  ThreadContext *tc)
1048 {
1049  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1051  misc_reg, tc);
1052  return !ELIs32(tc, EL1) && !(hcr.e2h && hcr.tge) && trap_cond;
1053 }
1054 
1055 bool
1057  ThreadContext *tc)
1058 {
1059  const CNTHCTL_E2H cnthctl = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1060  switch (misc_reg) {
1061  case MISCREG_CNTFRQ:
1062  case MISCREG_CNTFRQ_EL0:
1063  return !cnthctl.el0pcten && !cnthctl.el0vcten;
1064  case MISCREG_CNTPCT:
1065  case MISCREG_CNTPCT_EL0:
1066  return !cnthctl.el0pcten;
1067  case MISCREG_CNTVCT:
1068  case MISCREG_CNTVCT_EL0:
1069  return !cnthctl.el0vcten;
1072  return !cnthctl.el0pten;
1075  return !cnthctl.el0vten;
1076  default:
1077  break;
1078  }
1079  return false;
1080 }
1081 
1082 bool
1084  ThreadContext *tc)
1085 {
1086  const AA64MMFR0 mmfr0 = tc->readMiscRegNoEffect(MISCREG_ID_AA64MMFR0_EL1);
1087  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1088  const RegVal cnthctl_val = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1089  const CNTHCTL cnthctl = cnthctl_val;
1090  const CNTHCTL_E2H cnthctl_e2h = cnthctl_val;
1091  switch (misc_reg) {
1092  case MISCREG_CNTPCT:
1093  case MISCREG_CNTPCT_EL0:
1094  return hcr.e2h ? !cnthctl_e2h.el1pcten : !cnthctl.el1pcten;
1095  case MISCREG_CNTVCT:
1096  case MISCREG_CNTVCT_EL0:
1097  if (!mmfr0.ecv)
1098  return false;
1099  else
1100  return hcr.e2h ? cnthctl_e2h.el1tvct : cnthctl.el1tvct;
1103  return hcr.e2h ? !cnthctl_e2h.el1pten : false;
1106  if (!mmfr0.ecv)
1107  return false;
1108  else
1109  return hcr.e2h ? cnthctl_e2h.el1tvt : cnthctl.el1tvt;
1110  default:
1111  break;
1112  }
1113  return false;
1114 }
1115 
1116 bool
1118  ThreadContext *tc)
1119 {
1120  const CNTHCTL cnthctl = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1121  return !cnthctl.el1pcen;
1122 }
1123 
1124 bool
1126  ThreadContext *tc)
1127 {
1128  switch (misc_reg) {
1130  {
1131  const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
1132  return currEL(tc) == EL1 && !scr.ns && !scr.st;
1133  }
1134  default:
1135  break;
1136  }
1137  return false;
1138 }
1139 
1140 bool
1141 decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx,
1142  CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
1143 {
1145  bool ok = true;
1146 
1147  // R mostly indicates if its a int register or a misc reg, we override
1148  // below if the few corner cases
1149  isIntReg = !r;
1150  // Loosely based on ARM ARM issue C section B9.3.10
1151  if (r) {
1152  switch (sysM) {
1153  case 0xE:
1154  regIdx = MISCREG_SPSR_FIQ;
1155  mode = MODE_FIQ;
1156  break;
1157  case 0x10:
1158  regIdx = MISCREG_SPSR_IRQ;
1159  mode = MODE_IRQ;
1160  break;
1161  case 0x12:
1162  regIdx = MISCREG_SPSR_SVC;
1163  mode = MODE_SVC;
1164  break;
1165  case 0x14:
1166  regIdx = MISCREG_SPSR_ABT;
1167  mode = MODE_ABORT;
1168  break;
1169  case 0x16:
1170  regIdx = MISCREG_SPSR_UND;
1171  mode = MODE_UNDEFINED;
1172  break;
1173  case 0x1C:
1174  regIdx = MISCREG_SPSR_MON;
1175  mode = MODE_MON;
1176  break;
1177  case 0x1E:
1178  regIdx = MISCREG_SPSR_HYP;
1179  mode = MODE_HYP;
1180  break;
1181  default:
1182  ok = false;
1183  break;
1184  }
1185  } else {
1186  int sysM4To3 = bits(sysM, 4, 3);
1187 
1188  if (sysM4To3 == 0) {
1189  mode = MODE_USER;
1190  regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
1191  } else if (sysM4To3 == 1) {
1192  mode = MODE_FIQ;
1193  regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
1194  } else if (sysM4To3 == 3) {
1195  if (bits(sysM, 1) == 0) {
1196  mode = MODE_MON;
1197  regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
1198  } else {
1199  mode = MODE_HYP;
1200  if (bits(sysM, 0) == 1) {
1201  regIdx = intRegInMode(mode, 13); // R13 in HYP
1202  } else {
1203  isIntReg = false;
1204  regIdx = MISCREG_ELR_HYP;
1205  }
1206  }
1207  } else { // Other Banked registers
1208  int sysM2 = bits(sysM, 2);
1209  int sysM1 = bits(sysM, 1);
1210 
1211  mode = (OperatingMode)(((sysM2 || sysM1) << 0) |
1212  (1 << 1) |
1213  ((sysM2 && !sysM1) << 2) |
1214  ((sysM2 && sysM1) << 3) |
1215  (1 << 4));
1216  regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
1217  // Don't flatten the register here. This is going to go through
1218  // setIntReg() which will do the flattening
1219  ok &= mode != cpsr.mode;
1220  }
1221  }
1222 
1223  // Check that the requested register is accessable from the current mode
1224  if (ok && checkSecurity && mode != cpsr.mode) {
1225  switch (cpsr.mode) {
1226  case MODE_USER:
1227  ok = false;
1228  break;
1229  case MODE_FIQ:
1230  ok &= mode != MODE_HYP;
1231  ok &= (mode != MODE_MON) || !scr.ns;
1232  break;
1233  case MODE_HYP:
1234  ok &= mode != MODE_MON;
1235  ok &= (mode != MODE_FIQ) || !nsacr.rfr;
1236  break;
1237  case MODE_IRQ:
1238  case MODE_SVC:
1239  case MODE_ABORT:
1240  case MODE_UNDEFINED:
1241  case MODE_SYSTEM:
1242  ok &= mode != MODE_HYP;
1243  ok &= (mode != MODE_MON) || !scr.ns;
1244  ok &= (mode != MODE_FIQ) || !nsacr.rfr;
1245  break;
1246  // can access everything, no further checks required
1247  case MODE_MON:
1248  break;
1249  default:
1250  panic("unknown Mode 0x%x\n", cpsr.mode);
1251  break;
1252  }
1253  }
1254  return ok;
1255 }
1256 
1257 bool
1259 {
1260  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1261  const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1262 
1263  // NV Extension not implemented yet
1264  bool have_nv_ext = false;
1265  bool unpriv_el1 = currEL(tc) == EL1 &&
1266  !(ArmSystem::haveEL(tc, EL2) &&
1267  have_nv_ext && hcr.nv == 1 && hcr.nv1 == 1);
1268  bool unpriv_el2 = ArmSystem::haveEL(tc, EL2) && HaveVirtHostExt(tc) &&
1269  currEL(tc) == EL2 && hcr.e2h == 1 && hcr.tge == 1;
1270 
1271  return (unpriv_el1 || unpriv_el2) && !cpsr.uao;
1272 }
1273 
1274 bool
1276 {
1277  ExceptionLevel regime = s1TranslationRegime(tc, currEL(tc));
1278 
1279  switch (currEL(tc)) {
1280  case EL3:
1281  return ((SCTLR)tc->readMiscReg(MISCREG_SCTLR_EL3)).sa;
1282  case EL2:
1283  return ((SCTLR)tc->readMiscReg(MISCREG_SCTLR_EL2)).sa;
1284  case EL1:
1285  return ((SCTLR)tc->readMiscReg(MISCREG_SCTLR_EL1)).sa;
1286  case EL0:
1287  {
1288  SCTLR sc = (regime == EL2) ? tc->readMiscReg(MISCREG_SCTLR_EL2):
1290  return sc.sa0;
1291  }
1292  default:
1293  panic("Invalid exception level");
1294  break;
1295  }
1296 }
1297 
1298 int
1299 decodePhysAddrRange64(uint8_t pa_enc)
1300 {
1301  switch (pa_enc) {
1302  case 0x0:
1303  return 32;
1304  case 0x1:
1305  return 36;
1306  case 0x2:
1307  return 40;
1308  case 0x3:
1309  return 42;
1310  case 0x4:
1311  return 44;
1312  case 0x5:
1313  return 48;
1314  case 0x6:
1315  return 52;
1316  default:
1317  panic("Invalid phys. address range encoding");
1318  }
1319 }
1320 
1321 uint8_t
1323 {
1324  switch (pa_size) {
1325  case 32:
1326  return 0x0;
1327  case 36:
1328  return 0x1;
1329  case 40:
1330  return 0x2;
1331  case 42:
1332  return 0x3;
1333  case 44:
1334  return 0x4;
1335  case 48:
1336  return 0x5;
1337  case 52:
1338  return 0x6;
1339  default:
1340  panic("Invalid phys. address range");
1341  }
1342 }
1343 
1344 void
1346 {
1347  for (int ri = 0; ri < NumVecRegs; ri++) {
1348  RegId reg_id(VecRegClass, ri);
1349  const VecRegContainer &reg = tc->readVecReg(reg_id);
1350  for (int ei = 0; ei < NumVecElemPerVecReg; ei++) {
1351  RegId elem_id(VecElemClass, ri, ei);
1352  tc->setVecElem(elem_id, reg.as<VecElem>()[ei]);
1353  }
1354  }
1355 }
1356 
1357 void
1359 {
1360  for (int ri = 0; ri < NumVecRegs; ri++) {
1362  for (int ei = 0; ei < NumVecElemPerVecReg; ei++) {
1363  RegId elem_id(VecElemClass, ri, ei);
1364  reg.as<VecElem>()[ei] = tc->readVecElem(elem_id);
1365  }
1366  RegId reg_id(VecRegClass, ri);
1367  tc->setVecReg(reg_id, reg);
1368  }
1369 }
1370 
1371 } // namespace ArmISA
1372 } // namespace gem5
gem5::ArmISA::MISCREG_DCCMVAU
@ MISCREG_DCCMVAU
Definition: misc.hh:316
gem5::ArmISA::MISCREG_DFAR
@ MISCREG_DFAR
Definition: misc.hh:283
gem5::ArmISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition: vec.hh:58
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ArmISA::MISCREG_ID_MMFR4
@ MISCREG_ID_MMFR4
Definition: misc.hh:219
gem5::ArmISA::MISCREG_TLBIMVALIS
@ MISCREG_TLBIMVALIS
Definition: misc.hh:325
gem5::ArmISA::intRegInMode
static int intRegInMode(OperatingMode mode, int reg)
Definition: int.hh:475
gem5::ArmISA::MISCREG_PMCR
@ MISCREG_PMCR
Definition: misc.hh:351
gem5::ArmISA::MISCREG_CNTV_TVAL
@ MISCREG_CNTV_TVAL
Definition: misc.hh:427
gem5::ArmISA::MISCREG_CSSELR
@ MISCREG_CSSELR
Definition: misc.hh:230
gem5::ArmISA::MISCREG_DCCMVAC
@ MISCREG_DCCMVAC
Definition: misc.hh:312
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ArmISA::MODE_SVC
@ MODE_SVC
Definition: types.hh:284
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:285
gem5::ArmISA::MISCREG_TLBIALL
@ MISCREG_TLBIALL
Definition: misc.hh:333
gem5::ArmISA::MISCREG_HSTR
@ MISCREG_HSTR
Definition: misc.hh:252
gem5::ArmISA::ELIs64
bool ELIs64(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:290
gem5::ArmISA::MISCREG_ID_ISAR5
@ MISCREG_ID_ISAR5
Definition: misc.hh:225
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ArmISA::MISCREG_SCTLR_EL3
@ MISCREG_SCTLR_EL3
Definition: misc.hh:591
gem5::ArmISA::MISCREG_ICIALLU
@ MISCREG_ICIALLU
Definition: misc.hh:297
gem5::ArmISA::MODE_FIQ
@ MODE_FIQ
Definition: types.hh:282
gem5::ArmISA::MISCREG_CNTPS_CTL_EL1
@ MISCREG_CNTPS_CTL_EL1
Definition: misc.hh:770
gem5::ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:183
gem5::ArmISA::MISCREG_TTBR0
@ MISCREG_TTBR0
Definition: misc.hh:254
gem5::ArmISA::MISCREG_CNTVCT
@ MISCREG_CNTVCT
Definition: misc.hh:415
gem5::ArmISA::NumVecRegs
const int NumVecRegs
Definition: vec.hh:80
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:73
gem5::ArmISA::MISCREG_CNTFRQ
@ MISCREG_CNTFRQ
Definition: misc.hh:413
gem5::ArmISA::MISCREG_CONTEXTIDR
@ MISCREG_CONTEXTIDR
Definition: misc.hh:399
gem5::ArmISA::MISCREG_CNTV_CTL_EL0
@ MISCREG_CNTV_CTL_EL0
Definition: misc.hh:759
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:63
gem5::ArmISA::isGenericTimerPhysEL1SystemAccessTrapEL2
bool isGenericTimerPhysEL1SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:1022
gem5::ArmISA::MISCREG_TCR_EL2
@ MISCREG_TCR_EL2
Definition: misc.hh:604
gem5::ArmISA::MISCREG_CNTPS_TVAL_EL1
@ MISCREG_CNTPS_TVAL_EL1
Definition: misc.hh:772
gem5::ArmISA::MISCREG_SPSR_FIQ
@ MISCREG_SPSR_FIQ
Definition: misc.hh:63
gem5::ArmISA::MISCREG_CNTP_CTL_EL0
@ MISCREG_CNTP_CTL_EL0
Definition: misc.hh:756
gem5::ArmISA::MISCREG_ITLBIMVA
@ MISCREG_ITLBIMVA
Definition: misc.hh:328
warn_once
#define warn_once(...)
Definition: logging.hh:250
gem5::ArmISA::MISCREG_MDCR_EL2
@ MISCREG_MDCR_EL2
Definition: misc.hh:587
gem5::ArmISA::isGenericTimerHypTrap
bool isGenericTimerHypTrap(const MiscRegIndex misc_reg, ThreadContext *tc, ExceptionClass *ec)
Definition: utility.cc:826
gem5::ArmISA::tbi
Bitfield< 20 > tbi
Definition: misc_types.hh:515
gem5::ArmISA::MISCREG_TLBIMVAAL
@ MISCREG_TLBIMVAAL
Definition: misc.hh:338
gem5::ArmISA::ISA
Definition: isa.hh:68
gem5::ArmISA::MISCREG_DCCSW
@ MISCREG_DCCSW
Definition: misc.hh:313
gem5::ArmISA::decodePhysAddrRange64
int decodePhysAddrRange64(uint8_t pa_enc)
Returns the n.
Definition: utility.cc:1299
gem5::ArmISA::MODE_UNDEFINED
@ MODE_UNDEFINED
Definition: types.hh:288
gem5::ArmISA::EC_TRAPPED_CP15_MCR_MRC
@ EC_TRAPPED_CP15_MCR_MRC
Definition: types.hh:298
gem5::ArmISA::MODE_IRQ
@ MODE_IRQ
Definition: types.hh:283
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: misc.hh:593
gem5::ArmISA::isGenericTimerSystemAccessTrapEL1
bool isGenericTimerSystemAccessTrapEL1(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:890
gem5::ArmISA::isGenericTimerCommonEL0HypTrap
bool isGenericTimerCommonEL0HypTrap(const MiscRegIndex misc_reg, ThreadContext *tc, ExceptionClass *ec)
Definition: utility.cc:852
gem5::ArmISA::encodePhysAddrRange64
uint8_t encodePhysAddrRange64(int pa_size)
Returns the encoding corresponding to the specified n.
Definition: utility.cc:1322
gem5::ArmISA::MISCREG_ICIMVAU
@ MISCREG_ICIMVAU
Definition: misc.hh:298
gem5::replaceBits
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
gem5::ArmISA::isSecureBelowEL3
bool isSecureBelowEL3(ThreadContext *tc)
Definition: utility.cc:85
gem5::ArmISA::isGenericTimerSystemAccessTrapEL2
bool isGenericTimerSystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:950
gem5::ArmISA::MISCREG_TTBCR
@ MISCREG_TTBCR
Definition: misc.hh:260
gem5::ArmISA::MISCREG_TLBIMVAL
@ MISCREG_TLBIMVAL
Definition: misc.hh:337
gem5::ArmISA::MISCREG_JOSCR
@ MISCREG_JOSCR
Definition: misc.hh:201
gem5::ArmISA::MISCREG_DCISW
@ MISCREG_DCISW
Definition: misc.hh:303
gem5::ArmISA::MISCREG_TLBIALLIS
@ MISCREG_TLBIALLIS
Definition: misc.hh:321
gem5::ArmISA::MISCREG_TLBTR
@ MISCREG_TLBTR
Definition: misc.hh:208
gem5::ArmISA::mcrrMrrc15TrapToHyp
bool mcrrMrrc15TrapToHyp(const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec)
Definition: utility.cc:738
gem5::ArmISA::MISCREG_ITLBIASID
@ MISCREG_ITLBIASID
Definition: misc.hh:329
gem5::ArmISA::MISCREG_TCR_EL3
@ MISCREG_TCR_EL3
Definition: misc.hh:610
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:267
gem5::ArmISA::MISCREG_ID_ISAR3
@ MISCREG_ID_ISAR3
Definition: misc.hh:223
gem5::ArmISA::MISCREG_ID_AA64MMFR0_EL1
@ MISCREG_ID_AA64MMFR0_EL1
Definition: misc.hh:569
gem5::ArmISA::MISCREG_ID_MMFR3
@ MISCREG_ID_MMFR3
Definition: misc.hh:218
vec.hh
gem5::ArmISA::opModeToEL
static ExceptionLevel opModeToEL(OperatingMode mode)
Definition: types.hh:383
gem5::ArmISA::MISCREG_SPSR_MON
@ MISCREG_SPSR_MON
Definition: misc.hh:66
gem5::ArmISA::MISCREG_DBGOSLAR
@ MISCREG_DBGOSLAR
Definition: misc.hh:187
gem5::ArmISA::ELIsInHost
bool ELIsInHost(ThreadContext *tc, ExceptionLevel el)
Returns true if the current exception level el is executing a Host OS or an application of a Host OS ...
Definition: utility.cc:304
gem5::ArmISA::isAArch64AArch32SystemAccessTrapEL2
bool isAArch64AArch32SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:936
gem5::ArmISA::MISCREG_DCCISW
@ MISCREG_DCCISW
Definition: misc.hh:318
gem5::ArmISA::inAArch64
bool inAArch64(ThreadContext *tc)
Definition: utility.cc:121
gem5::ArmISA::MISCREG_ID_ISAR1
@ MISCREG_ID_ISAR1
Definition: misc.hh:221
gem5::ArmISA::opc2
Bitfield< 7, 5 > opc2
Definition: types.hh:106
gem5::ArmISA::badMode
bool badMode(ThreadContext *tc, OperatingMode mode)
badMode is checking if the execution mode provided as an argument is valid and implemented.
Definition: utility.cc:418
system.hh
gem5::ArmISA::MISCREG_SCTLR
@ MISCREG_SCTLR
Definition: misc.hh:235
gem5::ArmISA::MISCREG_CNTVCT_EL0
@ MISCREG_CNTVCT_EL0
Definition: misc.hh:755
gem5::ArmISA::MISCREG_CNTPCT_EL0
@ MISCREG_CNTPCT_EL0
Definition: misc.hh:754
gem5::ArmISA::MISCREG_CNTP_CTL
@ MISCREG_CNTP_CTL
Definition: misc.hh:416
gem5::ThreadContext::cpuId
virtual int cpuId() const =0
cc.hh
gem5::ArmISA::MISCREG_JIDR
@ MISCREG_JIDR
Definition: misc.hh:199
gem5::ArmISA::AArch64AArch32SystemAccessTrap
Fault AArch64AArch32SystemAccessTrap(const MiscRegIndex misc_reg, ExtMachInst mach_inst, ThreadContext *tc, uint32_t imm, ExceptionClass ec)
Definition: utility.cc:798
gem5::ArmISA::truncPage
Addr truncPage(Addr addr)
Definition: utility.cc:496
gem5::ArmISA::MISCREG_ID_MMFR1
@ MISCREG_ID_MMFR1
Definition: misc.hh:216
gem5::ArmISA::ELUsingAArch32K
std::pair< bool, bool > ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
This function checks whether selected EL provided as an argument is using the AArch32 ISA.
Definition: utility.cc:314
gem5::ArmISA::condGenericTimerCommonEL0SystemAccessTrapEL2
bool condGenericTimerCommonEL0SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:1056
gem5::ArmISA::condGenericTimerSystemAccessTrapEL1
bool condGenericTimerSystemAccessTrapEL1(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:909
gem5::ArmISA::mcrMrc14TrapToHyp
bool mcrMrc14TrapToHyp(const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss)
Definition: utility.cc:673
gem5::ArmISA::MISCREG_JMCR
@ MISCREG_JMCR
Definition: misc.hh:202
gem5::ArmISA::HaveLVA
bool HaveLVA(ThreadContext *tc)
Definition: utility.cc:239
gem5::ArmISA::MISCREG_DACR
@ MISCREG_DACR
Definition: misc.hh:265
gem5::ArmISA::MISCREG_HCPTR
@ MISCREG_HCPTR
Definition: misc.hh:251
gem5::ArmISA::MISCREG_ID_ISAR0
@ MISCREG_ID_ISAR0
Definition: misc.hh:220
gem5::ArmISA::MISCREG_CNTKCTL_EL1
@ MISCREG_CNTKCTL_EL1
Definition: misc.hh:768
gem5::ArmISA::ec
ec
Definition: misc_types.hh:670
gem5::ArmISA::mcrMrc15Trap
Fault mcrMrc15Trap(const MiscRegIndex misc_reg, ExtMachInst mach_inst, ThreadContext *tc, uint32_t imm)
Definition: utility.cc:508
gem5::ArmISA::purifyTaggedAddr
Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el, TCR tcr, bool is_instr)
Removes the tag from tagged addresses if that mode is enabled.
Definition: utility.cc:469
gem5::ArmISA::MISCREG_DBGDSAR
@ MISCREG_DBGDSAR
Definition: misc.hh:191
gem5::ArmISA::MISCREG_ID_MMFR2
@ MISCREG_ID_MMFR2
Definition: misc.hh:217
gem5::ArmISA::MISCREG_IFSR
@ MISCREG_IFSR
Definition: misc.hh:271
gem5::ArmISA::HavePACExt
bool HavePACExt(ThreadContext *tc)
Definition: utility.cc:224
gem5::ArmISA::unknownMode32
static bool unknownMode32(OperatingMode mode)
Definition: types.hh:438
gem5::ArmISA::MISCREG_DTLBIASID
@ MISCREG_DTLBIASID
Definition: misc.hh:332
mmu.hh
gem5::ArmISA::isGenericTimerCommonEL0SystemAccessTrapEL2
bool isGenericTimerCommonEL0SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:984
gem5::ArmISA::MISCREG_CNTHCTL_EL2
@ MISCREG_CNTHCTL_EL2
Definition: misc.hh:773
gem5::ThreadContext::readVecReg
virtual const TheISA::VecRegContainer & readVecReg(const RegId &reg) const =0
gem5::ArmISA::MISCREG_CNTVOFF
@ MISCREG_CNTVOFF
Definition: misc.hh:433
gem5::ArmISA::MISCREG_DTLBIMVA
@ MISCREG_DTLBIMVA
Definition: misc.hh:331
gem5::ArmISA::getAff1
static RegVal getAff1(ArmSystem *arm_sys, ThreadContext *tc)
Definition: utility.cc:206
gem5::ArmSystem::multiProc
bool multiProc
true if this a multiprocessor system
Definition: system.hh:150
gem5::ArmISA::MISCREG_PRRR
@ MISCREG_PRRR
Definition: misc.hh:369
gem5::ArmISA::getAff2
static RegVal getAff2(ArmSystem *arm_sys, ThreadContext *tc)
Definition: utility.cc:200
gem5::ArmISA::MISCREG_DBGDRAR
@ MISCREG_DBGDRAR
Definition: misc.hh:170
gem5::ArmSystem::highestEL
ArmISA::ExceptionLevel highestEL() const
Returns the highest implemented exception level.
Definition: system.hh:187
gem5::VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:121
gem5::ThreadContext::socketId
virtual uint32_t socketId() const =0
interrupts.hh
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr()=0
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ArmISA::EC_UNKNOWN
@ EC_UNKNOWN
Definition: types.hh:296
gem5::ArmISA::MODE_HYP
@ MODE_HYP
Definition: types.hh:287
gem5::ArmISA::mcrrMrrc15Trap
Fault mcrrMrrc15Trap(const MiscRegIndex misc_reg, ExtMachInst mach_inst, ThreadContext *tc, uint32_t imm)
Definition: utility.cc:728
gem5::ArmISA::condGenericTimerPhysHypTrap
bool condGenericTimerPhysHypTrap(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:875
gem5::ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition: misc.hh:579
gem5::ArmISA::MISCREG_ID_AA64MMFR2_EL1
@ MISCREG_ID_AA64MMFR2_EL1
Definition: misc.hh:822
gem5::ArmISA::MISCREG_ID_ISAR2
@ MISCREG_ID_ISAR2
Definition: misc.hh:222
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::ArmISA::MISCREG_HDCR
@ MISCREG_HDCR
Definition: misc.hh:250
gem5::ArmISA::HaveVirtHostExt
bool HaveVirtHostExt(ThreadContext *tc)
Definition: utility.cc:232
gem5::ArmISA::MISCREG_ID_ISAR4
@ MISCREG_ID_ISAR4
Definition: misc.hh:224
gem5::PowerISA::ri
Bitfield< 1 > ri
Definition: misc.hh:120
gem5::ArmISA::roundPage
Addr roundPage(Addr addr)
Definition: utility.cc:502
gem5::ArmISA::rt
Bitfield< 15, 12 > rt
Definition: types.hh:115
gem5::ArmISA::MISCREG_MAIR1
@ MISCREG_MAIR1
Definition: misc.hh:378
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:268
gem5::ArmISA::MISCREG_CNTPCT
@ MISCREG_CNTPCT
Definition: misc.hh:414
gem5::ArmISA::MISCREG_SPSR_IRQ
@ MISCREG_SPSR_IRQ
Definition: misc.hh:64
gem5::ArmISA::MISCREG_SCTLR_EL2
@ MISCREG_SCTLR_EL2
Definition: misc.hh:584
gem5::ArmISA::unknownMode
static bool unknownMode(OperatingMode mode)
Definition: types.hh:412
gem5::ArmISA::EC_TRAPPED_CP15_MCRR_MRRC
@ EC_TRAPPED_CP15_MCRR_MRRC
Definition: types.hh:299
gem5::ArmISA::ELIs32
bool ELIs32(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:296
gem5::ArmISA::MISCREG_CCSIDR
@ MISCREG_CCSIDR
Definition: misc.hh:227
cpu.hh
gem5::ArmISA::syncVecElemsToRegs
void syncVecElemsToRegs(ThreadContext *tc)
Definition: utility.cc:1358
gem5::ArmISA::MISCREG_ICIALLUIS
@ MISCREG_ICIALLUIS
Definition: misc.hh:292
port_proxy.hh
gem5::ArmISA::MISCREG_DCCIMVAC
@ MISCREG_DCCIMVAC
Definition: misc.hh:317
gem5::ArmISA::getAffinity
RegVal getAffinity(ArmSystem *arm_sys, ThreadContext *tc)
Retrieves MPIDR_EL1.
Definition: utility.cc:218
gem5::ArmISA::tbid
Bitfield< 29 > tbid
Definition: misc_types.hh:538
gem5::ArmISA::EL2Enabled
bool EL2Enabled(ThreadContext *tc)
Definition: utility.cc:282
gem5::ArmISA::MISCREG_TEEHBR
@ MISCREG_TEEHBR
Definition: misc.hh:200
gem5::ArmISA::MISCREG_ACTLR
@ MISCREG_ACTLR
Definition: misc.hh:238
gem5::ArmISA::MISCREG_IFAR
@ MISCREG_IFAR
Definition: misc.hh:286
gem5::ArmISA::MISCREG_ICC_ASGI1R
@ MISCREG_ICC_ASGI1R
Definition: misc.hh:975
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition: pcstate.hh:63
gem5::ArmISA::MISCREG_ID_AFR0
@ MISCREG_ID_AFR0
Definition: misc.hh:214
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
compiler.hh
gem5::ArmISA::SPAlignmentCheckEnabled
bool SPAlignmentCheckEnabled(ThreadContext *tc)
Definition: utility.cc:1275
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:269
gem5::ArmISA::mcrMrc15TrapToHyp
bool mcrMrc15TrapToHyp(const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec)
Definition: utility.cc:518
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::ArmISA::MODE_USER
@ MODE_USER
Definition: types.hh:281
gem5::ArmISA::MISCREG_DBGPRCR
@ MISCREG_DBGPRCR
Definition: misc.hh:190
std::pair
STL pair class.
Definition: stl.hh:58
gem5::ArmISA::MISCREG_ID_PFR1
@ MISCREG_ID_PFR1
Definition: misc.hh:212
gem5::ArmISA::s1TranslationRegime
ExceptionLevel s1TranslationRegime(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:246
faults.hh
gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
Definition: misc.hh:570
gem5::ArmISA::debugTargetFrom
ExceptionLevel debugTargetFrom(ThreadContext *tc, bool secure)
Definition: utility.cc:92
gem5::ArmISA::MISCREG_ICC_SGI1R
@ MISCREG_ICC_SGI1R
Definition: misc.hh:1001
gem5::ArmISA::MISCREG_TCMTR
@ MISCREG_TCMTR
Definition: misc.hh:207
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::MISCREG_TLBIMVA
@ MISCREG_TLBIMVA
Definition: misc.hh:334
gem5::ArmISA::MISCREG_DBGOSDLR
@ MISCREG_DBGOSDLR
Definition: misc.hh:189
gem5::ArmISA::MISCREG_DFSR
@ MISCREG_DFSR
Definition: misc.hh:268
gem5::ArmISA::MISCREG_NMRR
@ MISCREG_NMRR
Definition: misc.hh:375
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmISA::MISCREG_CNTP_TVAL_EL0
@ MISCREG_CNTP_TVAL_EL0
Definition: misc.hh:758
gem5::ArmISA::MISCREG_TTBR1
@ MISCREG_TTBR1
Definition: misc.hh:257
gem5::ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:73
gem5::ArmISA::ELStateUsingAArch32K
std::pair< bool, bool > ELStateUsingAArch32K(ThreadContext *tc, ExceptionLevel el, bool secure)
Definition: utility.cc:335
gem5::ArmISA::MISCREG_ID_AA64ISAR1_EL1
@ MISCREG_ID_AA64ISAR1_EL1
Definition: misc.hh:568
utility.hh
gem5::ArmISA::ExceptionClass
ExceptionClass
Definition: types.hh:293
full_system.hh
gem5::ArmISA::MISCREG_MAIR0
@ MISCREG_MAIR0
Definition: misc.hh:372
gem5::ArmISA::currEL
ExceptionLevel currEL(const ThreadContext *tc)
Returns the current Exception Level (EL) of the provided ThreadContext.
Definition: utility.cc:128
gem5::ThreadContext::readVecElem
virtual RegVal readVecElem(const RegId &reg) const =0
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::ArmISA::MISCREG_TLBIASIDIS
@ MISCREG_TLBIASIDIS
Definition: misc.hh:323
gem5::System::multiThread
const bool multiThread
Definition: system.hh:316
gem5::ArmSystem::has
bool has(ArmExtension ext) const
Definition: system.hh:154
gem5::ArmISA::MISCREG_AIDR
@ MISCREG_AIDR
Definition: misc.hh:229
gem5::ArmISA::MISCREG_ICC_SGI0R
@ MISCREG_ICC_SGI0R
Definition: misc.hh:1000
gem5::ArmISA::IsSecureEL2Enabled
bool IsSecureEL2Enabled(ThreadContext *tc)
Definition: utility.cc:268
gem5::ArmISA::MISCREG_AIFSR
@ MISCREG_AIFSR
Definition: misc.hh:277
gem5::ArmISA::MISCREG_DCIMVAC
@ MISCREG_DCIMVAC
Definition: misc.hh:302
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:266
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
gem5::ArmISA::MISCREG_CTR
@ MISCREG_CTR
Definition: misc.hh:206
gem5::ArmSystem
Definition: system.hh:91
gem5::ArmISA::imm
Bitfield< 7, 0 > imm
Definition: types.hh:132
gem5::ArmISA::MISCREG_TEECR
@ MISCREG_TEECR
Definition: misc.hh:198
gem5::ArmISA::MISCREG_DTLBIALL
@ MISCREG_DTLBIALL
Definition: misc.hh:330
gem5::ArmISA::MISCREG_HCR
@ MISCREG_HCR
Definition: misc.hh:248
gem5::ArmISA::MISCREG_ADFSR
@ MISCREG_ADFSR
Definition: misc.hh:274
inform
#define inform(...)
Definition: logging.hh:247
gem5::ArmISA::syncVecRegsToElems
void syncVecRegsToElems(ThreadContext *tc)
Definition: utility.cc:1345
gem5::ArmISA::decodeMrsMsrBankedReg
bool decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx, CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
Definition: utility.cc:1141
gem5::ArmISA::MISCREG_SPSR_SVC
@ MISCREG_SPSR_SVC
Definition: misc.hh:65
gem5::ArmISA::isUnpriviledgeAccess
bool isUnpriviledgeAccess(ThreadContext *tc)
Definition: utility.cc:1258
base.hh
gem5::ArmISA::VecElem
uint32_t VecElem
Definition: vec.hh:60
gem5::ArmISA::MISCREG_CLIDR
@ MISCREG_CLIDR
Definition: misc.hh:228
gem5::ArmISA::getAff0
static RegVal getAff0(ArmSystem *arm_sys, ThreadContext *tc)
Definition: utility.cc:212
gem5::ArmISA::isGenericTimerSystemAccessTrapEL3
bool isGenericTimerSystemAccessTrapEL3(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:1125
gem5::ArmISA::MISCREG_TLBIMVAALIS
@ MISCREG_TLBIMVAALIS
Definition: misc.hh:326
gem5::ArmISA::sendEvent
void sendEvent(ThreadContext *tc)
Send an event (SEV) to a specific PE if there isn't already a pending event.
Definition: utility.cc:64
gem5::ArmISA::ELStateUsingAArch32
bool ELStateUsingAArch32(ThreadContext *tc, ExceptionLevel el, bool secure)
Definition: utility.cc:386
gem5::ArmISA::MISCREG_DBGOSLSR
@ MISCREG_DBGOSLSR
Definition: misc.hh:188
gem5::ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition: misc.hh:243
gem5::ArmISA::longDescFormatInUse
bool longDescFormatInUse(ThreadContext *tc)
Definition: utility.cc:135
gem5::ArmISA::MISCREG_ID_PFR0
@ MISCREG_ID_PFR0
Definition: misc.hh:211
gem5::ArmISA::MODE_SYSTEM
@ MODE_SYSTEM
Definition: types.hh:289
gem5::ArmISA::PageBytes
const Addr PageBytes
Definition: page_size.hh:53
gem5::ThreadContext::setVecElem
virtual void setVecElem(const RegId &reg, RegVal val)=0
gem5::ArmISA::MISCREG_VMPIDR_EL2
@ MISCREG_VMPIDR_EL2
Definition: misc.hh:578
gem5::ArmISA::HaveSecureEL2Ext
bool HaveSecureEL2Ext(ThreadContext *tc)
Definition: utility.cc:261
gem5::ArmISA::MISCREG_REVIDR
@ MISCREG_REVIDR
Definition: misc.hh:210
gem5::ArmISA::badMode32
bool badMode32(ThreadContext *tc, OperatingMode mode)
badMode is checking if the execution mode provided as an argument is valid and implemented for AArch3...
Definition: utility.cc:412
gem5::ArmISA::MISCREG_SPSR_ABT
@ MISCREG_SPSR_ABT
Definition: misc.hh:67
gem5::ArmISA::MISCREG_ELR_HYP
@ MISCREG_ELR_HYP
Definition: misc.hh:70
gem5::MipsISA::r
r
Definition: pra_constants.hh:98
gem5::ArmISA::haveAArch32EL
bool haveAArch32EL(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:321
gem5::ArmISA::isGenericTimerVirtSystemAccessTrapEL2
bool isGenericTimerVirtSystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:1046
gem5::ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
gem5::ArmISA::MISCREG_SEV_MAILBOX
@ MISCREG_SEV_MAILBOX
Definition: misc.hh:92
gem5::ThreadContext::threadId
virtual int threadId() const =0
gem5::ArmISA::MISCREG_ID_ISAR6
@ MISCREG_ID_ISAR6
Definition: misc.hh:226
gem5::ArmISA::MISCREG_CNTP_TVAL_S
@ MISCREG_CNTP_TVAL_S
Definition: misc.hh:424
gem5::ArmISA::condGenericTimerPhysEL1SystemAccessTrapEL2
bool condGenericTimerPhysEL1SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:1117
page_size.hh
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:61
gem5::ArmISA::MISCREG_CNTFRQ_EL0
@ MISCREG_CNTFRQ_EL0
Definition: misc.hh:753
gem5::ArmISA::MISCREG_TLBIMVAIS
@ MISCREG_TLBIMVAIS
Definition: misc.hh:322
gem5::ArmSystem::haveEL
static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el)
Return true if the system implements a specific exception level.
Definition: system.cc:131
gem5::ArmISA::MODE_ABORT
@ MODE_ABORT
Definition: types.hh:286
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: misc.hh:586
gem5::ArmISA::condGenericTimerCommonEL1SystemAccessTrapEL2
bool condGenericTimerCommonEL1SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:1083
gem5::ArmISA::MISCREG_TLBIASID
@ MISCREG_TLBIASID
Definition: misc.hh:335
gem5::ArmISA::MISCREG_TLBIMVAA
@ MISCREG_TLBIMVAA
Definition: misc.hh:336
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::ArmISA::MISCREG_ID_AA64PFR0_EL1
@ MISCREG_ID_AA64PFR0_EL1
Definition: misc.hh:561
gem5::ArmISA::MISCREG_TLBIMVAAIS
@ MISCREG_TLBIMVAAIS
Definition: misc.hh:324
gem5::ArmISA::computeAddrTop
int computeAddrTop(ThreadContext *tc, bool selbit, bool is_instr, TCR tcr, ExceptionLevel el)
Definition: utility.cc:424
gem5::ArmISA::isGenericTimerPhysHypTrap
bool isGenericTimerPhysHypTrap(const MiscRegIndex misc_reg, ThreadContext *tc, ExceptionClass *ec)
Definition: utility.cc:868
gem5::ArmISA::MISCREG_CNTV_CTL
@ MISCREG_CNTV_CTL
Definition: misc.hh:425
gem5::ArmISA::isBigEndian64
bool isBigEndian64(const ThreadContext *tc)
Definition: utility.cc:394
gem5::ArmISA::isAArch64AArch32SystemAccessTrapEL1
bool isAArch64AArch32SystemAccessTrapEL1(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:812
gem5::ThreadContext::setVecReg
virtual void setVecReg(const RegId &reg, const TheISA::VecRegContainer &val)=0
gem5::ArmISA::MISCREG_ID_MMFR0
@ MISCREG_ID_MMFR0
Definition: misc.hh:215
int.hh
gem5::ArmISA::MISCREG_CPACR
@ MISCREG_CPACR
Definition: misc.hh:241
gem5::ArmISA::MISCREG_SPSR_HYP
@ MISCREG_SPSR_HYP
Definition: misc.hh:68
gem5::ArmISA::isGenericTimerPhysEL0SystemAccessTrapEL2
bool isGenericTimerPhysEL0SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:997
thread_context.hh
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:272
gem5::ArmISA::readMPIDR
RegVal readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
This helper function is either returing the value of MPIDR_EL1 (by calling getMPIDR),...
Definition: utility.cc:142
gem5::ArmISA::MISCREG_ID_DFR0
@ MISCREG_ID_DFR0
Definition: misc.hh:213
gem5::ArmISA::MISCREG_ITLBIALL
@ MISCREG_ITLBIALL
Definition: misc.hh:327
gem5::ArmISA::unflattenMiscReg
int unflattenMiscReg(int reg)
Definition: misc.cc:1365
gem5::ArmISA::getMPIDR
RegVal getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
This helper function is returning the value of MPIDR_EL1.
Definition: utility.cc:170
gem5::ArmISA::MISCREG_TCR_EL1
@ MISCREG_TCR_EL1
Definition: misc.hh:601
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:113
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::ArmISA::INT_SEV
@ INT_SEV
Definition: interrupts.hh:64
gem5::ArmISA::MISCREG_CNTV_TVAL_EL0
@ MISCREG_CNTV_TVAL_EL0
Definition: misc.hh:761
gem5::ArmISA::MISCREG_SPSR_UND
@ MISCREG_SPSR_UND
Definition: misc.hh:69
gem5::ArmISA::mcrMrcIssExtract
static void mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt, uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
Definition: utility.hh:241

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